640 lines
18 KiB
NASM
640 lines
18 KiB
NASM
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;++
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;
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;Copyright (c) 1991 Microsoft Corporation
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;
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;Module Name:
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;
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; ixsysint.asm
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;
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;Abstract:
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;
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; This module implements the HAL routines to enable/disable system
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; interrupts.
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;
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;Author:
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;
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; John Vert (jvert) 22-Jul-1991
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;
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;Environment:
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;
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; Kernel Mode
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;
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;Revision History:
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc ; calling convention macros
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include i386\ix8259.inc
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include i386\kimacro.inc
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include mac386.inc
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.list
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extrn KiI8259MaskTable:DWORD
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EXTRNP _KeBugCheck,1,IMPORT
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ifdef IRQL_METRICS
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extrn HalPostponedIntCount:dword
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endif
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extrn _HalpEisaELCR:dword ; Set bit indicates LEVEL
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extrn _HalpEisaIrqIgnore:dword
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extrn SWInterruptHandlerTable:dword
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extrn _HalpIrqMiniportInitialized:dword
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extrn HalpHardwareInterruptLevel:proc
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extrn _PciirqmpGetTrigger@4:proc
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extrn _PciirqmpSetTrigger@4:proc
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;
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; Constants used to initialize CMOS/Real Time Clock
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;
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CMOS_CONTROL_PORT EQU 70h ; command port for cmos
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CMOS_DATA_PORT EQU 71h ; cmos data port
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;
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; Macros to Read/Write/Reset CMOS to initialize RTC
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;
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; CMOS_READ
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;
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; Description: This macro read a byte from the CMOS register specified
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; in (AL).
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;
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; Parameter: (AL) = address/register to read
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; Return: (AL) = data
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;
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CMOS_READ MACRO
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OUT CMOS_CONTROL_PORT,al ; ADDRESS LOCATION AND DISABLE NMI
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IODelay ; I/O DELAY
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IN AL,CMOS_DATA_PORT ; READ IN REQUESTED CMOS DATA
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IODelay ; I/O DELAY
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ENDM
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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align dword
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;
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; HalDismissSystemInterrupt does an indirect jump through this table so it
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; can quickly execute specific code for different interrupts.
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;
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public HalpSpecialDismissTable
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HalpSpecialDismissTable label dword
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dd offset FLAT:HalpDismissNormal ; irq 0
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dd offset FLAT:HalpDismissNormal ; irq 1
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dd offset FLAT:HalpDismissNormal ; irq 2
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dd offset FLAT:HalpDismissNormal ; irq 3
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dd offset FLAT:HalpDismissNormal ; irq 4
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dd offset FLAT:HalpDismissNormal ; irq 5
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dd offset FLAT:HalpDismissNormal ; irq 6
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dd offset FLAT:HalpDismissIrq07 ; irq 7
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dd offset FLAT:HalpDismissNormal ; irq 8
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dd offset FLAT:HalpDismissNormal ; irq 9
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dd offset FLAT:HalpDismissNormal ; irq A
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dd offset FLAT:HalpDismissNormal ; irq B
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dd offset FLAT:HalpDismissNormal ; irq C
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dd offset FLAT:HalpDismissIrq0d ; irq D
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dd offset FLAT:HalpDismissNormal ; irq E
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dd offset FLAT:HalpDismissIrq0f ; irq F
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dd offset FLAT:HalpDismissNormal ; irq 10
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dd offset FLAT:HalpDismissNormal ; irq 11
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dd offset FLAT:HalpDismissNormal ; irq 12
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dd offset FLAT:HalpDismissNormal ; irq 13
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dd offset FLAT:HalpDismissNormal ; irq 14
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dd offset FLAT:HalpDismissNormal ; irq 15
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dd offset FLAT:HalpDismissNormal ; irq 16
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dd offset FLAT:HalpDismissNormal ; irq 17
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dd offset FLAT:HalpDismissNormal ; irq 18
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dd offset FLAT:HalpDismissNormal ; irq 19
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dd offset FLAT:HalpDismissNormal ; irq 1A
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dd offset FLAT:HalpDismissNormal ; irq 1B
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dd offset FLAT:HalpDismissNormal ; irq 1C
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dd offset FLAT:HalpDismissNormal ; irq 1D
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dd offset FLAT:HalpDismissNormal ; irq 1E
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dd offset FLAT:HalpDismissNormal ; irq 1F
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dd offset FLAT:HalpDismissNormal ; irq 20
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dd offset FLAT:HalpDismissNormal ; irq 21
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dd offset FLAT:HalpDismissNormal ; irq 22
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dd offset FLAT:HalpDismissNormal ; irq 23
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_DATA ENDS
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_TEXT SEGMENT DWORD PUBLIC 'DATA'
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public HalpSpecialDismissLevelTable
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HalpSpecialDismissLevelTable label dword
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dd offset FLAT:HalpDismissLevel ; irq 0
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dd offset FLAT:HalpDismissLevel ; irq 1
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dd offset FLAT:HalpDismissLevel ; irq 2
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dd offset FLAT:HalpDismissLevel ; irq 3
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dd offset FLAT:HalpDismissLevel ; irq 4
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dd offset FLAT:HalpDismissLevel ; irq 5
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dd offset FLAT:HalpDismissLevel ; irq 6
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dd offset FLAT:HalpDismissIrq07Level ; irq 7
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dd offset FLAT:HalpDismissLevel ; irq 8
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dd offset FLAT:HalpDismissLevel ; irq 9
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dd offset FLAT:HalpDismissLevel ; irq A
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dd offset FLAT:HalpDismissLevel ; irq B
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dd offset FLAT:HalpDismissLevel ; irq C
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dd offset FLAT:HalpDismissIrq0dLevel ; irq D
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dd offset FLAT:HalpDismissLevel ; irq E
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dd offset FLAT:HalpDismissIrq0fLevel ; irq F
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_TEXT ENDS
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_TEXT$01 SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;BOOLEAN
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;HalBeginSystemInterrupt(
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; IN KIRQL Irql
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; IN CCHAR Vector,
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; OUT PKIRQL OldIrql
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; )
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;
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;
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;
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;Routine Description:
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;
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; This routine is used to dismiss the specified vector number. It is called
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; before any interrupt service routine code is executed.
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;
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; N.B. This routine does NOT preserve EAX or EBX
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;
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; On a UP machine the interrupt dismissed at BeginSystemInterrupt time.
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; This is fine since the irql is being raise to mask it off.
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; HalEndSystemInterrupt is simply a LowerIrql request.
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;
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;
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;Arguments:
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;
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; Irql - Supplies the IRQL to raise to
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;
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; Vector - Supplies the vector of the interrupt to be dismissed
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;
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; OldIrql- Location to return OldIrql
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;
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;
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;Return Value:
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;
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; FALSE - Interrupt is spurious and should be ignored
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;
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; TRUE - Interrupt successfully dismissed and Irql raised.
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;
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;--
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align dword
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HbsiIrql equ byte ptr [esp+4]
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HbsiVector equ byte ptr [esp+8]
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HbsiOldIrql equ dword ptr [esp+12]
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cPublicProc _HalBeginSystemInterrupt ,3
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.FPO ( 0, 3, 0, 0, 0, 0 )
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xor ecx, ecx
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mov cl, HbsiVector ; (ecx) = System Vector
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sub ecx, PRIMARY_VECTOR_BASE ; (ecx) = 8259 IRQ #
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if DBG
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cmp ecx, 1fh
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jbe hbsi00
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int 3
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hbsi00:
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endif
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jmp HalpSpecialDismissTable[ecx*4]
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HalpDismissIrq0f:
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;
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; Check to see if this is a spurious interrupt
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;
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mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
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out PIC2_PORT0, al
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IODelay ; delay
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in al, PIC2_PORT0 ; (al) = content of PIC 1 ISR
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test al, 10000000B ; Is In-Service register set?
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jnz short HalpDismissNormal ; No, this is NOT a spurious int,
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; go do the normal interrupt stuff
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HalpIrq0fSpurious:
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;
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; This is a spurious interrupt.
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; Because the slave PIC is cascaded to irq2 of master PIC, we need to
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; dismiss the interupt on master PIC's irq2.
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;
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mov al, PIC2_EOI ; Specific eoi to master for pic2 eoi
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out PIC1_PORT0, al ; send irq2 specific eoi to master
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mov eax,0 ; return FALSE
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stdRET _HalBeginSystemInterrupt
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HalpDismissIrq07:
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;
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; Check to see if this is a spurious interrupt
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;
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mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
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out PIC1_PORT0, al
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IODelay ; delay
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in al, PIC1_PORT0 ; (al) = content of PIC 1 ISR
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test al, 10000000B ; Is In-Service register set?
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jnz HalpDismissNormal ; No, so this is NOT a spurious int
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mov eax, 0 ; return FALSE
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stdRET _HalBeginSystemInterrupt
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HalpDismissIrq0d:
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;
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; Clear the NPX busy latch.
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;
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xor al,al
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out I386_80387_BUSY_PORT, al
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align 4
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HalpDismissNormal:
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;
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; Raise IRQL to requested level
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;
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xor ebx,ebx
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mov al, HbsiIrql ; (al) = New irql
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; (ecx) = IRQ #
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mov bl, PCR[PcIrql] ; (ebx) = Current Irql
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;
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; Now we check to make sure the Irql of this interrupt > current Irql.
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; If it is not, we dismiss it as spurious and set the appropriate bit
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; in the IRR so we can dispatch the interrupt when Irql is lowered
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;
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cmp al, bl
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jbe Hdsi300
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mov PCR[PcIrql], al ; set new Irql
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mov edx, HbsiOldIrql ; save current irql to OldIrql variable
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mov byte ptr [edx], bl
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;
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; Dismiss interrupt.
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;
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mov eax, ecx ; (eax) = IRQ #
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cmp eax, 8 ; EOI to master or slave?
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jae short Hbsi100 ; EIO to both master and slave
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or al, PIC1_EOI_MASK ; create specific eoi mask for master
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out PIC1_PORT0, al ; dismiss the interrupt
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sti
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mov eax, 1 ; return TRUE
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stdRET _HalBeginSystemInterrupt
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align 4
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Hbsi100:
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add al, OCW2_SPECIFIC_EOI - 8 ; specific eoi to slave
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out PIC2_PORT0, al
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mov al, PIC2_EOI ; specific eoi to master for pic2 eoi
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out PIC1_PORT0, al ; send irq2 specific eoi to master
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sti
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mov eax, 1 ; return TRUE
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stdRET _HalBeginSystemInterrupt
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align 4
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Hdsi300:
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;
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; An interrupt has come in at a lower Irql, so we dismiss it as spurious and
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; set the appropriate bit in the IRR so that KeLowerIrql knows to dispatch
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; it when Irql is lowered.
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;
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; (ecx) = 8259 IRQ#
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; (al) = New Irql
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; (ebx) = Current Irql
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;
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mov eax, 1
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add ecx, 4 ; (ecx) = Irq # + 4
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shl eax, cl
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or PCR[PcIRR], eax
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;
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; Raise Irql to prevent it from happening again
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;
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;
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; Get the PIC masks for Irql
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;
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mov eax, KiI8259MaskTable[ebx*4]
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or eax, PCR[PcIDR]
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;
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; Write the new interrupt mask register back to the 8259
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;
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SET_8259_MASK
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Hbsi390:
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ifdef IRQL_METRICS
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lock inc HalPostponedIntCount
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endif
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xor eax, eax ; return FALSE, spurious interrupt
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stdRET _HalBeginSystemInterrupt
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HalpDismissIrq0fLevel:
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;
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; Check to see if this is a spurious interrupt
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;
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mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
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out PIC2_PORT0, al
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IODelay ; delay
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in al, PIC2_PORT0 ; (al) = content of PIC 1 ISR
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test al, 10000000B ; Is In-Service register set?
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jnz short HalpDismissLevel ; No, this is NOT a spurious int,
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; go do the normal interrupt stuff
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jmp HalpIrq0fSpurious
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HalpDismissIrq07Level:
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;
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; Check to see if this is a spurious interrupt
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;
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mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
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out PIC1_PORT0, al
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IODelay ; delay
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in al, PIC1_PORT0 ; (al) = content of PIC 1 ISR
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test al, 10000000B ; Is In-Service register set?
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jnz short HalpDismissLevel ; No, so this is NOT a spurious int
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mov eax, 0 ; return FALSE
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stdRET _HalBeginSystemInterrupt
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HalpDismissIrq0dLevel:
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;
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; Clear the NPX busy latch.
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;
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xor al,al
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out I386_80387_BUSY_PORT, al
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align 4
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HalpDismissLevel:
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;
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; Mask this level interrupt off
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|
|
; (ecx) = 8259 IRQ#
|
||
|
|
;
|
||
|
|
mov al, HbsiIrql ; (al) = New irql
|
||
|
|
mov eax, KiI8259MaskTable[eax*4] ; get 8259's masks
|
||
|
|
or eax, PCR[PcIDR] ; mask disabled irqs
|
||
|
|
SET_8259_MASK ; send mask to 8259s
|
||
|
|
;
|
||
|
|
; The SWInterruptHandler for this vector has been set to a NOP.
|
||
|
|
; Set the vector's IRR so that Lower Irql will clear the 8259 mask for this
|
||
|
|
; Irq when the irql is lowered below this level.
|
||
|
|
;
|
||
|
|
mov eax, ecx ; (eax) = Irq #
|
||
|
|
mov ebx, 1
|
||
|
|
add ecx, 4 ; (ecx) = Irq # + 4
|
||
|
|
shl ebx, cl
|
||
|
|
or PCR[PcIRR], ebx
|
||
|
|
|
||
|
|
;
|
||
|
|
; Dismiss interrupt. Current interrupt is already masked off.
|
||
|
|
; Then check to make sure the Irql of this interrupt > current Irql.
|
||
|
|
; If it is not, we dismiss it as spurious - since this is a level interrupt
|
||
|
|
; when the 8259's are unmasked the interrupt will reoccur
|
||
|
|
;
|
||
|
|
mov cl, HbsiIrql
|
||
|
|
mov bl, PCR[PcIrql]
|
||
|
|
mov edx, HbsiOldIrql
|
||
|
|
|
||
|
|
cmp eax, 8 ; EOI to master or slave?
|
||
|
|
jae short Hbsi450 ; EIO to both master and slave
|
||
|
|
|
||
|
|
or al, PIC1_EOI_MASK ; create specific eoi mask for master
|
||
|
|
out PIC1_PORT0, al ; dismiss the interrupt
|
||
|
|
|
||
|
|
cmp cl, bl
|
||
|
|
jbe short Hbsi390 ; Spurious?
|
||
|
|
|
||
|
|
mov PCR[PcIrql], cl ; raise to new irql
|
||
|
|
mov byte ptr [edx], bl ; return old irql
|
||
|
|
sti
|
||
|
|
mov eax, 1 ; return TRUE
|
||
|
|
stdRET _HalBeginSystemInterrupt
|
||
|
|
|
||
|
|
align 4
|
||
|
|
Hbsi450:
|
||
|
|
add al, OCW2_SPECIFIC_EOI - 8 ; specific eoi to slave
|
||
|
|
out PIC2_PORT0, al
|
||
|
|
mov al, PIC2_EOI ; specific eoi to master for pic2 eoi
|
||
|
|
out PIC1_PORT0, al ; send irq2 specific eoi to master
|
||
|
|
|
||
|
|
cmp cl, bl
|
||
|
|
jbe Hbsi390 ; Spurious?
|
||
|
|
|
||
|
|
mov PCR[PcIrql], cl ; raise to new irql
|
||
|
|
mov byte ptr [edx], bl ; return old irql
|
||
|
|
sti
|
||
|
|
mov eax, 1 ; return TRUE
|
||
|
|
stdRET _HalBeginSystemInterrupt
|
||
|
|
|
||
|
|
stdENDP _HalBeginSystemInterrupt
|
||
|
|
|
||
|
|
|
||
|
|
;++
|
||
|
|
;VOID
|
||
|
|
;HalDisableSystemInterrupt(
|
||
|
|
; IN CCHAR Vector,
|
||
|
|
; IN KIRQL Irql
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
;
|
||
|
|
;
|
||
|
|
;Routine Description:
|
||
|
|
;
|
||
|
|
; Disables a system interrupt.
|
||
|
|
;
|
||
|
|
;Arguments:
|
||
|
|
;
|
||
|
|
; Vector - Supplies the vector of the interrupt to be disabled
|
||
|
|
;
|
||
|
|
; Irql - Supplies the interrupt level of the interrupt to be disabled
|
||
|
|
;
|
||
|
|
;Return Value:
|
||
|
|
;
|
||
|
|
; None.
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
cPublicProc _HalDisableSystemInterrupt ,2
|
||
|
|
.FPO ( 0, 2, 0, 0, 0, 0 )
|
||
|
|
|
||
|
|
;
|
||
|
|
|
||
|
|
movzx ecx, byte ptr [esp+4] ; (ecx) = Vector
|
||
|
|
sub ecx, PRIMARY_VECTOR_BASE ; (ecx) = 8259 irq #
|
||
|
|
mov edx, 1
|
||
|
|
shl edx, cl ; (ebx) = bit in IMR to disable
|
||
|
|
cli
|
||
|
|
or PCR[PcIDR], edx
|
||
|
|
xor eax, eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Get the current interrupt mask register from the 8259
|
||
|
|
;
|
||
|
|
in al, PIC2_PORT1
|
||
|
|
shl eax, 8
|
||
|
|
in al, PIC1_PORT1
|
||
|
|
;
|
||
|
|
; Mask off the interrupt to be disabled
|
||
|
|
;
|
||
|
|
or eax, edx
|
||
|
|
;
|
||
|
|
; Write the new interrupt mask register back to the 8259
|
||
|
|
;
|
||
|
|
out PIC1_PORT1, al
|
||
|
|
shr eax, 8
|
||
|
|
out PIC2_PORT1, al
|
||
|
|
PIC2DELAY
|
||
|
|
|
||
|
|
sti
|
||
|
|
stdRET _HalDisableSystemInterrupt
|
||
|
|
|
||
|
|
stdENDP _HalDisableSystemInterrupt
|
||
|
|
|
||
|
|
;++
|
||
|
|
;
|
||
|
|
;BOOLEAN
|
||
|
|
;HalEnableSystemInterrupt(
|
||
|
|
; IN ULONG Vector,
|
||
|
|
; IN KIRQL Irql,
|
||
|
|
; IN KINTERRUPT_MODE InterruptMode
|
||
|
|
; )
|
||
|
|
;
|
||
|
|
;
|
||
|
|
;Routine Description:
|
||
|
|
;
|
||
|
|
; Enables a system interrupt
|
||
|
|
;
|
||
|
|
;Arguments:
|
||
|
|
;
|
||
|
|
; Vector - Supplies the vector of the interrupt to be enabled
|
||
|
|
;
|
||
|
|
; Irql - Supplies the interrupt level of the interrupt to be enabled.
|
||
|
|
;
|
||
|
|
;Return Value:
|
||
|
|
;
|
||
|
|
; None.
|
||
|
|
;
|
||
|
|
;--
|
||
|
|
cPublicProc _HalEnableSystemInterrupt ,3
|
||
|
|
.FPO ( 0, 3, 0, 0, 0, 0 )
|
||
|
|
|
||
|
|
movzx ecx, byte ptr [esp+4] ; (ecx) = vector
|
||
|
|
sub ecx, PRIMARY_VECTOR_BASE
|
||
|
|
jc hes_error
|
||
|
|
cmp ecx, CLOCK2_LEVEL
|
||
|
|
jnc hes_error
|
||
|
|
|
||
|
|
|
||
|
|
;
|
||
|
|
; Use the IRQ miniport to get the HW state.
|
||
|
|
;
|
||
|
|
cmp _HalpIrqMiniportInitialized, 0
|
||
|
|
jz hes_noMPGet
|
||
|
|
|
||
|
|
|
||
|
|
push ecx
|
||
|
|
lea eax, _HalpEisaELCR
|
||
|
|
push eax
|
||
|
|
call _PciirqmpGetTrigger@4
|
||
|
|
pop ecx
|
||
|
|
|
||
|
|
hes_noMPGet:
|
||
|
|
|
||
|
|
bt _HalpEisaIrqIgnore,ecx ;;Is this Eisa Ignore bit set?
|
||
|
|
jc short hes_ProgPic
|
||
|
|
;
|
||
|
|
; Clear or set the edge\level mask bit depending on what the caller wants.
|
||
|
|
;
|
||
|
|
btr _HalpEisaELCR, ecx
|
||
|
|
mov al, [esp+12]
|
||
|
|
cmp al, 0
|
||
|
|
jnz short hes_edge
|
||
|
|
|
||
|
|
bt _HalpEisaELCR, ecx
|
||
|
|
jc short @F
|
||
|
|
|
||
|
|
; Caller wants level triggered interrupts
|
||
|
|
; if IRQ routing is turned on, try and provide it
|
||
|
|
cmp _HalpIrqMiniportInitialized, 0
|
||
|
|
jz short @F
|
||
|
|
bts _HalpEisaELCR, ecx
|
||
|
|
|
||
|
|
|
||
|
|
@@:
|
||
|
|
mov SWInterruptHandlerTable+4*4[ecx*4], offset HalpHardwareInterruptLevel
|
||
|
|
|
||
|
|
mov edx, HalpSpecialDismissLevelTable[ecx*4]
|
||
|
|
mov HalpSpecialDismissTable[ecx*4], edx
|
||
|
|
|
||
|
|
hes_edge:
|
||
|
|
cmp _HalpIrqMiniportInitialized, 0
|
||
|
|
jz hes_ProgPIC
|
||
|
|
;
|
||
|
|
; Program the HW to make it match the callers request.
|
||
|
|
;
|
||
|
|
mov eax, _HalpEisaELCR
|
||
|
|
|
||
|
|
push ecx
|
||
|
|
push eax
|
||
|
|
call _PciirqmpSetTrigger@4
|
||
|
|
pop ecx
|
||
|
|
|
||
|
|
if 0
|
||
|
|
.err
|
||
|
|
|
||
|
|
;;
|
||
|
|
;; We can't just arbitrarily blast ports. This makes machines do really weird things
|
||
|
|
;;
|
||
|
|
hes_noMPSet:
|
||
|
|
mov edx, 4d0h
|
||
|
|
out dx, al
|
||
|
|
inc edx
|
||
|
|
mov al, ah
|
||
|
|
out dx, al
|
||
|
|
endif
|
||
|
|
|
||
|
|
|
||
|
|
hes_ProgPIC:
|
||
|
|
|
||
|
|
mov eax, 1
|
||
|
|
shl eax, cl ; (ebx) = bit in IMR to enable
|
||
|
|
not eax
|
||
|
|
|
||
|
|
cli
|
||
|
|
and PCR[PcIDR], eax
|
||
|
|
|
||
|
|
;
|
||
|
|
; Get the PIC masks for Irql 0
|
||
|
|
;
|
||
|
|
mov eax, KiI8259MaskTable[0]
|
||
|
|
or eax, PCR[PcIDR]
|
||
|
|
;
|
||
|
|
; Write the new interrupt mask register back to the 8259
|
||
|
|
;
|
||
|
|
SET_8259_MASK
|
||
|
|
|
||
|
|
sti
|
||
|
|
mov eax, 1 ; return TRUE
|
||
|
|
stdRET _HalEnableSystemInterrupt
|
||
|
|
|
||
|
|
hes_error:
|
||
|
|
if DBG
|
||
|
|
int 3
|
||
|
|
endif
|
||
|
|
xor eax, eax ; FALSE
|
||
|
|
stdRET _HalEnableSystemInterrupt
|
||
|
|
|
||
|
|
stdENDP _HalEnableSystemInterrupt
|
||
|
|
|
||
|
|
|
||
|
|
_TEXT$01 ENDS
|
||
|
|
|
||
|
|
END
|