79 lines
4 KiB
PHP
79 lines
4 KiB
PHP
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; INS8250 ACE Register Offsets And Bit Definitions
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ACE_RBR equ 0 ;Receiver Buffer
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ACE_THR equ 0 ;Transmit Holding Register
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ACE_IER equ 1 ;Interrupt Enable
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ACE_ERBFI equ 00000001b ; Received Data Available
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ACE_ETBEI equ 00000010b ; Transmitter Holding Register Empty
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ACE_ELSI equ 00000100b ; Receiver Line Status
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ACE_EDSSI equ 00001000b ; Modem Status
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ACE_FCR equ 2 ;FIFO control register
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ACE_EFIFO equ 00000001b ; Enable FIFO
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ACE_CRFIFO equ 00000010b ; Clear receive FIFO queue
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ACE_CTFIFO equ 00000100b ; Clear transmit FIFO queue
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ACE_TRIG01 equ 00000000b ; Trigger receive int on every char
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ACE_TRIG04 equ 01000000b ; Trigger receive int on every 4th char
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ACE_TRIG08 equ 10000000b ; Trigger receive int on every 8th char
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ACE_TRIG14 equ 11000000b ; Trigger receive int on every 14th char
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ACE_IIDR equ 2 ;Interrupt Identification
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ACE_IIP equ 00000001b ; Inverted Interrupt Pending (0=int)
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ACE_IID equ 00000110b ; Interrupt ID
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ACE_MSI equ 00000000b ; Modem Status
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ACE_THREI equ 00000010b ; Transmitter Holding Register Empty
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ACE_RDAI equ 00000100b ; Received Data Available
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ACE_RLSI equ 00000110b ; Receiver Line Status
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ACE_FIFO_E1 equ 01000000b ;set, if FIFO enabled on 16550A
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ACE_FIFO_E2 equ 10000000b ;set, if FIFO enabled on 16550 or 16550A
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ACE_LCR equ 3 ;Line Control
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ACE_WLS equ 00000011b ; Word Length Select Bits
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ACE_WLS0 equ 00000001b ; Word Length Select Bit 0
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ACE_WLS1 equ 00000010b ; Word Length Select Bit 1
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ACE_5BW equ 00000000b ; 5 Bit Words
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ACE_6BW equ 00000001b ; 6 Bit Words
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ACE_7BW equ 00000010b ; 7 Bit Words
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ACE_8BW equ 00000011b ; 8 Bit Words
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ACE_STB equ 00000100b ; Stop Bits
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ACE_1SB equ 00000000b ; 1 Stop Bits (1.5 for 5 bit words)
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ACE_2SB equ 00000100b ; 2 Stop Bits
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ACE_PEN equ 00001000b ; Parity Enable
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ACE_PSB equ 00110000b ; Parity select bits
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ACE_EPS equ 00010000b ; Even Parity Select
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ACE_SP equ 00100000b ; Stick Parity
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ACE_SB equ 01000000b ; Set Break
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ACE_DLAB equ 10000000b ; Divisor Latch Access Bit
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ACE_MCR equ 4 ;Modem Control
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ACE_DTR equ 00000001b ; Data Terminal ready
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ACE_RTS equ 00000010b ; Request To Send
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ACE_OUT1 equ 00000100b ; Output Line 1
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ACE_OUT2 equ 00001000b ; Output Line 2
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ACE_LOOP equ 00010000b ; Loopback
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ACE_LSR equ 5 ;Line Status
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ACE_DR equ 00000001b ; Data Ready
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ACE_OR equ 00000010b ; Overrun Error
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ACE_PE equ 00000100b ; Parity Error
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ACE_FE equ 00001000b ; Framing Error
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ACE_BI equ 00010000b ; Break Interrupt
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ACE_THRE equ 00100000b ; Transmitter Holding Register Empty
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ACE_TSRE equ 01000000b ; Transmitter Shift Register Empty
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ACE_MSR equ 6 ;Modem Status
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ACE_DCTS equ 00000001b ; Delta Clear to Send
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ACE_DDSR equ 00000010b ; Delta Data Set Ready
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ACE_TERI equ 00000100b ; Trailing Edge Ring Indicator
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ACE_DRLSD equ 00001000b ; Delta Receive Line Signal Detect
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ACE_CTS equ 00010000b ; Clear To Send
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ACE_DSR equ 00100000b ; Data Set ready
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ACE_RI equ 01000000b ; Ring Indicator
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ACE_RLSD equ 10000000b ; Receive Line Signal Detect
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ACE_DLL equ 0 ;LSB Baud Rate Divisor
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ACE_DLM equ 1 ;MSB Baud Rate Divisor
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