262 lines
5.9 KiB
C
262 lines
5.9 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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ncr53C94.h
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Abstract:
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The module defines the structures, defines and functions for the NCR 53C94
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host bus adapter chip.
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Author:
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Jeff Havens (jhavens) 28-Feb-1991
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Revision History:
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R.D. Lanser (DEC) 05-Oct-1991
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Copied SCSI_REGISTER structure from d3scsidd.c and added check for
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DECSTATION. Changed the UCHAR's in the read/write register structures
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with SCSI_REGISTER, and added the dot Byte member reference to
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SCSI_WRITE and SCSI_READ macros.
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--*/
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#ifndef _NCR53C94_
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#define _NCR53C94_
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//
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// Define SCSI Protocol Chip register format.
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//
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#if defined(DECSTATION)
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typedef struct _SCSI_REGISTER {
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UCHAR Byte;
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UCHAR Fill[3];
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} SCSI_REGISTER, *PSCSI_REGISTER;
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#else
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#define SCSI_REGISTER UCHAR
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#endif // DECSTATION
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//
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// SCSI Protocol Chip Definitions.
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//
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// Define SCSI Protocol Chip Read registers structure.
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//
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typedef struct _SCSI_READ_REGISTERS {
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SCSI_REGISTER TransferCountLow;
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SCSI_REGISTER TransferCountHigh;
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SCSI_REGISTER Fifo;
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SCSI_REGISTER Command;
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SCSI_REGISTER ScsiStatus;
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SCSI_REGISTER ScsiInterrupt;
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SCSI_REGISTER SequenceStep;
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SCSI_REGISTER FifoFlags;
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SCSI_REGISTER Configuration1;
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SCSI_REGISTER Reserved1;
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SCSI_REGISTER Reserved2;
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SCSI_REGISTER Configuration2;
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SCSI_REGISTER Configuration3;
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SCSI_REGISTER Reserved;
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SCSI_REGISTER TransferCountPage;
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SCSI_REGISTER FifoBottem;
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} SCSI_READ_REGISTERS, *PSCSI_READ_REGISTERS;
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//
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// Define SCSI Protocol Chip Write registers structure.
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//
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typedef struct _SCSI_WRITE_REGISTERS {
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SCSI_REGISTER TransferCountLow;
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SCSI_REGISTER TransferCountHigh;
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SCSI_REGISTER Fifo;
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SCSI_REGISTER Command;
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SCSI_REGISTER DestinationId;
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SCSI_REGISTER SelectTimeOut;
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SCSI_REGISTER SynchronousPeriod;
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SCSI_REGISTER SynchronousOffset;
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SCSI_REGISTER Configuration1;
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SCSI_REGISTER ClockConversionFactor;
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SCSI_REGISTER TestMode;
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SCSI_REGISTER Configuration2;
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SCSI_REGISTER Configuration3;
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SCSI_REGISTER Reserved;
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SCSI_REGISTER TransferCountPage;
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SCSI_REGISTER FifoBottem;
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} SCSI_WRITE_REGISTERS, *PSCSI_WRITE_REGISTERS;
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typedef union _SCSI_REGISTERS {
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SCSI_READ_REGISTERS ReadRegisters;
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SCSI_WRITE_REGISTERS WriteRegisters;
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} SCSI_REGISTERS, *PSCSI_REGISTERS;
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//
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// Define SCSI Command Codes.
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//
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#define NO_OPERATION_DMA 0x80
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#define FLUSH_FIFO 0x1
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#define RESET_SCSI_CHIP 0x2
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#define RESET_SCSI_BUS 0x3
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#define TRANSFER_INFORMATION 0x10
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#define TRANSFER_INFORMATION_DMA 0x90
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#define COMMAND_COMPLETE 0x11
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#define MESSAGE_ACCEPTED 0x12
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#define TRANSFER_PAD 0x18
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#define SET_ATTENTION 0x1a
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#define RESET_ATTENTION 0x1b
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#define RESELECT 0x40
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#define SELECT_WITHOUT_ATTENTION 0x41
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#define SELECT_WITH_ATTENTION 0x42
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#define SELECT_WITH_ATTENTION_STOP 0x43
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#define ENABLE_SELECTION_RESELECTION 0x44
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#define DISABLE_SELECTION_RESELECTION 0x45
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#define SELECT_WITH_ATTENTION3 0x46
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//
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// Define SCSI Status Register structure.
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//
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typedef struct _SCSI_STATUS {
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UCHAR Phase : 3;
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UCHAR ValidGroup : 1;
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UCHAR TerminalCount : 1;
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UCHAR ParityError : 1;
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UCHAR GrossError : 1;
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UCHAR Interrupt : 1;
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} SCSI_STATUS, *PSCSI_STATUS;
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//
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// Define SCSI Phase Codes.
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//
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#define DATA_OUT 0x0
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#define DATA_IN 0x1
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#define COMMAND_OUT 0x2
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#define STATUS_IN 0x3
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#define MESSAGE_OUT 0x6
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#define MESSAGE_IN 0x7
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//
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// Define SCSI Interrupt Register structure.
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//
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typedef struct _SCSI_INTERRUPT {
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UCHAR Selected : 1;
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UCHAR SelectedWithAttention : 1;
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UCHAR Reselected : 1;
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UCHAR FunctionComplete : 1;
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UCHAR BusService : 1;
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UCHAR Disconnect : 1;
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UCHAR IllegalCommand : 1;
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UCHAR ScsiReset : 1;
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} SCSI_INTERRUPT, *PSCSI_INTERRUPT;
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//
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// Define SCSI Sequence Step Register structure.
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//
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typedef struct _SCSI_SEQUENCE_STEP {
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UCHAR Step : 3;
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UCHAR MaximumOffset : 1;
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UCHAR Reserved : 4;
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} SCSI_SEQUENCE_STEP, *PSCSI_SEQUENCE_STEP;
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//
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// Define SCSI Fifo Flags Register structure.
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//
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typedef struct _SCSI_FIFO_FLAGS {
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UCHAR ByteCount : 5;
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UCHAR FifoStep : 3;
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} SCSI_FIFO_FLAGS, *PSCSI_FIFO_FLAGS;
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//
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// Define SCSI Configuration 1 Register structure.
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//
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typedef struct _SCSI_CONFIGURATION1 {
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UCHAR HostBusId : 3;
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UCHAR ChipTestEnable : 1;
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UCHAR ParityEnable : 1;
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UCHAR ParityTestMode : 1;
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UCHAR ResetInterruptDisable : 1;
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UCHAR SlowCableMode : 1;
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} SCSI_CONFIGURATION1, *PSCSI_CONFIGURATION1;
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//
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// Define SCSI Configuration 2 Register structure.
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//
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typedef struct _SCSI_CONFIGURATION2 {
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UCHAR DmaParityEnable : 1;
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UCHAR RegisterParityEnable : 1;
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UCHAR TargetBadParityAbort : 1;
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UCHAR Scsi2 : 1;
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UCHAR HighImpedance : 1;
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UCHAR EnableByteControl : 1;
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UCHAR EnablePhaseLatch : 1;
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UCHAR ReserveFifoByte : 1;
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} SCSI_CONFIGURATION2, *PSCSI_CONFIGURATION2;
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//
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// Define SCSI Configuration 3 Register structure.
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//
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typedef struct _SCSI_CONFIGURATION3 {
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UCHAR Threshold8 : 1;
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UCHAR AlternateDmaMode : 1;
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UCHAR SaveResidualByte : 1;
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UCHAR FastClock : 1;
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UCHAR FastScsi : 1;
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UCHAR EnableCdb10 : 1;
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UCHAR EnableQueue : 1;
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UCHAR CheckIdMessage : 1;
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} SCSI_CONFIGURATION3, *PSCSI_CONFIGURATION3;
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//
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// Define Emulex FAS 218 unique part Id code.
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//
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typedef struct _NCR_PART_CODE {
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UCHAR RevisionLevel : 3;
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UCHAR ChipFamily : 5;
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}NCR_PART_CODE, *PNCR_PART_CODE;
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#define EMULEX_FAS_216 2
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//
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// SCSI Protocol Chip Control read and write macros.
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//
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#if defined(DECSTATION)
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#define SCSI_READ(ChipAddr, Register) \
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(READ_REGISTER_UCHAR (&((ChipAddr)->ReadRegisters.Register.Byte)))
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#define SCSI_WRITE(ChipAddr, Register, Value) \
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WRITE_REGISTER_UCHAR(&((ChipAddr)->WriteRegisters.Register.Byte), (Value))
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#else
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#define SCSI_READ(ChipAddr, Register) \
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(READ_REGISTER_UCHAR (&((ChipAddr)->ReadRegisters.Register)))
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#define SCSI_WRITE(ChipAddr, Register, Value) \
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WRITE_REGISTER_UCHAR(&((ChipAddr)->WriteRegisters.Register), (Value))
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#endif
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#endif
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