610 lines
17 KiB
C
610 lines
17 KiB
C
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/*++
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Copyright (c) 1996-1998 Microsoft Corporation
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Module Name:
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simulate.c
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Abstract:
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This module contains the code that drives the intel instruction
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execution process.
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Author:
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Dave Hastings (daveh) creation-date 09-Jul-1994
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Revision History:
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--*/
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#include <nt.h>
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#include <ntrtl.h>
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#include <nturtl.h>
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#include <windows.h>
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#define _WX86CPUAPI_
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#include "wx86nt.h"
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#include "wx86.h"
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#include "wx86cpu.h"
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#include "cpuassrt.h"
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#include "threadst.h"
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#include "instr.h"
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#include "config.h"
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#include "entrypt.h"
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#include "compilep.h"
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#include "compiler.h"
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#include "instr.h"
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#include "frag.h"
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#include "cpumain.h"
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#include "mrsw.h"
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#include "cpunotif.h"
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#include "tc.h"
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#include "atomic.h"
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ASSERTNAME;
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//
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// Private definition of what a WX86_CPUHINT really contains.
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// The CPUHINT allows the CPU to bypass an expensive NativeAddressFromEip()
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// call to map the Intel EIP value into a RISC address. Most calls to
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// CpuSimulate() are from RISC-to-x86 callbacks, and they have two DWORDS
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// which the CPU uses to cache the NativeAddressFromEip() results.
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//
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// Timestamp -- value of TranslationCacheTimestamp when the CPUHINT was
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// filled in. This is used to determine if the Translation Cache
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// has been flushed. If so, the EntryPoint pointer is now
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// invalid.
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// EntryPoint -- pointer to the ENTRYPOINT describing the Intel Address
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// corresponding to this callback.
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//
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//
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typedef struct _CpuHint {
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DWORD Timestamp;
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PENTRYPOINT EntryPoint;
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} CPUHINT, *PCPUHINT;
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//
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// These values are modified by the wx86e debugger extension whenever it
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// writes into this process's address space. It is used whenever Int3
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// instructions are added or removed from Intel code. The CPU examines
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// these variables whenever CPUNOTIFY_DBGFLUSHTC is set.
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//
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ULONG DbgDirtyMemoryAddr = 0xffffffff;
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ULONG DbgDirtyMemoryLength;
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#ifdef PROFILE
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//
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// Wrap our assembly entrypoint so we can see it in the cap output
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//
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VOID
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_ProfStartTranslatedCode(
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PTHREADSTATE ThreadState,
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PVOID NativeCode
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)
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{
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StartTranslatedCode(ThreadState, NativeCode);
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}
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#endif
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VOID
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MsCpuSimulate(
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PWX86_CPUHINT Wx86CpuHint
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)
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/*++
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Routine Description:
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This is the cpu internal routine that causes intel instructions
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to be executed. Execution continues until something interesting
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happens (such as BOP Unsimulate)
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Arguments:
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None.
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Return Value:
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None.
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--*/
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{
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PVOID NativeCode;
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DWORD CpuNotify;
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DWORD OldCompilerFlags = CompilerFlags;
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DECLARE_CPU;
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CPUASSERT(sizeof(CPUHINT) == sizeof(WX86_CPUHINT));
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//
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// Check CpuNotify to see if the Translation Cache needs flushing.
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//
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CpuNotify = cpu->CpuNotify;
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cpu->CpuNotify &= ~(ULONG)CPUNOTIFY_DBGFLUSHTC;
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if (cpu->flag_tf) {
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CpuNotify |= CPUNOTIFY_MODECHANGE;
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CompilerFlags = COMPFL_SLOW;
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}
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if (CpuNotify & (CPUNOTIFY_DBGFLUSHTC|CPUNOTIFY_MODECHANGE)) {
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if (CpuNotify & CPUNOTIFY_MODECHANGE) {
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//
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// On a fast/slow compiler mode change, flush the whole cache
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//
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DbgDirtyMemoryAddr = 0;
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DbgDirtyMemoryLength = 0xffffffff;
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}
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//
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// The debugger has modified memory - flush the Translation Cache
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//
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CpuFlushInstructionCache((PVOID)DbgDirtyMemoryAddr,
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DbgDirtyMemoryLength);
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DbgDirtyMemoryAddr = 0xffffffff;
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DbgDirtyMemoryLength = 0;
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}
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//
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// Flag ourseleves as having the TC lock.
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//
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CPUASSERTMSG(cpu->fTCUnlocked != FALSE,
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"CPU has been reentered with the TC already locked.\n");
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cpu->fTCUnlocked = FALSE;
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//
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// The caller has already pushed a return address on the stack.
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// (Probably to a BOP FE). Get the callstack in sync.
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//
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PUSH_CALLSTACK(*(DWORD *)cpu->Esp.i4, 0)
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if (Wx86CpuHint) {
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PCPUHINT CpuHint = (PCPUHINT)Wx86CpuHint;
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PVOID Eip = (PVOID)cpu->eipReg.i4;
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//
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// CpuNotify isn't set, and a hint is present...try to use it.
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//
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MrswReaderEnter(&MrswTC);
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if (CpuHint->Timestamp != TranslationCacheTimestamp ||
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CpuHint->EntryPoint->intelStart != Eip) {
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//
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// The hint is present, but invalid. Get the new address and
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// update the hint
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//
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MrswReaderExit(&MrswTC);
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#if 0
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LOGPRINT((DEBUGLOG, "CPU: CpuHint was invalid: got (%X,%X) expected (%X,%X)\r\n",
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CpuHint->Timestamp, ((CpuHint->Timestamp)?CpuHint->EntryPoint->intelStart:0),
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TranslationCacheTimestamp, Eip));
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#endif
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CpuHint->EntryPoint = NativeAddressFromEip(Eip, FALSE);
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CpuHint->Timestamp = TranslationCacheTimestamp;
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}
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NativeCode = CpuHint->EntryPoint->nativeStart;
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} else {
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//
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// Find the address of the Native code to execute, and lock the
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// Translation cache
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//
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NativeCode = NativeAddressFromEip((PVOID)cpu->eipReg.i4, FALSE)->nativeStart;
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}
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while (TRUE) {
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if (cpu->CSTimestamp != TranslationCacheTimestamp) {
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//
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// The timestamp associated with the callstack is different
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// than the timestamp for the Translation Cache. Therefore,
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// the TC has been flushed. We must flush the callstack, too.
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//
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FlushCallstack(cpu);
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}
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//
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// Go execute the code
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//
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#ifdef PROFILE
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_ProfStartTranslatedCode(cpu, NativeCode);
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#else
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StartTranslatedCode(cpu, NativeCode);
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#endif
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CompilerFlags = OldCompilerFlags;
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//
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// Release the translation cache
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//
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MrswReaderExit(&MrswTC);
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//
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// if TF flag is set, then switch the compiler to SLOW_MODE
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// and set the CPUNOTIFY_TRACEFLAG to generate an x86 single-step
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// exception.
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//
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cpu->CpuNotify |= cpu->flag_tf;
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//
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// Check and see if anything needs to be done
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//
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if (cpu->CpuNotify) {
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//
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// Atomically get CpuNotify and clear the appropriate bits
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//
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CpuNotify = cpu->CpuNotify;
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cpu->CpuNotify &= (CPUNOTIFY_TRACEADDR|CPUNOTIFY_SLOWMODE|CPUNOTIFY_TRACEFLAG);
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//
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// Indicate we have left the Translation Cache
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//
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cpu->fTCUnlocked = TRUE;
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if (CpuNotify & CPUNOTIFY_UNSIMULATE) {
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break;
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}
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if (CpuNotify & CPUNOTIFY_EXITTC) {
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// There is no work to do - The Translation Cache is going
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// away, so all active reader threads needed to leave the
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// cache ASAP and block inside NativeAddressFromEip() until
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// the cache flush has completed.
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}
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if (CpuNotify & CPUNOTIFY_SUSPEND) {
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//
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// Another thread wants to suspend us. Notify that
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// thread that we're in a consistent state, then wait
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// until we are resumed.
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//
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CpupSuspendCurrentThread();
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}
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if (CpuNotify & CPUNOTIFY_SLOWMODE) {
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// log the instruction address for debugging purposes
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cpu->eipLog[cpu->eipLogIndex++] = cpu->eipReg.i4;
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cpu->eipLogIndex %= EIPLOGSIZE;
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}
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if (CpuNotify & CPUNOTIFY_INTX) {
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BYTE intnum;
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//
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// Get the interrupt number from the code stream, and
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// advance Eip to the start of the next instruction.
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//
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intnum = *(PBYTE)cpu->eipReg.i4;
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cpu->eipReg.i4 += 1;
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if (intnum == 0xcc) {
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intnum = 3;
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} else {
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cpu->eipReg.i4 += 1;
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}
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CpupDoInterrupt(intnum);
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//
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// Flush the entire translation cache since we don't know what memory
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// areas the debugger has changed. We do this by simulating
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// a compiler mode change.
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//
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CpuNotify |= CPUNOTIFY_MODECHANGE;
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} else if (CpuNotify & (CPUNOTIFY_TRACEADDR|CPUNOTIFY_TRACEFLAG)) {
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if ((CpuNotify & CPUNOTIFY_TRACEADDR) &&
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((DWORD)(ULONGLONG)cpu->TraceAddress == cpu->eipReg.i4)
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) {
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cpu->TraceAddress = NULL;
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cpu->CpuNotify &= ~(ULONG)CPUNOTIFY_TRACEADDR;
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Wx86RaiseStatus(WX86CPU_SINGLE_STEP);
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}
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if (CpuNotify & CPUNOTIFY_TRACEFLAG) {
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cpu->flag_tf = 0;
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cpu->CpuNotify &= ~(ULONG)CPUNOTIFY_TRACEFLAG;
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Wx86RaiseStatus(WX86CPU_SINGLE_STEP);
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}
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//
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// Flush the entire translation cache since we don't know what memory
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// areas the debugger has changed. We do this by simulating
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// a compiler mode change.
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//
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CpuNotify |= CPUNOTIFY_MODECHANGE;
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}
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if (CpuNotify & (CPUNOTIFY_DBGFLUSHTC|CPUNOTIFY_MODECHANGE)) {
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if (CpuNotify & CPUNOTIFY_MODECHANGE) {
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//
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// On a fast/slow compiler mode change, flush whole cache
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//
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DbgDirtyMemoryAddr = 0;
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DbgDirtyMemoryLength = 0xffffffff;
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}
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//
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// The debugger has modified memory - flush the Translation
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// Cache
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//
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CpuFlushInstructionCache((PVOID)DbgDirtyMemoryAddr,
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DbgDirtyMemoryLength);
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DbgDirtyMemoryAddr = 0xffffffff;
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DbgDirtyMemoryLength = 0;
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}
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//
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// Indicate we are re-entering the Translation Cache
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//
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cpu->fTCUnlocked = FALSE;
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}
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if (cpu->flag_tf) {
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OldCompilerFlags = CompilerFlags;
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CompilerFlags = COMPFL_SLOW;
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if (!(CpuNotify & CPUNOTIFY_MODECHANGE)) {
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CpuFlushInstructionCache(NULL, 0xffffffff);
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}
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}
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//
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// Find the address of the Native code to execute, and lock the
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// Translation cache
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//
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NativeCode = NativeAddressFromEip((PVOID)cpu->eipReg.i4, FALSE)->nativeStart;
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}
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}
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PENTRYPOINT
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NativeAddressFromEip(
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PVOID Eip,
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BOOL LockTCForWrite
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)
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/*++
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Routine Description:
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This routine finds (or creates) the native code for the specified Intel
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code.
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NOTE: This function can only be called when the Translation Cache is
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not locked (either read or write) by the current thread.
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Arguments:
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Eip -- Supplies the address of the Intel code
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LockTCForWrite -- TRUE if caller wants TC locked for WRITE, FALSE if the
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call wants it locked for READ.
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Return Value:
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Entrypoint whose nativeStart Address corresponds to the Intel Address
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passed in.
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--*/
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{
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PENTRYPOINT Entrypoint;
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typedef VOID (*pfnMrswCall)(PMRSWOBJECT);
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pfnMrswCall MrswCall;
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DWORD OldEntrypointTimestamp;
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//
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// Assume we are going to call MrswReaderExit(&MrswEP) at the end
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// of this function.
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//
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|
||
|
|
MrswCall = MrswReaderExit;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Lock the Entrypoint for reading
|
||
|
|
//
|
||
|
|
MrswReaderEnter(&MrswEP);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Find the location of the Risc code corresponding to the
|
||
|
|
// Intel EIP register
|
||
|
|
//
|
||
|
|
Entrypoint = EPFromIntelAddr(Eip);
|
||
|
|
|
||
|
|
|
||
|
|
//
|
||
|
|
// If there is no entrypoint, compile up the code
|
||
|
|
//
|
||
|
|
if (Entrypoint == NULL || Entrypoint->intelStart != Eip) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// Unlock the Entrypoint read
|
||
|
|
//
|
||
|
|
OldEntrypointTimestamp = EntrypointTimestamp;
|
||
|
|
MrswReaderExit(&MrswEP);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Lock the Entrypoint for write, and change the function to be
|
||
|
|
// called at the end of the function to be MrswWriterExit(&MrswEP)
|
||
|
|
//
|
||
|
|
MrswWriterEnter(&MrswEP);
|
||
|
|
MrswCall = MrswWriterExit;
|
||
|
|
|
||
|
|
//
|
||
|
|
// See if another thread compiled the Entrypoint while we were
|
||
|
|
// switching from read mode to write mode
|
||
|
|
//
|
||
|
|
if (OldEntrypointTimestamp != EntrypointTimestamp) {
|
||
|
|
//
|
||
|
|
// Timestamp has changed. There is a possibility that another
|
||
|
|
// thread has compiled code at Eip for us, so retry the search.
|
||
|
|
//
|
||
|
|
Entrypoint = EPFromIntelAddr(Eip);
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Call the compiler. It will do one of the following things:
|
||
|
|
// 1. if Entrypoint==NULL, it will compile new code
|
||
|
|
// 2. if Entrypoint!=NULL and Entrypoint->Eip == Eip, it will
|
||
|
|
// return Entrypoint unchanged
|
||
|
|
// 3. otherwise, the Entrypoint needs splitting. It will do so,
|
||
|
|
// and compile a subset of the code described by Entrypoint and
|
||
|
|
// then return a new Entrypoint
|
||
|
|
//
|
||
|
|
Entrypoint = Compile(Entrypoint, Eip);
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Instruction was found - grab the translation cache for either
|
||
|
|
// read or write, then free the entrypoint write lock. The
|
||
|
|
// order is important as it prevents the TC from being flushed
|
||
|
|
// between the two Mrsw calls.
|
||
|
|
//
|
||
|
|
if (LockTCForWrite) {
|
||
|
|
InterlockedIncrement(&ProcessCpuNotify);
|
||
|
|
MrswWriterEnter(&MrswTC);
|
||
|
|
InterlockedDecrement(&ProcessCpuNotify);
|
||
|
|
} else {
|
||
|
|
MrswReaderEnter(&MrswTC);
|
||
|
|
}
|
||
|
|
(*MrswCall)(&MrswEP); // Either MrswReaderExit() or MrswWriterExit()
|
||
|
|
|
||
|
|
return Entrypoint;
|
||
|
|
}
|
||
|
|
|
||
|
|
PVOID
|
||
|
|
NativeAddressFromEipNoCompile(
|
||
|
|
PVOID Eip
|
||
|
|
)
|
||
|
|
/*++
|
||
|
|
|
||
|
|
Routine Description:
|
||
|
|
|
||
|
|
This routine finds the native code for the specified Intel code, if it
|
||
|
|
exists. No new code is compiled.
|
||
|
|
|
||
|
|
NOTE: This function can only be called when the Translation Cache is
|
||
|
|
not locked (either read or write) by the current thread.
|
||
|
|
|
||
|
|
Arguments:
|
||
|
|
|
||
|
|
Eip -- Supplies the address of the Intel code
|
||
|
|
|
||
|
|
Return Value:
|
||
|
|
|
||
|
|
Address of corresponding native code, or NULL if none exists. Translation
|
||
|
|
cache locked for WRITE if native code exists for Eip. TC is locked for
|
||
|
|
READ if no code exitss.
|
||
|
|
|
||
|
|
--*/
|
||
|
|
{
|
||
|
|
PENTRYPOINT Entrypoint;
|
||
|
|
DWORD OldEntrypointTimestamp;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Lock the Entrypoint for reading
|
||
|
|
//
|
||
|
|
MrswReaderEnter(&MrswEP);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Find the location of the Risc code corresponding to the
|
||
|
|
// Intel EIP register
|
||
|
|
//
|
||
|
|
Entrypoint = EPFromIntelAddr(Eip);
|
||
|
|
|
||
|
|
if (Entrypoint == NULL) {
|
||
|
|
//
|
||
|
|
// Entrypoint not found - no native code exists for this Intel address
|
||
|
|
//
|
||
|
|
MrswReaderEnter(&MrswTC);
|
||
|
|
MrswReaderExit(&MrswEP);
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
} else if (Entrypoint->intelStart == Eip) {
|
||
|
|
//
|
||
|
|
// Exact instruction found - return the NATIVE address
|
||
|
|
//
|
||
|
|
InterlockedIncrement(&ProcessCpuNotify);
|
||
|
|
MrswWriterEnter(&MrswTC);
|
||
|
|
InterlockedDecrement(&ProcessCpuNotify);
|
||
|
|
MrswReaderExit(&MrswEP);
|
||
|
|
return Entrypoint->nativeStart;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Else the entrypoint contains the Intel address. Nothing can
|
||
|
|
// be done. Release EP write and get TC read.
|
||
|
|
//
|
||
|
|
MrswReaderExit(&MrswEP);
|
||
|
|
MrswReaderEnter(&MrswTC);
|
||
|
|
return NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
PENTRYPOINT
|
||
|
|
NativeAddressFromEipNoCompileEPWrite(
|
||
|
|
PVOID Eip
|
||
|
|
)
|
||
|
|
/*++
|
||
|
|
|
||
|
|
Routine Description:
|
||
|
|
|
||
|
|
This routine finds the native code for the specified Intel code, if it
|
||
|
|
exists. No new code is compiled. This function is called by functions
|
||
|
|
in patchfn.c during compile time when they need to decide whether to
|
||
|
|
directly place the patched version in the Translation Cache or not.
|
||
|
|
|
||
|
|
NOTE: This function can only be called when the Translation Cache is
|
||
|
|
not locked (either read or write) by the current thread.
|
||
|
|
|
||
|
|
NOTE: The difference between this function and NativeAddressFromEipNoCompile
|
||
|
|
is that here we assume that we have the Entry Point write lock upon
|
||
|
|
entry to the function. This function makes no calls to MRSW functions
|
||
|
|
for any locks.
|
||
|
|
|
||
|
|
Arguments:
|
||
|
|
|
||
|
|
Eip -- Supplies the address of the Intel code
|
||
|
|
|
||
|
|
Return Value:
|
||
|
|
|
||
|
|
Address of corresponding native code, or NULL if none exists. All MRSW objects
|
||
|
|
are in exactly the same state they were when we entered this function.
|
||
|
|
|
||
|
|
--*/
|
||
|
|
{
|
||
|
|
PENTRYPOINT Entrypoint;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Find the location of the Risc code corresponding to the
|
||
|
|
// Intel EIP register
|
||
|
|
//
|
||
|
|
Entrypoint = EPFromIntelAddr(Eip);
|
||
|
|
|
||
|
|
if (Entrypoint == NULL) {
|
||
|
|
//
|
||
|
|
// Entrypoint not found - no native code exists for this Intel address
|
||
|
|
//
|
||
|
|
return NULL;
|
||
|
|
|
||
|
|
} else if (Entrypoint->intelStart == Eip) {
|
||
|
|
//
|
||
|
|
// Exact instruction found - return the NATIVE address
|
||
|
|
//
|
||
|
|
return Entrypoint;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Entrypoint needs to be split. Can't do that without compiling.
|
||
|
|
//
|
||
|
|
return NULL;
|
||
|
|
}
|