564 lines
14 KiB
C
564 lines
14 KiB
C
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/*++
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Copyright (c) 1995 Microsoft Corporation
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Module Name:
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fpuload.c
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Abstract:
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Floating point load functions
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Author:
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04-Oct-1995 BarryBo
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Revision History:
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--*/
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#include <nt.h>
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#include <ntrtl.h>
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#include <nturtl.h>
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#include <windows.h>
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#include <float.h>
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#include <math.h>
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#include <stdio.h>
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#include "wx86.h"
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#include "cpuassrt.h"
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#include "fragp.h"
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#include "fpufragp.h"
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#include "fpuarith.h"
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ASSERTNAME;
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VOID GetIntelR4(
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PFPREG Fp,
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FLOAT *pIntelReal
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)
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/*++
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Routine Description:
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Load an Intel R4 and convert it to a native R4, accounting for
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the difference in how MIPS represents QNAN/SNAN.
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NOTE: This is not in fpufrag.c due to a code-generator bug on PPC -
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irbexpr.c:932 asserts trying to inline this function. Moving it
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to a different file defeats the inliner.
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Arguments:
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Fp - floating-point register to load the R4 into
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pIntelReal - R4 value to load (in Intel format)
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Return Value:
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None.
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--*/
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{
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DWORD d = GET_LONG(pIntelReal);
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if ((d & 0x7f800000) == 0x7f800000) {
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Fp->Tag = TAG_SPECIAL;
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// Found some sort of NAN
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if (d == 0xffc00000) { // Indefinite
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// Create the native indefinite form
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#if NATIVE_NAN_IS_INTEL_FORMAT
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Fp->rdw[0] = 0;
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Fp->rdw[1] = 0xfff80000;
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#else
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Fp->rdw[0] = 0xffffffff;
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Fp->rdw[1] = 0x7ff7ffff;
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#endif
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Fp->TagSpecial = TAG_SPECIAL_INDEF;
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} else if (d == 0x7f800000) { // +infinity
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Fp->r64 = R8PositiveInfinity;
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Fp->TagSpecial = TAG_SPECIAL_INFINITY;
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} else if (d == 0xff800000) { // -infinity
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Fp->r64 = R8NegativeInfinity;
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Fp->TagSpecial = TAG_SPECIAL_INFINITY;
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} else { // SNAN/QNAN
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DWORD Sign;
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if (d & 0x00400000) {
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//
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// Intel QNAN
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//
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Fp->TagSpecial = TAG_SPECIAL_QNAN;
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} else {
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//
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// Intel SNAN
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//
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Fp->TagSpecial = TAG_SPECIAL_SNAN;
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}
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#if !NATIVE_NAN_IS_INTEL_FORMAT
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//
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// Toggle the NAN to native format
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//
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d ^= 0x00400000;
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#endif
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//
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// Cast the r4 RISC QNAN to double. Don't trust the CRT to
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// do the right thing - MIPS converts them both to INDEFINITE.
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//
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Sign = d & 0x80000000;
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d &= 0x007fffff; // grab the mantissa from the r4 (23 bits)
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Fp->rdw[1] = Sign | 0x7ff00000 | (d >> 3); // store 20 bits of mantissa, plus sign
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Fp->rdw[0] = d << 25; // store 3 bits of mantissa
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}
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} else { // denormal, zero, or number
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// Coerce it to an R8
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Fp->r64 = (DOUBLE)*(FLOAT *)&d;
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// Compute its tag by looking at the value *after* the conversion,
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// as the native FPU may have normalized the value
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if (Fp->r64 == 0.0) {
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Fp->Tag = TAG_ZERO;
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} else if ((Fp->rdw[1] & 0x7ff00000) == 0) {
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// Exponent is 0 - R8 denormal
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Fp->Tag = TAG_SPECIAL;
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Fp->TagSpecial = TAG_SPECIAL_DENORM;
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} else {
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Fp->Tag = TAG_VALID;
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#if DBG
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SetTag(Fp);
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CPUASSERT(Fp->Tag == TAG_VALID);
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#endif
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}
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}
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}
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#if !NATIVE_NAN_IS_INTEL_FORMAT
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VOID GetIntelR8(
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PFPREG Fp,
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DOUBLE *pIntelReal
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)
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/*++
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Routine Description:
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Load an Intel R8 and convert it to a native R8, accounting for
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the difference in how MIPS represents QNAN/SNAN.
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Arguments:
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Fp - floating-point register to load the R8 into
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pIntelReal - R8 value to load (in Intel format)
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Return Value:
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None.
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--*/
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{
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//
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// Copy the R8 into the FP register
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//
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Fp->r64 = *(UNALIGNED DOUBLE *)pIntelReal;
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//
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// Compute its tag
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//
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SetTag(Fp);
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//
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// If the value is QNAN/SNAN/INDEF, convert it to native format
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//
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if (IS_TAG_NAN(Fp)) {
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if (Fp->rdw[0] == 0 && Fp->rdw[1] == 0xfff80000) {
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// indefinite - make the R8 into a native indefinite
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Fp->TagSpecial = TAG_SPECIAL_INDEF;
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Fp->rdw[0] = 0xffffffff;
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Fp->rdw[1] = 0x7ff7ffff;
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} else {
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if (Fp->rdw[1] & 0x00080000) {
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// top bit of mantissa is set - QNAN
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Fp->TagSpecial = TAG_SPECIAL_QNAN;
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} else {
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// top bit of mantissa clear - SNAN
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Fp->TagSpecial = TAG_SPECIAL_SNAN;
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}
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Fp->rdw[1] ^= 0x00080000; // invert the top bit of the mantissa
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}
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}
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}
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#endif //!NATIVE_NAN_IS_INTEL_FORMAT
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VOID
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SetTag(
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PFPREG FpReg
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)
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/*++
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Routine Description:
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Sets the Tag value corresponding to a r64 value in an FP register.
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Assumes the R8 value is in native format (ie. Intel NANs are already
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converted to native NANs).
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Arguments:
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FpReg - register to set Tag field in.
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Return Value:
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None
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--*/
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{
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DWORD Exponent;
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/* On average, the value will be zero or a valid real, so those cases
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* have the fastest code paths. NANs tend to be less frequent and are
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* slower to calculate.
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*/
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Exponent = FpReg->rdw[1] & 0x7ff00000;
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if (Exponent == 0x7ff00000) {
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// exponent is all 1's - NAN of some sort
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FpReg->Tag = TAG_SPECIAL;
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if (FpReg->rdw[0] == 0 && (FpReg->rdw[1] & 0x7fffffff) == 0x7ff00000) {
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// Exponent is all 1s, mantissa is all 0s - Infinity
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FpReg->TagSpecial = TAG_SPECIAL_INFINITY;
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} else {
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#if NATIVE_NAN_IS_INTEL_FORMAT
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if (FpReg->rdw[0] == 0 && FpReg->rdw[1] == 0xfff80000) {
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// indefinite
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FpReg->TagSpecial = TAG_SPECIAL_INDEF;
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} else if (FpReg->rdw[1] & 0x00080000) {
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// top bit of mantissa is set - QNAN
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FpReg->TagSpecial = TAG_SPECIAL_QNAN;
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} else {
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// Top bit of mantissa clear - but some mantissa bit set - QNAN
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FpReg->TagSpecial = TAG_SPECIAL_SNAN;
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}
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#else //!NATIVE_NAN_IS_INTEL_FORMAT
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if (FpReg->rdw[0] == 0xffffffff && FpReg->rdw[1] == 0x7ff7ffff) {
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// indefinite
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FpReg->TagSpecial = TAG_SPECIAL_INDEF;
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} else if (FpReg->rdw[1] & 0x00080000) {
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// top bit of mantissa is set - SNAN
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FpReg->TagSpecial = TAG_SPECIAL_SNAN;
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} else {
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// top bit of mantissa clear - QNAN
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FpReg->TagSpecial = TAG_SPECIAL_QNAN;
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}
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#endif //!NATIVE_NAN_IS_INTEL_FORMAT
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}
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} else if (Exponent == 0) {
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// exponent is 0 - DENORMAL or ZERO
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if ((FpReg->rdw[1] & 0x1ffff) == 0 && FpReg->rdw[0] == 0) {
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// mantissa is all zeroes - ZERO
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FpReg->Tag = TAG_ZERO;
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} else {
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FpReg->Tag = TAG_SPECIAL;
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FpReg->TagSpecial = TAG_SPECIAL_DENORM;
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}
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} else {
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// Exponent is not all 1's and not all 0's - a VALID
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FpReg->Tag = TAG_VALID;
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}
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}
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FRAG1(FILD16, SHORT) // FILD m16int
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{
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PFPREG ST0;
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FpArithDataPreamble(cpu, pop1);
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cpu->FpStatusC1 = 0; // assume no error
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PUSHFLT(ST0);
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if (ST0->Tag != TAG_EMPTY) {
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HandleStackFull(cpu, ST0);
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} else {
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SHORT s;
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s = (SHORT)GET_SHORT(pop1);
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ST0->r64 = (DOUBLE)s;
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if (s) {
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ST0->Tag = TAG_VALID;
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} else {
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ST0->Tag = TAG_ZERO;
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}
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}
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}
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FRAG1(FILD32, LONG) // FILD m32int
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{
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PFPREG ST0;
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FpArithDataPreamble(cpu, pop1);
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cpu->FpStatusC1 = 0; // assume no error
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PUSHFLT(ST0);
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if (ST0->Tag != TAG_EMPTY) {
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HandleStackFull(cpu, ST0);
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} else {
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LONG l;
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l = (LONG)GET_LONG(pop1);
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ST0->r64 = (DOUBLE)l;
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if (l) {
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ST0->Tag = TAG_VALID;
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} else {
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ST0->Tag = TAG_ZERO;
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}
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}
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}
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FRAG1(FILD64, LONGLONG) // FILD m64int
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{
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PFPREG ST0;
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FpArithDataPreamble(cpu, pop1);
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cpu->FpStatusC1 = 0; // assume no error
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PUSHFLT(ST0);
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if (ST0->Tag != TAG_EMPTY) {
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HandleStackFull(cpu, ST0);
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} else {
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LONGLONG ll;
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ll = *(UNALIGNED LONGLONG *)pop1;
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ST0->r64 = (DOUBLE)ll;
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if (ll) {
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ST0->Tag = TAG_VALID;
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} else {
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ST0->Tag = TAG_ZERO;
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}
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}
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}
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FRAG1(FLD32, FLOAT) // FLD m32real
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{
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PFPREG ST0;
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FpArithDataPreamble(cpu, pop1);
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cpu->FpStatusC1 = 0; // assume no error
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PUSHFLT(ST0);
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if (ST0->Tag != TAG_EMPTY) {
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HandleStackFull(cpu, ST0);
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} else {
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GetIntelR4(ST0, pop1);
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if (ST0->Tag == TAG_SPECIAL) {
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if (ST0->TagSpecial == TAG_SPECIAL_DENORM) {
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if (!(cpu->FpControlMask & FPCONTROL_DM)) {
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cpu->FpStatusES = 1; // Unmasked exception
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//
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// Instruction needs to be aborted due to unmasked
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// exception. We've already hosed ST0, so "correct"
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// it by popping the FP stack. Note that
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// the contents of the register have been lost, which
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// is a compatibility break with Intel.
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//
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POPFLT;
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}
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cpu->FpStatusExceptions |= FPCONTROL_DM;
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} else if (ST0->TagSpecial == TAG_SPECIAL_SNAN) {
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if (HandleSnan(cpu, ST0)) {
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//
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// Instruction needs to be aborted due to unmasked
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// exception. We've already hosed ST0, so "correct"
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// it by popping the FP stack. Note that
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// the contents of the register have been lost, which
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// is a compatibility break with Intel.
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//
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POPFLT;
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}
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}
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}
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}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG1(FLD64, DOUBLE) // FLD m64real
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithDataPreamble(cpu, pop1);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
GetIntelR8(ST0, pop1);
|
||
|
|
if (ST0->Tag == TAG_SPECIAL) {
|
||
|
|
if (ST0->TagSpecial == TAG_SPECIAL_DENORM) {
|
||
|
|
if (!(cpu->FpControlMask & FPCONTROL_DM)) {
|
||
|
|
cpu->FpStatusES = 1; // Unmasked exception
|
||
|
|
//
|
||
|
|
// Instruction needs to be aborted due to unmasked
|
||
|
|
// exception. We've already hosed ST0, so "correct"
|
||
|
|
// it by popping the FP stack. Note that
|
||
|
|
// the contents of the register have been lost, which
|
||
|
|
// is a compatibility break with Intel.
|
||
|
|
//
|
||
|
|
POPFLT;
|
||
|
|
}
|
||
|
|
cpu->FpStatusExceptions |= FPCONTROL_DM;
|
||
|
|
} else if (ST0->TagSpecial == TAG_SPECIAL_SNAN) {
|
||
|
|
if (HandleSnan(cpu, ST0)) {
|
||
|
|
//
|
||
|
|
// Instruction needs to be aborted due to unmasked
|
||
|
|
// exception. We've already hosed ST0, so "correct"
|
||
|
|
// it by popping the FP stack. Note that
|
||
|
|
// the contents of the register have been lost, which
|
||
|
|
// is a compatibility break with Intel.
|
||
|
|
//
|
||
|
|
POPFLT;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLD1)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 1.0;
|
||
|
|
ST0->Tag = TAG_VALID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLDL2T)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 2.3025850929940456840E0 / 6.9314718055994530942E-1; //log2(10) = ln10/ln2
|
||
|
|
ST0->Tag = TAG_VALID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLDL2E)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 1.4426950408889634074E0;
|
||
|
|
ST0->Tag = TAG_VALID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLDPI)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 3.14159265358979323846;
|
||
|
|
ST0->Tag = TAG_VALID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLDLG2)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 6.9314718055994530942E-1 / 2.3025850929940456840E0;
|
||
|
|
ST0->Tag = TAG_VALID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLDLN2)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 6.9314718055994530942E-1;
|
||
|
|
ST0->Tag = TAG_VALID;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
FRAG1IMM(FLD_STi, INT)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
PFPREG STi;
|
||
|
|
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
STi = &cpu->FpStack[ST(op1)];
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = STi->r64;
|
||
|
|
ST0->Tag = STi->Tag;
|
||
|
|
ST0->TagSpecial = STi->TagSpecial;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
FRAG0(FLDZ)
|
||
|
|
{
|
||
|
|
PFPREG ST0;
|
||
|
|
FpArithPreamble(cpu);
|
||
|
|
|
||
|
|
cpu->FpStatusC1 = 0; // assume no error
|
||
|
|
PUSHFLT(ST0);
|
||
|
|
if (ST0->Tag != TAG_EMPTY) {
|
||
|
|
HandleStackFull(cpu, ST0);
|
||
|
|
} else {
|
||
|
|
ST0->r64 = 0.0;
|
||
|
|
ST0->Tag = TAG_ZERO;
|
||
|
|
}
|
||
|
|
}
|