107 lines
5.4 KiB
C
107 lines
5.4 KiB
C
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/********************************************************************************
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** Copyright (c) 1998-2000 Microsoft Corporation. All Rights Reserved.
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**
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** Portions Copyright (c) 1998-1999 Intel Corporation
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**
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********************************************************************************/
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#ifndef _ICHREG_H_
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#define _ICHREG_H_
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// We define the offsets like PI_BDBAR as ULONG (instead of UCHAR) for run
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// time efficiency.
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// CoDec AC97 register space offsets
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const ULONG PRIMARY_CODEC = 0x00;
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const ULONG SECONDARY_CODEC = 0x80;
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// Native audio bus master control registers (offsets)
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const ULONG PI_BDBAR = 0x00; // PCM In Buffer Descriptor Base Address Register
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const ULONG PI_CIV = 0x04; // PCM In Current Index Value
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const ULONG PI_LVI = 0x05; // PCM In Last Valid Index
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const ULONG PI_SR = 0x06; // PCM In Status Register
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const ULONG PI_PICB = 0x08; // PCM In Position In Current Buffer
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const ULONG PI_PIV = 0x0A; // PCM In Prefetch Index Value
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const ULONG PI_CR = 0x0B; // PCM In Control Register
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const ULONG PO_BDBAR = 0x10; // PCM Out Buffer Descriptor Base Address Register
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const ULONG PO_CIV = 0x14; // PCM Out Current Index Value
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const ULONG PO_LVI = 0x15; // PCM Out Last Valid Index
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const ULONG PO_SR = 0x16; // PCM Out Status Register
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const ULONG PO_PICB = 0x18; // PCM Out Position In Current Buffer
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const ULONG PO_PIV = 0x1A; // PCM Out Prefetch Index Value
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const ULONG PO_CR = 0x1B; // PCM Out Control Register
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const ULONG MC_BDBAR = 0x20; // Mic In Buffer Descriptor Base Address Register
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const ULONG MC_CIV = 0x24; // Mic In Current Index Value
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const ULONG MC_LVI = 0x25; // Mic In Last Valid Index
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const ULONG MC_SR = 0x26; // Mic In Status Register
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const ULONG MC_PICB = 0x28; // Mic In Position In Current Buffer
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const ULONG MC_PIV = 0x2A; // Mic In Prefetch Index Value
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const ULONG MC_CR = 0x2B; // Mic In Control Register
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const ULONG GLOB_CNT = 0x2C; // Global Control
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const ULONG GLOB_STA = 0x30; // Global Status
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const ULONG CAS = 0x34; // Codec Access Semiphore
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// Defines for relative accesses (offsets)
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const ULONG X_PI_BASE = 0x00; // PCM In Base
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const ULONG X_PO_BASE = 0x10; // PCM Out Base
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const ULONG X_MC_BASE = 0x20; // Mic In Base
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const ULONG X_BDBAR = 0x00; // Buffer Descriptor Base Address Register
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const ULONG X_CIV = 0x04; // Current Index Value
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const ULONG X_LVI = 0x05; // Last Valid Index
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const ULONG X_SR = 0x06; // Status Register
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const ULONG X_PICB = 0x08; // Position In Current Buffer
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const ULONG X_PIV = 0x0A; // Prefetch Index Value
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const ULONG X_CR = 0x0B; // Control Register
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// Bits defined in satatus register (*_SR)
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const USHORT SR_FIFOE = 0x0010; // FIFO error
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const USHORT SR_BCIS = 0x0008; // Buffer Completeion Interrupt Status
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const USHORT SR_LVBCI = 0x0004; // Last Valid Buffer Completion Interrupt
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const USHORT SR_CELV = 0x0002; // Last Valid Buffer Completion Interrupt
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// Global Control bit defines (GLOB_CNT)
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const ULONG GLOB_CNT_PCM6 = 0x00200000; // 6 Channel Mode bit
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const ULONG GLOB_CNT_PCM4 = 0x00100000; // 4 Channel Mode bit
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const ULONG GLOB_CNT_SRIE = 0x00000020; // Secondary Resume Interrupt Enable
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const ULONG GLOB_CNT_PRIE = 0x00000010; // Primary Resume Interrupt Enable
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const ULONG GLOB_CNT_ACLOFF = 0x00000008; // ACLINK Off
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const ULONG GLOB_CNT_WARM = 0x00000004; // AC97 Warm Reset
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const ULONG GLOB_CNT_COLD = 0x00000002; // AC97 Cold Reset
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const ULONG GLOB_CNT_GIE = 0x00000001; // GPI Interrupt Enable
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// Global Status bit defines (GLOB_STA)
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const ULONG GLOB_STA_MC6 = 0x00200000; // Multichannel Capability 6 channel
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const ULONG GLOB_STA_MC4 = 0x00100000; // Multichannel Capability 4 channel
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const ULONG GLOB_STA_MD3 = 0x00020000; // Modem Power Down Semiphore
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const ULONG GLOB_STA_AD3 = 0x00010000; // Audio Power Down Semiphore
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const ULONG GLOB_STA_RCS = 0x00008000; // Read Completion Status
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const ULONG GLOB_STA_B3S12 = 0x00004000; // Bit 3 Slot 12
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const ULONG GLOB_STA_B2S12 = 0x00002000; // Bit 2 Slot 12
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const ULONG GLOB_STA_B1S12 = 0x00001000; // Bit 1 Slot 12
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const ULONG GLOB_STA_SRI = 0x00000800; // Secondary Resume Interrupt
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const ULONG GLOB_STA_PRI = 0x00000400; // Primary Resume Interrupt
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const ULONG GLOB_STA_SCR = 0x00000200; // Secondary Codec Ready
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const ULONG GLOB_STA_PCR = 0x00000100; // Primary Codec Ready
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const ULONG GLOB_STA_MINT = 0x00000080; // Mic In Interrupt
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const ULONG GLOB_STA_POINT = 0x00000040; // PCM Out Interrupt
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const ULONG GLOB_STA_PIINT = 0x00000020; // PCM In Interrupt
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const ULONG GLOB_STA_MOINT = 0x00000004; // Modem Out Interrupt
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// CoDec Access Semiphore bit defines (CAS)
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const UCHAR CAS_CAS = 0x01; // Codec Access Semiphore Bit
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// DMA Engine Control Register (*_CR) bit defines
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const UCHAR CR_IOCE = 0x10; // Interrupt On Completion Enable
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const UCHAR CR_FEIE = 0x08; // FIFO Error Interrupt Enable
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const UCHAR CR_LVBIE = 0x04; // Last Valid Buffer Interrupt Enable
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const UCHAR CR_RPBM = 0x01; // Run/Pause Bus Master
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const UCHAR CR_RR = 0x02; // Reset Registers (RR)
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// BDL policy bits
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const USHORT IOC_ENABLE = 0x8000;
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const USHORT BUP_SET = 0x4000;
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#endif //_ICHREG_H_
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