205 lines
7.8 KiB
C
205 lines
7.8 KiB
C
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/**********************************************************
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* Copyright Cirrus Logic, Inc. 1996. All rights reserved.
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***********************************************************
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*
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* 7555BW.H
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*
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* Contains preprocessor definitions needed for CL-GD7555
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* bandwidth equations.
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*
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***********************************************************
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*
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* WHO WHEN WHAT/WHY/HOW
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* --- ---- ------------
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* RT 11/07/96 Created.
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* TT 02-24-97 Modified from 5446misc.h for 7555.
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*
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***********************************************************/
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//#ifndef _7555BW_H
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//#define _7555BW_H
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//
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//#include <Windows.h>
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//#include <Windowsx.h>
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//
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//#include "VPM_Cir.h"
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//#include "Debug.h"
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//#include "BW.h"
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/* type definitions & structures -------------------------*/
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typedef struct _BWEQ_STATE_INFO
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{
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RECTL rVPort; /* Rect. at video port, if capture enabled */
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RECTL rCrop; /* Rect. after cropping, if capture enabled */
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RECTL rPrescale; /* Rect. after scaling, if capture enabled */
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RECTL rSrc; /* Rect. in memory for display */
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RECTL rDest; /* Rect. on the screen for display */
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DWORD dwSrcDepth; /* Bits per pixel of data, in memory */
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DWORD dwPixelsPerSecond;/* Rate of data into video port, if capture enabled */
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DWORD dwFlags; /* See FLG_ in OVERLAY.H */
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} BWEQ_STATE_INFO, *PBWEQ_STATE_INFO;
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/* preprocessor definitions ------------------------------*/
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#define WIDTH(a) ((a).right - (a).left)
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#define HEIGHT(a) ((a).bottom - (a).top)
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#define REF_XTAL (14318182ul) // Crystal reference frequency (Hz)
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/*
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* VGA MISC Register
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*/
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#define MISC_WRITE 0x03C2 // Miscellaneous Output Register (Write)
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#define MISC_READ 0x03CC // Miscellaneous Output Register (Read)
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#define MISC_VCLK_SELECT 0x0C // Choose one of the four VCLKs
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#define MISC_MEMORY_ACCESS 0x02 // Enable memory access
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/*
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* VGA CRTC Registers
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*/
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#define CR01 0x01 // Horizontal Display End Register
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#define CR01_HORZ_END 0xFF // Horizontal Display End
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#define CR42 0x42 // VW FIFO Threshold and Chroma Key
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// Mode Select Register
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#define CR42_MVWTHRESH 0x0C // VW FIFO Threshold
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#define CR51 0x51 // V-Port Data Format Register
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#define CR51_VPORTMVW_THRESH 0xE0 // V-Port FIFO Threshold in VW
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#define CR5A 0x5A // V-Port Cycle and V-Port FIFO Control
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#define CR5A_VPORTGFX_THRESH 0x07 // V-Port FIFO Threshold in Surrounding
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// graphics
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#define CR5D 0x5D // Number of Memory Cycles per Scanline
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// Override Register
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#define CR5D_MEMCYCLESPERSCAN 0xFF // Number of Memory Cycles per Scanline
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// Override
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#define CR80 0x80 // Power Management Control Register
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#define CR80_LCD_ENABLE 0x01 // Flat Panel Enable
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#define CR83 0x83 // Flat Panel Type Register
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#define CR83_LCD_TYPE 0x70 // Flat Panel Type Select
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/*
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* VGA GRC Registers
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*/
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#define GRC_INDEX 0x03CE // Graphics controller index register
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#define GRC_DATA 0x03CF // Graphics controller data register
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#define GR18 0x18 // EDO RAM Control Register
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#define GR18_LONG_RAS 0x04 // EDO DRAM Long RAS# Cycle Enable
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/*
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* VGA Sequencer Registers
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*/
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#define SR0F 0x0F // Display Memory Control Register
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#define SR0F_DISPLAY_RAS 0x04 // Display Memory RAS# Cycle Select
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#define SR0B 0x0B // VCLK0 Numerator
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#define SR0C 0x0C // VCLK1 Numerator
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#define SR0D 0x0D // VCLK2 Numerator
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#define SR0E 0x0E // VCLK3 Numerator
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#define SR0X_VCLK_NUMERATOR 0x7F // VCLK Numerator
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#define SR1B 0x1B // VCLK0 Denomintor and Post-Scalar
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#define SR1C 0x1C // VCLK1 Denomintor and Post-Scalar
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#define SR1D 0x1D // VCLK2 Denomintor and Post-Scalar
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#define SR1E 0x1E // VCLK3 Denomintor and Post-Scalar
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#define SR1X_VCLK_DENOMINATOR 0x3E // VCLK Denominator
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#define SR1X_VCLK_POST_SCALAR 0x01 // VCLK Post-Scalar
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#define SR1E_VCLK_MCLK_DIV2 0x01 // MCLK Divide by 2 (when SR1F[6] = 1)
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#define SR1F 0x1F // MCLK Frequency and VCLK Source Select
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#define SR1F_VCLK_SRC 0x40 // VCLK Source Select
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#define SR1F_MCLK_FREQ 0x3F // MCLK Frequency
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#define SR20 0x20 // Miscellaneous Control Register 2
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#define SR20_9MCLK_RAS 0x40 // Select 9-MCLK RAS# Cycles for EDO DRAMs
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#define SR20_VCLKDIV4 0x02 // Set VCLK0, 1 Source to VCLK VCO/4
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#define SR2F 0x2F // HFA FIFO Threshold for Surrounding
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// Graphics Register
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#define SR2F_HFAFIFOGFX_THRESH 0x0F // HFA FIFO Threshold for Surr. Gfx
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#define SR32 0x32 // HFA FIFO Threshold in VW and DAC
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// IREF Power Control Register
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#define SR32_HFAFIFOMVW_THRESH 0x07 // HFA FIFO Thresh in VW
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#define SR34 0x34 // Host CPU Cycle Stop Control Register
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#define SR34_CPUSTOP_ENABLE 0x10 // Terminate Paged Host CPU Cycles when
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// Re-starting is Disabled
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#define SR34_DSTN_CPUSTOP 0x08 // Stop Host CPU Cycle before Half-
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// Frame Accelerator Cycle
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#define SR34_VPORT_CPUSTOP 0x04 // Stop Host CPU Cycle before V-Port cycle
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#define SR34_MVW_CPUSTOP 0x02 // Stop Host CPU Cycle before VW cycle
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#define SR34_GFX_CPUSTOP 0x01 // Stop Host CPU Cycle before CRT
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// Monitor cycle
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#define GFXFIFO_THRESH 8
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//typedef struct PROGREGS_
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//{
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// BYTE bSR2F;
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// BYTE bSR32;
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// BYTE bSR34;
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//
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// BYTE bCR42;
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// BYTE bCR51;
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// BYTE bCR5A;
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// BYTE bCR5D;
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//}PROGREGS, FAR *LPPROGREGS;
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//
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#if 0 //myf32
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typedef struct BWREGS_
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{
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BYTE bSR2F;
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BYTE bSR32;
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BYTE bSR34;
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BYTE bCR42;
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BYTE bCR51;
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BYTE bCR5A;
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BYTE bCR5D;
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BYTE bCR5F;
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}BWREGS, FAR *LPBWREGS;
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#endif
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/*
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* Function prototypes
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*/
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//BOOL IsSufficientBandwidth7555 (WORD, WORD, DWORD, DWORD, DWORD, DWORD,
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//DWORD, DWORD, LPBWREGS);
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//BOOL IsSufficientBandwidth7555 (WORD, LPRECTL, LPRECTL, DWORD);
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// 7555BW.c
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//static int ScaleMultiply(DWORD, // Factor 1
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// DWORD, // Factor 2
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// LPDWORD); // Pointer to returned product
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//BOOL ChipCalcMCLK(LPBWREGS, // Current register settings
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// LPDWORD); // Pointer to returned MCLK
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//BOOL ChipCalcVCLK(LPBWREGS, // Current register settings
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// LPDWORD); // Pointer to returned VCLK
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//BOOL ChipGetMCLK(LPDWORD); // Pointer to returned MCLK
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//BOOL ChipGetVCLK(LPDWORD); // Pointer to returned VCLK
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//BOOL ChipIsDSTN(LPBWREGS); // Current register settings
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//BOOL ChipCheckBandwidth(LPVIDCONFIG, // Current video configuration
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// LPBWREGS, // Current register values
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// LPPROGREGS); // Holds return value for regs
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// // (may be NULL)
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//BOOL ChipIsEnoughBandwidth(LPVIDCONFIG, // Current video configuration
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// LPPROGREGS); // Holds return value for regs
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// // (may be NULL)
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//// 7555IO.c
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//BOOL ChipIOReadBWRegs(LPBWREGS); // Filled with current reg settings
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//BOOL ChipIOWriteProgRegs(LPPROGREGS); // Writes register values
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//BOOL ChipIOReadProgRegs(LPPROGREGS); // Get current register settings
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//
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//#endif // _7555BW_H
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