185 lines
4.1 KiB
C
185 lines
4.1 KiB
C
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/*
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************************************************************************
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*
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* COMM.h
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*
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*
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* Portions Copyright (C) 1996-1998 National Semiconductor Corp.
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* All rights reserved.
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* Copyright (C) 1996-1998 Microsoft Corporation. All Rights Reserved.
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*
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*
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*
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*************************************************************************
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*/
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#ifndef COMM_H
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#define COMM_H
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/*
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* Size of the 16550 read and write FIFOs
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*/
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#define FIFO_SIZE 16
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/*
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* The programming interface to a UART (COM serial port)
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* consists of eight consecutive registers.
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* These are the port offsets from the UART's base I/O address.
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*/
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typedef enum comPortRegOffsets {
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XFER_REG_OFFSET = 0,
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INT_ENABLE_REG_OFFSET = 1,
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INT_ID_AND_FIFO_CNTRL_REG_OFFSET = 2,
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LINE_CONTROL_REG_OFFSET = 3,
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MODEM_CONTROL_REG_OFFSET = 4,
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LINE_STAT_REG_OFFSET = 5,
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MODEM_STAT_REG_OFFSET = 6,
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SCRATCH_REG_OFFSET = 7
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} comPortRegOffset;
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/*
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* Bits in the UART Interrupt-Id register.
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*/
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#define INTID_INTERRUPT_NOT_PENDING (UCHAR)(1 << 0)
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/*
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* Values for bits 2-1 of Interrupt-Id register:
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* 00 Modem Stat reg interrupt
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* 01 Transmitter holding reg interrupt
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* 10 Receive data ready interrupt
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* 11 Receive line status interrupt
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*
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*/
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#define INTID_INTIDMASK (UCHAR)(3 << 1)
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#define INTID_MODEMSTAT_INT (UCHAR)(0 << 1)
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#define INTID_XMITREG_INT (UCHAR)(1 << 1)
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#define INTID_RCVDATAREADY_INT (UCHAR)(2 << 1)
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#define INTID_RCVLINESTAT_INT (UCHAR)(3 << 1)
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/*
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* Bits in the UART line-status register.
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*/
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#define LINESTAT_DATAREADY (UCHAR)(1 << 0)
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#define LINESTAT_OVERRUNERROR (UCHAR)(1 << 1)
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#define LINESTAT_PARITYERROR (UCHAR)(1 << 2)
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#define LINESTAT_FRAMINGERROR (UCHAR)(1 << 3)
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#define LINESTAT_BREAK (UCHAR)(1 << 4)
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#define LINESTAT_XMIT_HOLDING_REG_EMPTY (UCHAR)(1 << 5)
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#define LINESTAT_XMIT_SHIFT_AND_HOLDING_REG_EMPTY (UCHAR)(1 << 6)
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/*
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* These are bits in the UART's interrupt-enable register (INT_ENABLE_REG_OFFSET).
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*/
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#define DATA_AVAIL_INT_ENABLE (1 << 0)
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#define READY_FOR_XMIT_INT_ENABLE (1 << 1)
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#define RCV_LINE_STAT_INT_ENABLE (1 << 2)
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#define MODEM_STAT_INT_ENABLE (1 << 3)
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#define RCV_MODE_INTS_ENABLE (DATA_AVAIL_INT_ENABLE)
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#define XMIT_MODE_INTS_ENABLE (READY_FOR_XMIT_INT_ENABLE|DATA_AVAIL_INT_ENABLE)
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#define ALL_INTS_ENABLE (RCV_MODE_INTS_ENABLE | XMIT_MODE_INTS_ENABLE)
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#define ALL_INTS_DISABLE 0
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/*
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* These are fine-tuning parameters for the COM port ISR.
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* Number of times we poll a COM port register waiting
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* for a value which may/must appear.
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*/
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#define REG_POLL_LOOPS 2
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#define REG_TIMEOUT_LOOPS 1000000
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typedef enum {
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STATE_INIT = 0,
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STATE_GOT_BOF,
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STATE_ACCEPTING,
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STATE_ESC_SEQUENCE,
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STATE_SAW_EOF,
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STATE_CLEANUP
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} portRcvState;
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/*
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* This is the information that we need to keep for each COMM port.
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*/
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typedef struct _comPortInfo {
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/*
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* HW resource settings for COM port.
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*/
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//
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// Physical address of the ConfigIoBaseAddress
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//
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ULONG ConfigIoBasePhysAddr;
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//
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// Virtual address of the ConfigIoBaseAddress
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//
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PUCHAR ConfigIoBaseAddr;
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//
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// Physical address of the UartIoBaseAddress
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//
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ULONG ioBasePhys;
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//
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// Virtual address of the UartIoBaseAddress
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//
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PUCHAR ioBase;
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//
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// Interrupt number this adapter is using.
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//
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UINT irq;
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//
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// DMA Cnannel Number.
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//
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UCHAR DMAChannel;
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/*
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* Is this COM port a 16550 with a 16-byte FIFO or
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* a 16450/8250 with no FIFO ?
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*/
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BOOLEAN haveFIFO;
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/*
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* Data for our rcv state machine.
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*/
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UCHAR rawBuf[FIFO_SIZE];
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PUCHAR readBuf;
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PUCHAR dmaReadBuf;
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UINT readBufPos;
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portRcvState rcvState;
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//
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// Debug counter for packets received correctly.
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//
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UINT PacketsReceived_DEBUG;
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/*
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* Data for send state machine
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*/
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PUCHAR writeBuf;
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UINT writeBufPos;
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UINT writeBufLen;
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UINT SirWritePending;
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UINT IsrDoneWithPacket;
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/*
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* Dongle or part-specific information
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*/
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dongleCapabilities hwCaps;
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UINT dongleContext;
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} comPortInfo;
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#endif COMM_H
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