859 lines
22 KiB
C
859 lines
22 KiB
C
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/*++
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Copyright (c) 1990-2000 Microsoft Corporation
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Module Name:
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bootvid.c
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Abstract:
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This is the device independent portion of the graphical boot dll.
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Author:
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Erick Smith (ericks) Oct. 1997
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Environment:
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kernel mode only
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Revision History:
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--*/
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#include <nthal.h>
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#include <hal.h>
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#include "cmdcnst.h"
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#include <bootvid.h>
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#include "vga.h"
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extern USHORT VGA_640x480[];
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extern USHORT AT_Initialization[];
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extern int curr_x;
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extern int curr_y;
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PUCHAR VgaBase;
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PUCHAR VgaRegisterBase;
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NTSTATUS
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InitBusCallback(
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IN PVOID Context,
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IN PUNICODE_STRING PathName,
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IN INTERFACE_TYPE BusType,
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IN ULONG BusNumber,
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IN PKEY_VALUE_FULL_INFORMATION *BusInformation,
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IN CONFIGURATION_TYPE ControllerType,
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IN ULONG ControllerNumber,
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IN PKEY_VALUE_FULL_INFORMATION *ControllerInformation,
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IN CONFIGURATION_TYPE PeripheralType,
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IN ULONG PeripheralNumber,
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IN PKEY_VALUE_FULL_INFORMATION *PeripheralInformation
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)
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{
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return STATUS_SUCCESS;
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}
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BOOLEAN
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VidInitialize(
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BOOLEAN SetMode
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)
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/*++
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Routine Description:
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This routine checks for the existance of a VGA chip, and initializes
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it.
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Arguments:
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SetMode - Set to true if you want this routine to initialize mode.
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Return Value:
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TRUE - if the boot driver found vga and initialized correctly,
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FALSE - otherwise.
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--*/
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{
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PHYSICAL_ADDRESS IoAddress;
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PHYSICAL_ADDRESS MemoryAddress;
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ULONG AddressSpace;
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PHYSICAL_ADDRESS TranslatedAddress;
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PUCHAR mappedAddress;
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ULONG_PTR TranslateContext;
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//
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// Saftey check. Allows migration from old HalDisplayString
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// support to bootvid, if the HAL didn't supply the routine
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//
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// HALPDISPATCH->HalFindBusAddressTranslation
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//
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// this routine cannot succeed.
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//
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if (!HALPDISPATCH->HalFindBusAddressTranslation) {
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return FALSE;
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}
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//
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// Start search with "no previous" context.
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//
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TranslateContext = 0;
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//
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// Set up the addresses we need to translate.
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//
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IoAddress.LowPart = 0x0;
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IoAddress.HighPart = 0;
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MemoryAddress.LowPart = 0xa0000;
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MemoryAddress.HighPart = 0;
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//
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// While there are more busses to examine try to map the VGA
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// registers.
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//
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while (TRUE) {
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AddressSpace = 1; // we are requesting IO space.
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if (!HALPDISPATCH->HalFindBusAddressTranslation(
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IoAddress,
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&AddressSpace,
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&TranslatedAddress,
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&TranslateContext,
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TRUE)) {
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//
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// Failed to find a bus with the VGA device on it.
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//
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return FALSE;
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}
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//
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// We were able to translate the address. Now, map the
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// translated address.
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//
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if (AddressSpace & 0x1) {
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VgaRegisterBase = (PUCHAR)(DWORD_PTR) TranslatedAddress.QuadPart;
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} else {
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VgaRegisterBase = (PUCHAR) MmMapIoSpace(TranslatedAddress,
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0x400,
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FALSE);
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}
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//
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// Now that we have the VGA I/O ports, check to see if a VGA
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// device is present.
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//
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if (!VgaIsPresent()) {
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if (!(AddressSpace & 0x1)) {
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MmUnmapIoSpace(VgaRegisterBase, 0x400);
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}
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//
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// Continue on next bus that has this IO address.
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//
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continue;
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}
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//
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//
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// Map the frame buffer.
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//
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AddressSpace = 0; // we are requesting memory not IO.
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//
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// Map the video memory so that we can write to the screen after
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// setting a mode.
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//
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// Note: We assume the memory will be on the same bus as the IO.
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//
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if (HALPDISPATCH->HalFindBusAddressTranslation(
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MemoryAddress,
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&AddressSpace,
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&TranslatedAddress,
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&TranslateContext,
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FALSE)) {
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//
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// We were able to translate the address. Now, map the
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// translated address.
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//
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if (AddressSpace & 0x1) {
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VgaBase = (PUCHAR)(DWORD_PTR) TranslatedAddress.QuadPart;
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} else {
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VgaBase = (PUCHAR) MmMapIoSpace(TranslatedAddress,
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0x20000, // 128k
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FALSE);
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}
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//
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// Life is good.
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//
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break;
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}
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}
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//
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// Initialize the display
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//
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if (SetMode) {
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curr_x = curr_y = 0;
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HalResetDisplay();
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VgaInterpretCmdStream(AT_Initialization);
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}
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return TRUE;
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}
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VOID
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VidResetDisplay(
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BOOLEAN SetMode
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)
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{
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curr_x = curr_y = 0;
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if (SetMode) {
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HalResetDisplay();
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}
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VgaInterpretCmdStream(AT_Initialization);
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InitializePalette();
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VidSolidColorFill(0,0,639,479,0);
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}
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BOOLEAN
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VgaInterpretCmdStream(
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PUSHORT pusCmdStream
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)
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/*++
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Routine Description:
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Interprets the appropriate command array to set up VGA registers for the
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requested mode. Typically used to set the VGA into a particular mode by
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programming all of the registers
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Arguments:
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pusCmdStream - array of commands to be interpreted.
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Return Value:
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The status of the operation (can only fail on a bad command); TRUE for
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success, FALSE for failure.
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--*/
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{
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ULONG ulCmd;
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ULONG_PTR ulPort;
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UCHAR jValue;
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USHORT usValue;
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ULONG culCount;
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ULONG ulIndex;
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ULONG_PTR ulBase;
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if (pusCmdStream == NULL) {
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//KdPrint(("VgaInterpretCmdStream: pusCmdStream == NULL\n"));
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return TRUE;
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}
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ulBase = (ULONG_PTR) VgaRegisterBase;
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//
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// Now set the adapter to the desired mode.
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//
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while ((ulCmd = *pusCmdStream++) != EOD) {
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//
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// Determine major command type
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//
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switch (ulCmd & 0xF0) {
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//
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// Basic input/output command
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//
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case INOUT:
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//
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// Determine type of inout instruction
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//
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if (!(ulCmd & IO)) {
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//
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// Out instruction. Single or multiple outs?
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//
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if (!(ulCmd & MULTI)) {
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//
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// Single out. Byte or word out?
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//
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if (!(ulCmd & BW)) {
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//
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// Single byte out
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//
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ulPort = *pusCmdStream++;
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jValue = (UCHAR) *pusCmdStream++;
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WRITE_PORT_UCHAR((PUCHAR)(ulBase+ulPort),
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jValue);
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} else {
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//
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// Single word out
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//
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ulPort = *pusCmdStream++;
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usValue = *pusCmdStream++;
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WRITE_PORT_USHORT((PUSHORT)(ulBase+ulPort),
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usValue);
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}
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} else {
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//
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// Output a string of values
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// Byte or word outs?
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//
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if (!(ulCmd & BW)) {
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//
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// String byte outs. Do in a loop; can't use
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// VideoPortWritePortBufferUchar because the data
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// is in USHORT form
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//
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ulPort = ulBase + *pusCmdStream++;
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culCount = *pusCmdStream++;
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while (culCount--) {
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jValue = (UCHAR) *pusCmdStream++;
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WRITE_PORT_UCHAR((PUCHAR)ulPort,
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jValue);
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}
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} else {
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//
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// String word outs
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//
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ulPort = *pusCmdStream++;
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culCount = *pusCmdStream++;
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WRITE_PORT_BUFFER_USHORT((PUSHORT)
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(ulBase + ulPort), pusCmdStream, culCount);
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pusCmdStream += culCount;
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}
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}
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} else {
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// In instruction
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//
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// Currently, string in instructions aren't supported; all
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// in instructions are handled as single-byte ins
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//
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// Byte or word in?
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//
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if (!(ulCmd & BW)) {
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//
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// Single byte in
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//
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ulPort = *pusCmdStream++;
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jValue = READ_PORT_UCHAR((PUCHAR)ulBase+ulPort);
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} else {
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//
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// Single word in
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//
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ulPort = *pusCmdStream++;
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usValue = READ_PORT_USHORT((PUSHORT)
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(ulBase+ulPort));
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}
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}
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break;
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//
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// Higher-level input/output commands
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//
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case METAOUT:
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//
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// Determine type of metaout command, based on minor
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// command field
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//
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switch (ulCmd & 0x0F) {
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//
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// Indexed outs
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//
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case INDXOUT:
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ulPort = ulBase + *pusCmdStream++;
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culCount = *pusCmdStream++;
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ulIndex = *pusCmdStream++;
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while (culCount--) {
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usValue = (USHORT) (ulIndex +
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(((ULONG)(*pusCmdStream++)) << 8));
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WRITE_PORT_USHORT((PUSHORT)ulPort, usValue);
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ulIndex++;
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}
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break;
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//
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// Masked out (read, AND, XOR, write)
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//
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case MASKOUT:
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||
|
|
ulPort = *pusCmdStream++;
|
||
|
|
jValue = READ_PORT_UCHAR((PUCHAR)ulBase+ulPort);
|
||
|
|
jValue &= *pusCmdStream++;
|
||
|
|
jValue ^= *pusCmdStream++;
|
||
|
|
WRITE_PORT_UCHAR((PUCHAR)ulBase + ulPort,
|
||
|
|
jValue);
|
||
|
|
break;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Attribute Controller out
|
||
|
|
//
|
||
|
|
|
||
|
|
case ATCOUT:
|
||
|
|
|
||
|
|
ulPort = ulBase + *pusCmdStream++;
|
||
|
|
culCount = *pusCmdStream++;
|
||
|
|
ulIndex = *pusCmdStream++;
|
||
|
|
|
||
|
|
while (culCount--) {
|
||
|
|
|
||
|
|
// Write Attribute Controller index
|
||
|
|
WRITE_PORT_UCHAR((PUCHAR)ulPort,
|
||
|
|
(UCHAR)ulIndex);
|
||
|
|
|
||
|
|
// Write Attribute Controller data
|
||
|
|
jValue = (UCHAR) *pusCmdStream++;
|
||
|
|
WRITE_PORT_UCHAR((PUCHAR)ulPort, jValue);
|
||
|
|
|
||
|
|
ulIndex++;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
//
|
||
|
|
// None of the above; error
|
||
|
|
//
|
||
|
|
default:
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
//
|
||
|
|
// NOP
|
||
|
|
//
|
||
|
|
|
||
|
|
case NCMD:
|
||
|
|
|
||
|
|
break;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Unknown command; error
|
||
|
|
//
|
||
|
|
|
||
|
|
default:
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
return TRUE;
|
||
|
|
|
||
|
|
} // end VgaInterpretCmdStream()
|
||
|
|
|
||
|
|
BOOLEAN
|
||
|
|
VgaIsPresent(
|
||
|
|
VOID
|
||
|
|
)
|
||
|
|
|
||
|
|
/*++
|
||
|
|
|
||
|
|
Routine Description:
|
||
|
|
|
||
|
|
This routine returns TRUE if a VGA is present. Determining whether a VGA
|
||
|
|
is present is a two-step process. First, this routine walks bits through
|
||
|
|
the Bit Mask register, to establish that there are readable indexed
|
||
|
|
registers (EGAs normally don't have readable registers, and other adapters
|
||
|
|
are unlikely to have indexed registers). This test is done first because
|
||
|
|
it's a non-destructive EGA rejection test (correctly rejects EGAs, but
|
||
|
|
doesn't potentially mess up the screen or the accessibility of display
|
||
|
|
memory). Normally, this would be an adequate test, but some EGAs have
|
||
|
|
readable registers, so next, we check for the existence of the Chain4 bit
|
||
|
|
in the Memory Mode register; this bit doesn't exist in EGAs. It's
|
||
|
|
conceivable that there are EGAs with readable registers and a register bit
|
||
|
|
where Chain4 is stored, although I don't know of any; if a better test yet
|
||
|
|
is needed, memory could be written to in Chain4 mode, and then examined
|
||
|
|
plane by plane in non-Chain4 mode to make sure the Chain4 bit did what it's
|
||
|
|
supposed to do. However, the current test should be adequate to eliminate
|
||
|
|
just about all EGAs, and 100% of everything else.
|
||
|
|
|
||
|
|
If this function fails to find a VGA, it attempts to undo any damage it
|
||
|
|
may have inadvertently done while testing. The underlying assumption for
|
||
|
|
the damage control is that if there's any non-VGA adapter at the tested
|
||
|
|
ports, it's an EGA or an enhanced EGA, because: a) I don't know of any
|
||
|
|
other adapters that use 3C4/5 or 3CE/F, and b), if there are other
|
||
|
|
adapters, I certainly don't know how to restore their original states. So
|
||
|
|
all error recovery is oriented toward putting an EGA back in a writable
|
||
|
|
state, so that error messages are visible. The EGA's state on entry is
|
||
|
|
assumed to be text mode, so the Memory Mode register is restored to the
|
||
|
|
default state for text mode.
|
||
|
|
|
||
|
|
If a VGA is found, the VGA is returned to its original state after
|
||
|
|
testing is finished.
|
||
|
|
|
||
|
|
Arguments:
|
||
|
|
|
||
|
|
None.
|
||
|
|
|
||
|
|
Return Value:
|
||
|
|
|
||
|
|
TRUE if a VGA is present, FALSE if not.
|
||
|
|
|
||
|
|
--*/
|
||
|
|
|
||
|
|
{
|
||
|
|
UCHAR originalGCAddr;
|
||
|
|
UCHAR originalSCAddr;
|
||
|
|
UCHAR originalBitMask;
|
||
|
|
UCHAR originalReadMap;
|
||
|
|
UCHAR originalMemoryMode;
|
||
|
|
UCHAR testMask;
|
||
|
|
BOOLEAN returnStatus;
|
||
|
|
|
||
|
|
//
|
||
|
|
// Remember the original state of the Graphics Controller Address register.
|
||
|
|
//
|
||
|
|
|
||
|
|
originalGCAddr = READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Write the Read Map register with a known state so we can verify
|
||
|
|
// that it isn't changed after we fool with the Bit Mask. This ensures
|
||
|
|
// that we're dealing with indexed registers, since both the Read Map and
|
||
|
|
// the Bit Mask are addressed at GRAPH_DATA_PORT.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_READ_MAP);
|
||
|
|
|
||
|
|
//
|
||
|
|
// If we can't read back the Graphics Address register setting we just
|
||
|
|
// performed, it's not readable and this isn't a VGA.
|
||
|
|
//
|
||
|
|
|
||
|
|
if ((READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT) & GRAPH_ADDR_MASK) != IND_READ_MAP) {
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set the Read Map register to a known state.
|
||
|
|
//
|
||
|
|
|
||
|
|
originalReadMap = READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, READ_MAP_TEST_SETTING);
|
||
|
|
|
||
|
|
if (READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT) != READ_MAP_TEST_SETTING) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// The Read Map setting we just performed can't be read back; not a
|
||
|
|
// VGA. Restore the default Read Map state.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, READ_MAP_DEFAULT);
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Remember the original setting of the Bit Mask register.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_BIT_MASK);
|
||
|
|
if ((READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT) & GRAPH_ADDR_MASK) != IND_BIT_MASK) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// The Graphics Address register setting we just made can't be read
|
||
|
|
// back; not a VGA. Restore the default Read Map state.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_READ_MAP);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, READ_MAP_DEFAULT);
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
originalBitMask = READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Set up the initial test mask we'll write to and read from the Bit Mask.
|
||
|
|
//
|
||
|
|
|
||
|
|
testMask = 0xBB;
|
||
|
|
|
||
|
|
do {
|
||
|
|
|
||
|
|
//
|
||
|
|
// Write the test mask to the Bit Mask.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, testMask);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Make sure the Bit Mask remembered the value.
|
||
|
|
//
|
||
|
|
|
||
|
|
if (READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT) != testMask) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// The Bit Mask is not properly writable and readable; not a VGA.
|
||
|
|
// Restore the Bit Mask and Read Map to their default states.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, BIT_MASK_DEFAULT);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_READ_MAP);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, READ_MAP_DEFAULT);
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// Cycle the mask for next time.
|
||
|
|
//
|
||
|
|
|
||
|
|
testMask >>= 1;
|
||
|
|
|
||
|
|
} while (testMask != 0);
|
||
|
|
|
||
|
|
//
|
||
|
|
// There's something readable at GRAPH_DATA_PORT; now switch back and
|
||
|
|
// make sure that the Read Map register hasn't changed, to verify that
|
||
|
|
// we're dealing with indexed registers.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_READ_MAP);
|
||
|
|
if (READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT) != READ_MAP_TEST_SETTING) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// The Read Map is not properly writable and readable; not a VGA.
|
||
|
|
// Restore the Bit Mask and Read Map to their default states, in case
|
||
|
|
// this is an EGA, so subsequent writes to the screen aren't garbled.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, READ_MAP_DEFAULT);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_BIT_MASK);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, BIT_MASK_DEFAULT);
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
|
||
|
|
//
|
||
|
|
// We've pretty surely verified the existence of the Bit Mask register.
|
||
|
|
// Put the Graphics Controller back to the original state.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, originalReadMap);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, IND_BIT_MASK);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_DATA_PORT, originalBitMask);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
GRAPH_ADDRESS_PORT, originalGCAddr);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Now, check for the existence of the Chain4 bit.
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Remember the original states of the Sequencer Address and Memory Mode
|
||
|
|
// registers.
|
||
|
|
//
|
||
|
|
|
||
|
|
originalSCAddr = READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT, IND_MEMORY_MODE);
|
||
|
|
if ((READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT) & SEQ_ADDR_MASK) != IND_MEMORY_MODE) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// Couldn't read back the Sequencer Address register setting we just
|
||
|
|
// performed.
|
||
|
|
//
|
||
|
|
|
||
|
|
return FALSE;
|
||
|
|
}
|
||
|
|
originalMemoryMode = READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_DATA_PORT);
|
||
|
|
|
||
|
|
//
|
||
|
|
// Toggle the Chain4 bit and read back the result. This must be done during
|
||
|
|
// sync reset, since we're changing the chaining state.
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Begin sync reset.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_USHORT((PUSHORT)(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT),
|
||
|
|
(IND_SYNC_RESET + (START_SYNC_RESET_VALUE << 8)));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Toggle the Chain4 bit.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT, IND_MEMORY_MODE);
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_DATA_PORT, (UCHAR)(originalMemoryMode ^ CHAIN4_MASK));
|
||
|
|
|
||
|
|
if (READ_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_DATA_PORT) != (UCHAR) (originalMemoryMode ^ CHAIN4_MASK)) {
|
||
|
|
|
||
|
|
//
|
||
|
|
// Chain4 bit not there; not a VGA.
|
||
|
|
// Set text mode default for Memory Mode register.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_DATA_PORT, MEMORY_MODE_TEXT_DEFAULT);
|
||
|
|
//
|
||
|
|
// End sync reset.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_USHORT((PUSHORT) (VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT),
|
||
|
|
(IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8)));
|
||
|
|
|
||
|
|
returnStatus = FALSE;
|
||
|
|
|
||
|
|
} else {
|
||
|
|
|
||
|
|
//
|
||
|
|
// It's a VGA.
|
||
|
|
//
|
||
|
|
|
||
|
|
//
|
||
|
|
// Restore the original Memory Mode setting.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_DATA_PORT, originalMemoryMode);
|
||
|
|
|
||
|
|
//
|
||
|
|
// End sync reset.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_USHORT((PUSHORT)(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT),
|
||
|
|
(USHORT)(IND_SYNC_RESET + (END_SYNC_RESET_VALUE << 8)));
|
||
|
|
|
||
|
|
//
|
||
|
|
// Restore the original Sequencer Address setting.
|
||
|
|
//
|
||
|
|
|
||
|
|
WRITE_PORT_UCHAR(VgaRegisterBase +
|
||
|
|
SEQ_ADDRESS_PORT, originalSCAddr);
|
||
|
|
|
||
|
|
returnStatus = TRUE;
|
||
|
|
}
|
||
|
|
|
||
|
|
return returnStatus;
|
||
|
|
|
||
|
|
} // VgaIsPresent()
|