381 lines
9.2 KiB
ArmAsm
381 lines
9.2 KiB
ArmAsm
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//
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// Module name:
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//
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// i64fwasm.s
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//
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// Author:
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//
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// Arad Rostampour (arad@fc.hp.com) Mar-21-99
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//
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// Description:
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//
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// Assembly routines for calling into SAL, PAL, and setting up translation registers
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//
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//--
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#include "ksia64.h"
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.sdata
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//
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// HalpSalSpinLock:
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//
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// HAL private spinlock protecting generic SAL calls.
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//
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.align 128
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HalpSalSpinLock::
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data8 0
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//
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// HalpSalStateInfoSpinLock:
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//
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// HAL private spinlock protecting specific SAL STATE_INFO calls.
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//
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.align 128
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HalpSalStateInfoSpinLock::
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data8 0
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//
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// HalpMcaSpinLock
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//
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// HAL private spinlock protecting HAL internal MCA data structures and operations.
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// Including operations at IRQL DISPATCH_LEVEL and higher.
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//
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.align 128
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HalpMcaSpinLock::
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data8 0
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//
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// HalpInitSpinLock
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//
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// HAL private spinlock protecting HAL internal INIT data structures and operations.
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// Including operations at IRQL DISPATCH_LEVEL and higher.
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//
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.align 128
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HalpInitSpinLock::
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data8 0
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//
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// HalpCmcSpinLock
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//
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// HAL private spinlock protecting HAL internal CMC data structures and operations.
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// Including operations at IRQL DISPATCH_LEVEL and higher.
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//
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.align 128
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HalpCmcSpinLock::
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data8 0
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//
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// HalpCpeSpinLock
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//
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// HAL private spinlock protecting HAL internal CPE data structures and operations.
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// Including operations at IRQL DISPATCH_LEVEL and higher.
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//
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.align 128
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HalpCpeSpinLock::
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data8 0
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//
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// Definitions used in this file
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//
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// Bits to set for the Mode argument in the HalpSetupTranslationRegisters call
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#define SET_DTR_BIT 1
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#define SET_ITR_BIT 0
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// TR for PAL is:
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// ed=1, PPN=0 (to be ORed in), RWX privledge only for ring 0, dirty/accessed bit set,
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// cacheable memory, present bit set.
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#define HAL_SAL_PAL_TR_ATTRIB TR_VALUE(1,0,3,0,1,1,0,1)
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#define HAL_TR_ATTRIBUTE_PPN_MASK 0x0000FFFFFFFFF000
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.file "i64fwasm.s"
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// These globals are defined in i64fw.c
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.global HalpSalProcPointer
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.global HalpSalProcGlobalPointer
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.global HalpPalProcPointer
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//++
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//
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// VOID
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// HalpSalProc(
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// LONGLONG a0, /* SAL function ID */
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// LONGLONG a1, /* SAL argument */
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// LONGLONG a2, /* SAL argument */
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// LONGLONG a3, /* SAL argument */
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// LONGLONG a4, /* SAL argument */
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// LONGLONG a5, /* SAL argument */
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// LONGLONG a6, /* SAL argument */
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// LONGLONG a7 /* SAL argument */
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// );
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//
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// Routine Description:
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// This is a simple assembly wrapper that jumps directly to the SAL code. The ONLY
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// caller should be HalpSalCall. Other users must use the HalpSalCall API for
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// calling into the SAL.
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//
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// Return Values:
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// r8->r11 contain the 4 64-bit return values for SAL, r8 is the status
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//--
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NESTED_ENTRY(HalpSalProc)
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NESTED_SETUP(8,3,8,0)
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// copy args to outs
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mov out0 = a0
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mov out1 = a1
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mov out2 = a2
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mov out3 = a3
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mov out4 = a4
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mov out5 = a5
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mov out6 = a6
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mov out7 = a7
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;;
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// Simply load the address and branch to it
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addl t1 = @gprel(HalpSalProcPointer), gp
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addl t2 = @gprel(HalpSalProcGlobalPointer), gp
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;;
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mov loc2 = gp
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ld8 t0 = [t1]
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;;
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ld8 gp = [t2]
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mov bt0 = t0
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rsm 1 << PSR_I // disable interrupts
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;;
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// br.sptk.many bt0
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br.call.sptk brp = bt0
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;;
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mov gp = loc2
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ssm 1 << PSR_I // enable interrupts
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;;
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NESTED_RETURN
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NESTED_EXIT(HalpSalProc)
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//++
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//
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// VOID
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// HalpPalProc(
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// LONGLONG a0, /* PAL function ID */
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// LONGLONG a1, /* PAL argument */
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// LONGLONG a2, /* PAL argument */
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// LONGLONG a3 /* PAL argument */
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// );
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//
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// Routine Description
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// This routine sets up the correct registers for input into PAL depending on
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// if the call uses static or stacked registers, turns off interrupts, ensures
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// the correct bank registers are being used and calls into the PAL. The ONLY
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// caller should be HalpPalCall. Other users must use the HalpPalCall API for
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// calling into the PAL.
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//
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// Return Values:
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// r8->r11 contain the 4 64-bit return values for PAL, r8 is the status
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//--
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NESTED_ENTRY(HalpPalProc)
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NESTED_SETUP(4,3,4,0)
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PROLOGUE_END
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// For both the static and stacked register conventions, load r28 with FunctionID
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mov r28 = a0
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// If static register calling convention (1-255, 512-767), copy arguments to r29->r31
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// Otherwise, copy to out0->out3 so they are in r32->r35 in PAL_PROC
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mov t0 = a0
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;;
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shr t0 = t0, 8
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;;
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tbit.z pt0, pt1 = t0, 0
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;;
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//
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// Static proc: do br not call
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//
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(pt0) mov r29 = a1
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(pt0) mov r30 = a2
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(pt0) mov r31 = a3
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//
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// Stacked call
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//
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(pt1) mov out0 = a0
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(pt1) mov out1 = a1
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(pt1) mov out2 = a2
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(pt1) mov out3 = a3
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// Load up the address of PAL_PROC and call it
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addl t1 = @gprel(HalpPalProcPointer), gp
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;;
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ld8 t0 = [t1]
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;;
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mov bt0 = t0
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// Call into PAL_PROC
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(pt0) addl t1 = @ltoff(PalReturn), gp
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;;
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(pt0) ld8 t0 = [t1]
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;;
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(pt0) mov brp = t0
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;;
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// Disable interrupts
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DISABLE_INTERRUPTS(loc2)
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;;
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srlz.d
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;;
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(pt0) br.sptk.many bt0
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;;
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(pt1) br.call.sptk brp = bt0
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;;
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PalReturn:
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// Restore the interrupt state
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RESTORE_INTERRUPTS(loc2)
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;;
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NESTED_RETURN
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NESTED_EXIT(HalpPalProc)
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//++
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//
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// VOID
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// HalpPalProcPhysicalStatic(
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// LONGLONG a0, /* PAL function ID */
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// LONGLONG a1, /* PAL argument */
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// LONGLONG a2, /* PAL argument */
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// LONGLONG a3 /* PAL argument */
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// );
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//
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// Routine Description
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// This routine sets up the correct registers for input into PAL turns off interrupts,
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// ensures the correct bank registers are being used and calls into the PAL in PHYSICAL
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// mode since some of the calls require it. The ONLY caller should be HalpPalCall.
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// Other users must use the HalpPalCall API for calling into the PAL.
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//
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// Return Values:
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// r8->r11 contain the 4 64-bit return values for PAL, r8 is the status
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//--
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NESTED_ENTRY(HalpPalProcPhysicalStatic)
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NESTED_SETUP(4,3,4,0)
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PROLOGUE_END
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mov r28 = a0
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mov r29 = a1
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mov r30 = a2
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mov r31 = a3
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// Disable interrupts
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DISABLE_INTERRUPTS(loc2)
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;;
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srlz.d
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;;
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// For now, return unimplemented
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//
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// Need to switch into physical mode before calling into PAL, so could:
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//
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// a) Map everything through Region 4, simply turn off translation, and
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// be identity mapped in an uncacheable area (any issues?)
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//
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// b) Setup IIP and IPSR to jump to a physical address in physical mode
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// by doing an RFI.
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movl r8 = -1
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movl r9 = 0
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movl r10 = 0
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movl r11 = 0
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// Restore the interrupt state
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RESTORE_INTERRUPTS(loc2)
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;;
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srlz.d
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;;
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NESTED_RETURN
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NESTED_EXIT(HalpPalProcPhysicalStatic)
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//++
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//
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// VOID
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// HalpPalProcPhysicalStacked(
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// LONGLONG a0, /* PAL function ID */
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// LONGLONG a1, /* PAL argument */
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// LONGLONG a2, /* PAL argument */
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// LONGLONG a3 /* PAL argument */
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// );
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//
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// Routine Description
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// This routine calls PAL in physical mode for the stacked calling
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// convention. The ONLY caller should be HalpPalCall. Other users must
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// use the HalpPalCall API for calling into the PAL.
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//
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// Return Values:
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// r8->r11 contain the 4 64-bit return values for PAL, r8 is the status
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//--
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NESTED_ENTRY(HalpPalProcPhysicalStacked)
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NESTED_SETUP(4,3,4,0)
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PROLOGUE_END
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// Setup the input parameters for PAL (note r28 must specify the function ID as well)
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mov r28 = a0
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mov out0 = a0
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mov out1 = a1
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mov out2 = a2
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mov out3 = a3
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// Disable interrupts
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DISABLE_INTERRUPTS(loc2)
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;;
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srlz.d
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;;
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// For now, return unimplemented as we can not transition to physical
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// mode using RFI with the stacked convention. There are RSE issues
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// as well as needing psr.ic bit set to set IIP and other registers,
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// but memory arguments aren't mapped with a TR, so they could cause
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// a fault.
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movl r8 = -1
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movl r9 = 0
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movl r10 = 0
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movl r11 = 0
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// Restore the interrupt state
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RESTORE_INTERRUPTS(loc2)
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;;
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srlz.d
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;;
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NESTED_RETURN
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NESTED_EXIT(HalpPalProcPhysicalStacked)
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