300 lines
7.1 KiB
NASM
300 lines
7.1 KiB
NASM
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;Module Name
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; imca.asm
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;
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;Abstract:
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; Assembly support needed for Intel MCA
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;
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; Author:
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; Anil Aggarwal (Intel Corp)
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;
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;Revision History:
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;
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;
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;--
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.586p
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.xlist
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include hal386.inc
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include callconv.inc
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include i386\kimacro.inc
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.list
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EXTRNP _HalpMcaExceptionHandler,0
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EXTRNP _KeBugCheckEx,5,IMPORT
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KGDT_MCA_TSS EQU 0A0H
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MINIMUM_TSS_SIZE EQU TssIoMaps
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;
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; TEXT Segment
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;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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_TEXT SEGMENT PARA PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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.586p
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;++
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;
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;VOID
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;HalpSerialize(
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; VOID
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; )
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;
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; Routine Description:
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; This function implements the fence operation for out-of-order execution
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;
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; Arguments:
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; None
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;
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; Return Value:
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; None
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;
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;--
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cPublicProc _HalpSerialize,0
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push ebx
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xor eax, eax
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cpuid
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pop ebx
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stdRET _HalpSerialize
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stdENDP _HalpSerialize
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;++
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;
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; Routine Description:
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;
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; Machine Check exception handler
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;
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;
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; Arguments:
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;
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; Return value:
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;
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; If the error is non-restartable, we will bugcheck.
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; Otherwise, we just return
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;
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;--
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ASSUME DS:NOTHING, SS:NOTHING, ES:NOTHING
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align dword
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public _HalpMcaExceptionHandlerWrapper
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_HalpMcaExceptionHandlerWrapper proc
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.FPO (0, 0, 0, 0, 0, 2)
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cli
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;
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; Update the TSS pointer in the PCR to point to the MCA TSS
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; (which is what we're running on, or else we wouldn't be here)
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;
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push dword ptr PCR[PcTss]
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mov eax, PCR[PcGdt]
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mov ch, [eax+KGDT_MCA_TSS+KgdtBaseHi]
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mov cl, [eax+KGDT_MCA_TSS+KgdtBaseMid]
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shl ecx, 16
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mov cx, [eax+KGDT_MCA_TSS+KgdtBaseLow]
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mov PCR[PcTss], ecx
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;
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; Clear the busy bit in the TSS selector
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;
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mov ecx, PCR[PcGdt]
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lea eax, [ecx] + KGDT_MCA_TSS
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mov byte ptr [eax+5], 089h ; 32bit, dpl=0, present, TSS32, not busy
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;
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; Clear Nested Task bit in EFLAGS
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;
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pushfd
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and [esp], not 04000h
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popfd
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;
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; Check if there is a bugcheck-able error. If need to bugcheck, the
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; caller does it.
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;
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stdCall _HalpMcaExceptionHandler
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;
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; We're back which means that the error was restartable.
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;
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pop dword ptr PCR[PcTss] ; restore PcTss
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mov ecx, PCR[PcGdt]
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lea eax, [ecx] + KGDT_TSS
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mov byte ptr [eax+5], 08bh ; 32bit, dpl=0, present, TSS32, *busy*
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pushfd ; Set Nested Task bit in EFLAGS
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or [esp], 04000h ; so iretd will do a tast switch
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popfd
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iretd ; Return from MCA Exception handler
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jmp short _HalpMcaExceptionHandlerWrapper
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; For next Machine check exception
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_HalpMcaExceptionHandlerWrapper endp
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_TEXT ends
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INIT SEGMENT DWORD PUBLIC 'CODE'
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;++
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;VOID
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;HalpMcaCurrentProcessorSetTSS(
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; IN PULONG pTSS // MCE TSS area for this processor
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; )
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; Routine Description:
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; This function sets up the TSS for MCA exception 18
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;
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; Arguments:
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; pTSS : Pointer to the TSS to be used for MCE
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;
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; Return Value:
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; None
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;
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;--
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cPublicProc _HalpMcaCurrentProcessorSetTSS,1
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;
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; Edit IDT Entry for MCA Exception (18) to contain a task gate
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;
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mov ecx, PCR[PcIdt] ; Get IDT address
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lea eax, [ecx] + 090h ; MCA Exception is 18
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mov byte ptr [eax + 5], 085h ; P=1,DPL=0,Type=5
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mov word ptr [eax + 2], KGDT_MCA_TSS ; TSS Segment Selector
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mov edx, [esp+4] ; the address of TSS in edx
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;
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; Set various fields in TSS
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;
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mov eax, cr3
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mov [edx + TssCR3], eax
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;
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; Get double fault stack address
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;
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lea eax, [ecx] + 040h ; DF Exception is 8
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;
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; Get to TSS Descriptor of double fault handler TSS
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;
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xor ecx, ecx
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mov cx, word ptr [eax+2]
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add ecx, PCR[PcGdt]
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;
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; Get the address of TSS from this TSS Descriptor
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;
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mov ah, [ecx+KgdtBaseHi]
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mov al, [ecx+KgdtBaseMid]
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shl eax, 16
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mov ax, [ecx+KgdtBaseLow]
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;
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; Get ESP from DF TSS
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;
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mov ecx, [eax+038h]
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;
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; Set address of MCA Exception stack to double fault stack address
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;
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mov dword ptr [edx+038h], ecx ; Set ESP
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mov dword ptr [edx+TssEsp0], ecx ; Set ESP0
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mov dword ptr [edx+020h], offset FLAT:_HalpMcaExceptionHandlerWrapper ; set EIP
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mov dword ptr [edx+024h], 0 ; set EFLAGS
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mov word ptr [edx+04ch],KGDT_R0_CODE ; set value for CS
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mov word ptr [edx+058h],KGDT_R0_PCR ; set value for FS
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mov [edx+050h], ss
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mov word ptr [edx+048h],KGDT_R3_DATA OR RPL_MASK ; Es
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mov word ptr [edx+054h],KGDT_R3_DATA OR RPL_MASK ; Ds
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;
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; Part that gets done in KiInitialiazeTSS()
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;
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mov word ptr [edx + 08], KGDT_R0_DATA ; Set SS0
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mov word ptr [edx + 060h],0 ; Set LDT
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mov word ptr [edx + 064h],0 ; Set T bit
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mov word ptr [edx + 066h],020adh ; I/O Map base address = sizeof(KTSS)+1
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;
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; Edit GDT entry for KGDT_MCA_TSS to create a valid TSS Descriptor
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;
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mov ecx, PCR[PcGdt] ; Get GDT address
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lea eax, [ecx] + KGDT_MCA_TSS ; offset of MCA TSS in GDT
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mov ecx, eax
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;
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; Set Type field of TSS Descriptor
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;
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mov byte ptr [ecx + 5], 089H ; P=1, DPL=0, Type = 9
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;
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; Set Base Address field of TSS Descriptor
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;
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mov eax, edx ; TSS address in eax
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mov [ecx + KgdtBaseLow], ax
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shr eax, 16
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mov [ecx + KgdtBaseHi],ah
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mov [ecx + KgdtBaseMid],al
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;
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; Set Segment limit for TSS Descriptor
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;
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mov eax, MINIMUM_TSS_SIZE
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mov [ecx + KgdtLimitLow],ax
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stdRET _HalpMcaCurrentProcessorSetTSS
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stdENDP _HalpMcaCurrentProcessorSetTSS
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INIT ends
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PAGELK SEGMENT DWORD PUBLIC 'CODE'
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;++
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;
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;VOID
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;HalpSetCr4MCEBit(
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; VOID
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; )
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;
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; Routine Description:
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; This function sets the CR4.MCE bit
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;
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; Arguments:
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; None
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;
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; Return Value:
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; None
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;
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;--
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cPublicProc _HalpSetCr4MCEBit,0
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mov eax, cr4
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or eax, CR4_MCE
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mov cr4, eax
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stdRET _HalpSetCr4MCEBit
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stdENDP _HalpSetCr4MCEBit
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PAGELK ends
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end
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