390 lines
9 KiB
C
390 lines
9 KiB
C
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/*++
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Copyright (c) 1990 Microsoft Corporation
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Module Name:
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eisa.h
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Abstract:
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The module defines the structures, and defines for the EISA chip set.
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Author:
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Jeff Havens (jhavens) 19-Jun-1991
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Revision History:
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--*/
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#ifndef _EISA_
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#define _EISA_
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//
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// Define the DMA page register structure.
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//
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typedef struct _DMA_PAGE{
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UCHAR Reserved1;
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UCHAR Channel2;
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UCHAR Channel3;
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UCHAR Channel1;
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UCHAR Reserved2[3];
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UCHAR Channel0;
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UCHAR Reserved3;
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UCHAR Channel6;
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UCHAR Channel7;
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UCHAR Channel5;
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UCHAR Reserved4[3];
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UCHAR RefreshPage;
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}DMA_PAGE, *PDMA_PAGE;
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//
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// Define the DMA stop register structure.
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//
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typedef struct _DMA_CHANNEL_STOP {
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UCHAR ChannelLsb;
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UCHAR ChannelMsb;
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UCHAR ChannelHsb;
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UCHAR Reserved;
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}DMA_CHANNEL_STOP, *PDMA_CHANNEL_STOP;
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//
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// Define DMA 1 address and count structure.
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//
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typedef struct _DMA1_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR DmaBaseCount;
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}DMA1_ADDRESS_COUNT, *PDMA1_ADDRESS_COUNT;
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//
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// Define DMA 2 address and count structure.
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//
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typedef struct _DMA2_ADDRESS_COUNT {
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UCHAR DmaBaseAddress;
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UCHAR Reserved1;
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UCHAR DmaBaseCount;
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UCHAR Reserved2;
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}DMA2_ADDRESS_COUNT, *PDMA2_ADDRESS_COUNT;
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//
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// Define DMA 1 control register structure.
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//
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typedef struct _DMA1_CONTROL {
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DMA1_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR DmaRequest;
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UCHAR SingleMask;
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UCHAR Mode;
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UCHAR ClearBytePointer;
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UCHAR MasterClear;
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UCHAR ClearMask;
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UCHAR AllMask;
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}DMA1_CONTROL, *PDMA1_CONTROL;
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//
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// Define DMA 2 control register structure.
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//
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typedef struct _DMA2_CONTROL {
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DMA2_ADDRESS_COUNT DmaAddressCount[4];
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UCHAR DmaStatus;
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UCHAR Reserved1;
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UCHAR DmaRequest;
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UCHAR Reserved2;
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UCHAR SingleMask;
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UCHAR Reserved3;
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UCHAR Mode;
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UCHAR Reserved4;
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UCHAR ClearBytePointer;
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UCHAR Reserved5;
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UCHAR MasterClear;
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UCHAR Reserved6;
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UCHAR ClearMask;
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UCHAR Reserved7;
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UCHAR AllMask;
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UCHAR Reserved8;
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}DMA2_CONTROL, *PDMA2_CONTROL;
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//
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// Define Timer control register structure.
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//
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typedef struct _TIMER_CONTROL {
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UCHAR BcdMode : 1;
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UCHAR Mode : 3;
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UCHAR SelectByte : 2;
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UCHAR SelectCounter : 2;
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}TIMER_CONTROL, *PTIMER_CONTROL;
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//
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// Define Timer status register structure.
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//
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typedef struct _TIMER_STATUS {
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UCHAR BcdMode : 1;
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UCHAR Mode : 3;
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UCHAR SelectByte : 2;
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UCHAR CrContentsMoved : 1;
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UCHAR OutPin : 1;
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}TIMER_STATUS, *PTIMER_STATUS;
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//
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// Define Mode values.
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//
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#define TM_SIGNAL_END_OF_COUNT 0
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#define TM_ONE_SHOT 1
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#define TM_RATE_GENERATOR 2
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#define TM_SQUARE_WAVE 3
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#define TM_SOFTWARE_STROBE 4
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#define TM_HARDWARE_STROBE 5
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//
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// Define SelectByte values
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//
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#define SB_COUNTER_LATCH 0
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#define SB_LSB_BYTE 1
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#define SB_MSB_BYTE 2
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#define SB_LSB_THEN_MSB 3
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//
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// Define SelectCounter values.
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//
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#define SELECT_COUNTER_0 0
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#define SELECT_COUNTER_1 1
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#define SELECT_COUNTER_2 2
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#define SELECT_READ_BACK 3
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//
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// Define Timer clock for speaker.
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//
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#define TIMER_CLOCK_IN 1193167 // 1.193Mhz
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//
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// Define NMI Status/Control register structure.
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//
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typedef struct _NMI_STATUS {
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UCHAR SpeakerGate : 1;
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UCHAR SpeakerData : 1;
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UCHAR DisableEisaParity : 1;
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UCHAR DisableNmi : 1;
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UCHAR RefreshToggle : 1;
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UCHAR SpeakerTimer : 1;
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UCHAR IochkNmi : 1;
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UCHAR ParityNmi : 1;
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}NMI_STATUS, *PNMI_STATUS;
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//
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// Define NMI Enable register structure.
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//
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typedef struct _NMI_ENABLE {
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UCHAR RtClockAddress : 7;
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UCHAR NmiDisable : 1;
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}NMI_ENABLE, *PNMI_ENABLE;
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//
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// Define the NMI extended status and control register structure.
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//
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typedef struct _NMI_EXTENDED_CONTROL {
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UCHAR BusReset : 1;
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UCHAR EnableNmiPort : 1;
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UCHAR EnableFailSafeNmi : 1;
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UCHAR EnableBusMasterTimeout : 1;
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UCHAR Reserved1 : 1;
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UCHAR PendingPortNmi : 1;
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UCHAR PendingBusMasterTimeout : 1;
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UCHAR PendingFailSafeNmi : 1;
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}NMI_EXTENDED_CONTROL, *PNMI_EXTENDED_CONTROL;
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//
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// Define 82357 register structure.
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//
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typedef struct _EISA_CONTROL {
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DMA1_CONTROL Dma1BasePort; // Offset 0x000
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UCHAR Reserved0[16];
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UCHAR Interrupt1ControlPort0; // Offset 0x020
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UCHAR Interrupt1ControlPort1; // Offset 0x021
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UCHAR Reserved1[32 - 2];
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UCHAR Timer1; // Offset 0x40
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UCHAR RefreshRequest; // Offset 0x41
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UCHAR SpeakerTone; // Offset 0x42
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UCHAR CommandMode1; // Offset 0x43
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UCHAR Reserved17[4];
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UCHAR Timer2; // Offset 0x48
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UCHAR Reserved13;
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UCHAR CpuSpeedControl; // Offset 0x4a
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UCHAR CommandMode2; // Offset 0x4b
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UCHAR Reserved14[21];
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UCHAR NmiStatus; // Offset 0x61
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UCHAR Reserved15[14];
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UCHAR NmiEnable; // Offset 0x70
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UCHAR Reserved16[15];
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DMA_PAGE DmaPageLowPort; // Offset 0x080
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UCHAR Reserved2[16];
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UCHAR Interrupt2ControlPort0; // Offset 0x0a0
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UCHAR Interrupt2ControlPort1; // Offset 0x0a1
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UCHAR Reserved3[32-2];
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DMA2_CONTROL Dma2BasePort; // Offset 0x0c0
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UCHAR Reserved4[0x320];
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UCHAR Dma1CountHigh[8]; // Offset 0x400
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UCHAR Reserved5[2];
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UCHAR Dma1ChainingInterrupt; // Offset 0x40a
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UCHAR Dma1ExtendedModePort; // Offset 0x40b
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UCHAR MasterControlPort; // Offset 0x40c
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UCHAR SteppingLevelRegister; // Offset 0x40d
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UCHAR IspTest1; // Offset 0x40e
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UCHAR IspTest2; // Offset 0x40f
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UCHAR Reserved6[81];
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UCHAR ExtendedNmiResetControl; // Offset 0x461
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UCHAR NmiIoInterruptPort; // Offset 0x462
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UCHAR Reserved7;
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UCHAR LastMaster; // Offset 0x464
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UCHAR Reserved8[27];
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DMA_PAGE DmaPageHighPort; // Offset 0x480
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UCHAR Reserved12[48];
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UCHAR Dma2HighCount[16]; // Offset 0x4c0
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UCHAR Interrupt1EdgeLevel; // Offset 0x4d0
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UCHAR Interrupt2EdgeLevel; // Offset 0x4d1
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UCHAR Reserved9[2];
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UCHAR Dma2ChainingInterrupt; // Offset 0x4d4
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UCHAR Reserved10;
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UCHAR Dma2ExtendedModePort; // Offset 0x4d6
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UCHAR Reserved11[9];
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DMA_CHANNEL_STOP DmaChannelStop[8]; // Offset 0x4e0
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} EISA_CONTROL, *PEISA_CONTROL;
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//
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// Define initialization command word 1 structure.
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//
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typedef struct _INITIALIZATION_COMMAND_1 {
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UCHAR Icw4Needed : 1;
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UCHAR CascadeMode : 1;
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UCHAR Unused1 : 2;
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UCHAR InitializationFlag : 1;
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UCHAR Unused2 : 3;
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}INITIALIZATION_COMMAND_1, *PINITIALIZATION_COMMAND_1;
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//
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// Define initialization command word 4 structure.
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//
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typedef struct _INITIALIZATION_COMMAND_4 {
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UCHAR I80x86Mode : 1;
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UCHAR AutoEndOfInterruptMode : 1;
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UCHAR Unused1 : 2;
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UCHAR SpecialFullyNested : 1;
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UCHAR Unused2 : 3;
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}INITIALIZATION_COMMAND_4, *PINITIALIZATION_COMMAND_4;
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//
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// Define EISA interrupt controller operational command values.
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// Define operation control word 2 commands.
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//
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#define NONSPECIFIC_END_OF_INTERRUPT 0x20
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#define SPECIFIC_END_OF_INTERRUPT 0x60
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//
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// Define the IRQL which the slave intterrupts the master controller.
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//
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#define SLAVE_IRQL_LEVEL 2
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//
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// Define external EISA interupts
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//
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#define EISA_EXTERNAL_INTERRUPTS_1 0xf8
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#define EISA_EXTERNAL_INTERRUPTS_2 0xbe
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//
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// Define the DMA mode register structure.
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//
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typedef struct _DMA_EISA_MODE {
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UCHAR Channel : 2;
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UCHAR TransferType : 2;
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UCHAR AutoInitialize : 1;
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UCHAR AddressDecrement : 1;
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UCHAR RequestMode : 2;
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}DMA_EISA_MODE, *PDMA_EISA_MODE;
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//
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// Define TransferType values.
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//
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#define VERIFY_TRANSFER 0x00
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#define READ_TRANSFER 0x01 // Read from the device.
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#define WRITE_TRANSFER 0x02 // Write to the device.
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//
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// Define RequestMode values.
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//
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#define DEMAND_REQUEST_MODE 0x00
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#define SINGLE_REQUEST_MODE 0x01
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#define BLOCK_REQUEST_MODE 0x02
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#define CASCADE_REQUEST_MODE 0x03
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//
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// Define the DMA extended mode register structure.
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//
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typedef struct _DMA_EXTENDED_MODE {
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UCHAR ChannelNumber : 2;
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UCHAR TransferSize : 2;
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UCHAR TimingMode : 2;
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UCHAR EndOfPacketInput : 1;
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UCHAR StopRegisterEnabled : 1;
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}DMA_EXTENDED_MODE, *PDMA_EXTENDED_MODE;
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//
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// Define the DMA extended mode register transfer size values.
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//
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#define BY_BYTE_8_BITS 0
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#define BY_WORD_16_BITS 1
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#define BY_BYTE_32_BITS 2
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#define BY_BYTE_16_BITS 3
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//
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// Define the DMA extended mode timing mode values.
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//
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#define COMPATIBLITY_TIMING 0
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#define TYPE_A_TIMING 1
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#define TYPE_B_TIMING 2
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#define BURST_TIMING 3
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#ifndef DMA1_COMMAND_STATUS
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//
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// Define constants used by Intel 8237A DMA chip
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//
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#define DMA_SETMASK 4
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#define DMA_CLEARMASK 0
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#define DMA_READ 4 // These two appear backwards, but I think
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#define DMA_WRITE 8 // the DMA docs have them mixed up
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#define DMA_SINGLE_TRANSFER 0x40
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#define DMA_AUTO_INIT 0x10 // Auto initialization mode
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#endif
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#endif
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