199 lines
8.2 KiB
C
199 lines
8.2 KiB
C
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/*++ BUILD Version: 0001 // Increment this if a change has global effects
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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p5data.h
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Abstract:
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Header file for the p5 Extensible Object data definitions
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This file contains definitions to construct the dynamic data
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which is returned by the Configuration Registry. Data from
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various system API calls is placed into the structures shown
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here.
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Author:
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Russ Blake 12/23/93
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Revision History:
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--*/
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#ifndef _P5DATA_H_
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#define _P5DATA_H_
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#pragma pack(4)
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//----------------------------------------------------------------------------
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//
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// This structure defines the definition header for this performance object
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// This data is initialized in p5data.c and is more or less constant after
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// that. Organizationally, it is followed by an instance definition
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// structure and a counter data structure for each processor on the system.
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//
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typedef struct _P5_DATA_DEFINITION
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{
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PERF_OBJECT_TYPE P5PerfObject;
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PERF_COUNTER_DEFINITION Data_read;
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PERF_COUNTER_DEFINITION Data_write;
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PERF_COUNTER_DEFINITION Data_tlb_miss;
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PERF_COUNTER_DEFINITION Data_read_miss;
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PERF_COUNTER_DEFINITION Data_write_miss;
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PERF_COUNTER_DEFINITION Write_hit_to_me_line;
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PERF_COUNTER_DEFINITION Data_cache_line_wb;
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PERF_COUNTER_DEFINITION Data_cache_snoops;
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PERF_COUNTER_DEFINITION Data_cache_snoop_hits;
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PERF_COUNTER_DEFINITION Memory_accesses_in_pipes;
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PERF_COUNTER_DEFINITION Bank_conflicts;
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PERF_COUNTER_DEFINITION Misaligned_data_ref;
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PERF_COUNTER_DEFINITION Code_read;
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PERF_COUNTER_DEFINITION Code_tlb_miss;
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PERF_COUNTER_DEFINITION Code_cache_miss;
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PERF_COUNTER_DEFINITION Segment_loads;
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PERF_COUNTER_DEFINITION Branches;
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PERF_COUNTER_DEFINITION Btb_hits;
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PERF_COUNTER_DEFINITION Taken_branch_or_btb_hits;
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PERF_COUNTER_DEFINITION Pipeline_flushes;
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PERF_COUNTER_DEFINITION Instructions_executed;
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PERF_COUNTER_DEFINITION Instructions_executed_in_vpipe;
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PERF_COUNTER_DEFINITION Bus_utilization;
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PERF_COUNTER_DEFINITION Pipe_stalled_on_writes;
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PERF_COUNTER_DEFINITION Pipe_stalled_on_read;
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PERF_COUNTER_DEFINITION Stalled_while_ewbe;
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PERF_COUNTER_DEFINITION Locked_bus_cycle;
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PERF_COUNTER_DEFINITION Io_rw_cycle;
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PERF_COUNTER_DEFINITION Non_cached_memory_ref;
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PERF_COUNTER_DEFINITION Pipe_stalled_on_addr_gen;
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PERF_COUNTER_DEFINITION Flops;
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PERF_COUNTER_DEFINITION DebugRegister0;
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PERF_COUNTER_DEFINITION DebugRegister1;
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PERF_COUNTER_DEFINITION DebugRegister2;
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PERF_COUNTER_DEFINITION DebugRegister3;
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PERF_COUNTER_DEFINITION Interrupts;
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PERF_COUNTER_DEFINITION Data_rw;
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PERF_COUNTER_DEFINITION Data_rw_miss;
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// Derived Counters
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PERF_COUNTER_DEFINITION PctDataReadMiss;
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PERF_COUNTER_DEFINITION PctDataReadBase;
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PERF_COUNTER_DEFINITION PctDataWriteMiss;
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PERF_COUNTER_DEFINITION PctDataWriteBase;
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PERF_COUNTER_DEFINITION PctDataRWMiss;
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PERF_COUNTER_DEFINITION PctDataRWBase;
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PERF_COUNTER_DEFINITION PctDataTLBMiss;
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PERF_COUNTER_DEFINITION PctDataTLBBase;
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PERF_COUNTER_DEFINITION PctDataSnoopHits;
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PERF_COUNTER_DEFINITION PctDataSnoopBase;
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PERF_COUNTER_DEFINITION PctCodeReadMiss;
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PERF_COUNTER_DEFINITION PctCodeReadBase;
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PERF_COUNTER_DEFINITION PctCodeTLBMiss;
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PERF_COUNTER_DEFINITION PctCodeTLBBase;
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PERF_COUNTER_DEFINITION PctBTBHits;
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PERF_COUNTER_DEFINITION PctBTBBase;
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PERF_COUNTER_DEFINITION PctVpipeInst;
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PERF_COUNTER_DEFINITION PctVpipeBase;
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PERF_COUNTER_DEFINITION PctBranches;
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PERF_COUNTER_DEFINITION PctBranchesBase;
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} P5_DATA_DEFINITION, *PP5_DATA_DEFINITION;
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extern P5_DATA_DEFINITION P5DataDefinition;
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// this structure defines the data block that follows each instance
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// definition structure for each processor
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typedef struct _P5_COUNTER_DATA { // driver index
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PERF_COUNTER_BLOCK CounterBlock;
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// direct counters
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LONGLONG llData_read; // 0x00
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LONGLONG llData_write; // 0x01
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LONGLONG llData_tlb_miss; // 0x02
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LONGLONG llData_read_miss; // 0x03
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LONGLONG llData_write_miss; // 0x04
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LONGLONG llWrite_hit_to_me_line; // 0x05
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LONGLONG llData_cache_line_wb; // 0x06
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LONGLONG llData_cache_snoops; // 0x07
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LONGLONG llData_cache_snoop_hits; // 0x08
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LONGLONG llMemory_accesses_in_pipes; // 0x09
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LONGLONG llBank_conflicts; // 0x0a
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LONGLONG llMisaligned_data_ref; // 0x0b
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LONGLONG llCode_read; // 0x0c
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LONGLONG llCode_tlb_miss; // 0x0d
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LONGLONG llCode_cache_miss; // 0x0e
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LONGLONG llSegment_loads; // 0x0f
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LONGLONG llBranches; // 0x12
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LONGLONG llBtb_hits; // 0x13
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LONGLONG llTaken_branch_or_btb_hits; // 0x14
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LONGLONG llPipeline_flushes; // 0x15
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LONGLONG llInstructions_executed; // 0x16
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LONGLONG llInstructions_executed_in_vpipe;//0x17
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LONGLONG llBus_utilization; // 0x18
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LONGLONG llPipe_stalled_on_writes; // 0x19
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LONGLONG llPipe_stalled_on_read; // 0x1a
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LONGLONG llStalled_while_ewbe; // 0x1b
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LONGLONG llLocked_bus_cycle; // 0x1c
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LONGLONG llIo_rw_cycle; // 0x1d
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LONGLONG llNon_cached_memory_ref; // 0x1e
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LONGLONG llPipe_stalled_on_addr_gen; // 0x1f
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LONGLONG llFlops; // 0x22
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LONGLONG llDebugRegister0; // 0x23
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LONGLONG llDebugRegister1; // 0x24
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LONGLONG llDebugRegister2; // 0x25
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LONGLONG llDebugRegister3; // 0x26
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LONGLONG llInterrupts; // 0x27
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LONGLONG llData_rw; // 0x28
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LONGLONG llData_rw_miss; // 0x29
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// Derived Counters // counter index used
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DWORD dwPctDataReadMiss; // 0x03
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DWORD dwPctDataReadBase; // 0x00
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DWORD dwPctDataWriteMiss; // 0x04
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DWORD dwPctDataWriteBase; // 0x01
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DWORD dwPctDataRWMiss; // Ox29
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DWORD dwPctDataRWBase; // 0x28
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DWORD dwPctDataTLBMiss; // 0x02
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DWORD dwPctDataTLBBase; // 0x28
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DWORD dwPctDataSnoopHits; // 0x08
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DWORD dwPctDataSnoopBase; // 0x07
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DWORD dwPctCodeReadMiss; // 0x0e
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DWORD dwPctCodeReadBase; // 0x0c
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DWORD dwPctCodeTLBMiss; // 0x0d
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DWORD dwPctCodeTLBBase; // 0x0c
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DWORD dwPctBTBHits; // 0x13
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DWORD dwPctBTBBase; // 0x12
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DWORD dwPctVpipeInst; // 0x17
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DWORD dwPctVpipeBase; // 0x16
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DWORD dwPctBranches; // 0x12
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DWORD dwPctBranchesBase; // 0x16
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} P5_COUNTER_DATA, *PP5_COUNTER_DATA;
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extern DWORD P5IndexToData[]; // table to find data field
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extern DWORD P5IndexMax; // number of direct counters
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extern BOOL dwDerivedp5Counters[]; // table to find counters used in derived ctrs.
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// table entry to map direct counters to derived counter fields
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typedef struct _DERIVED_P5_COUNTER_DEF {
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DWORD dwCR0Index; // if the EventId[0] == this field
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DWORD dwCR1Index; // and EventId[1] == this field then store
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DWORD dwCR0FieldOffset; // the Low DWORD of Counter[0] at this offset and
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DWORD dwCR1FieldOffset; // the low DWORD of Counter[1] at this offset
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} DERIVED_P5_COUNTER_DEF, *PDERIVED_P5_COUNTER_DEF;
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extern DERIVED_P5_COUNTER_DEF P5DerivedCounters[]; // table of derived counters
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extern DWORD dwP5DerivedCountersCount; // count of derived counter ref's
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#pragma pack ()
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#endif //_P5DATA_H_
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