587 lines
16 KiB
C
587 lines
16 KiB
C
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/*++
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Copyright (c) 1999 Microsoft Corporation
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Module Name:
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trans.h
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Abstract:
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Header file for math functions.
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Author:
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Revision History:
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29-sept-1999 ATM Shafiqul Khalid [askhalid] copied from rtl library.
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--*/
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#ifndef _INC_TRANS
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __assembler /* MIPS ONLY: Protect from assembler */
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//#include <cruntime.h>
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void
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SetMathError (
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int Code
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);
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#define OP_UNSPEC 0
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#define OP_ADD 1
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#define OP_SUB 2
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#define OP_MUL 3
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#define OP_DIV 4
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#define OP_SQRT 5
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#define OP_REM 6
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#define OP_COMP 7
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#define OP_CVT 8
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#define OP_RND 9
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#define OP_TRUNC 10
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#define OP_FLOOR 11
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#define OP_CEIL 12
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#define OP_ACOS 13
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#define OP_ASIN 14
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#define OP_ATAN 15
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#define OP_ATAN2 16
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#define OP_CABS 17
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#define OP_COS 18
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#define OP_COSH 19
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#define OP_EXP 20
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#define OP_ABS 21 /* same as OP_FABS */
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#define OP_FABS 21 /* same as OP_ABS */
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#define OP_FMOD 22
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#define OP_FREXP 23
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#define OP_HYPOT 24
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#define OP_LDEXP 25
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#define OP_LOG 26
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#define OP_LOG10 27
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#define OP_MODF 28
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#define OP_POW 29
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#define OP_SIN 30
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#define OP_SINH 31
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#define OP_TAN 32
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#define OP_TANH 33
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#define OP_Y0 34
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#define OP_Y1 35
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#define OP_YN 36
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#define OP_LOGB 37
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#define OP_NEXTAFTER 38
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#define OP_NEG 39
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/* Define __cdecl for non-Microsoft compilers */
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#if ( !defined(_MSC_VER) && !defined(__cdecl) )
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#define __cdecl
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#endif
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#include <fpieee.h>
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#define D_BIASM1 0x3fe /* off by one to compensate for the implied bit */
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#ifdef B_END
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/* big endian */
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#define D_EXP(x) ((unsigned short *)&(x))
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#define D_HI(x) ((unsigned long *)&(x))
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#define D_LO(x) ((unsigned long *)&(x)+1)
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#else
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#define D_EXP(x) ((unsigned short *)&(x)+3)
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#define D_HI(x) ((unsigned long *)&(x)+1)
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#define D_LO(x) ((unsigned long *)&(x))
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#endif
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/* return the int representation of the exponent
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* if x = .f * 2^n, 0.5<=f<1, return n (unbiased)
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* e.g. INTEXP(3.0) == 2
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*/
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#define INTEXP(x) ((signed short)((*D_EXP(x) & 0x7ff0) >> 4) - D_BIASM1)
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/* check for infinity, NAN */
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#define D_ISINF(x) ((*D_HI(x) & 0x7fffffff) == 0x7ff00000 && *D_LO(x) == 0)
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#define IS_D_SPECIAL(x) ((*D_EXP(x) & 0x7ff0) == 0x7ff0)
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#define IS_D_NAN(x) (IS_D_SPECIAL(x) && !D_ISINF(x))
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#ifdef _M_MRX000
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#define IS_D_SNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff8)
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#define IS_D_QNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff0 && \
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(*D_HI(x) << 13 || *D_LO(x)))
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#else
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#define IS_D_QNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff8)
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#define IS_D_SNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff0 && \
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(*D_HI(x) << 13 || *D_LO(x)))
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#endif
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#define IS_D_DENORM(x) ((*D_EXP(x) & 0x7ff0) == 0 && \
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(*D_HI(x) << 12 || *D_LO(x)))
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#define IS_D_INF(x) (*D_HI(x) == 0x7ff00000 && *D_LO(x) == 0)
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#define IS_D_MINF(x) (*D_HI(x) == 0xfff00000 && *D_LO(x) == 0)
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#ifdef _M_MRX000
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#define D_IND_HI 0x7ff7ffff
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#define D_IND_LO 0xffffffff
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#else
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#define D_IND_HI 0xfff80000
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#define D_IND_LO 0x0
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#endif
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typedef union {
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long lng[2];
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double dbl;
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} _dbl;
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#ifndef DEFINE_EXTERN_HERE
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extern _dbl _d_inf;
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extern _dbl _d_ind;
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extern _dbl _d_max;
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extern _dbl _d_min;
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extern _dbl _d_mzero;
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#else
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_dbl _d_inf;
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_dbl _d_ind;
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_dbl _d_max;
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_dbl _d_min;
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_dbl _d_mzero;
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#endif
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#define D_INF (_d_inf.dbl)
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#define D_IND (_d_ind.dbl)
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#define D_MAX (_d_max.dbl)
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#define D_MIN (_d_min.dbl)
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#define D_MZERO (_d_mzero.dbl) /* minus zero */
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/* min and max exponents for normalized numbers in the
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* form: 0.xxxxx... * 2^exp (NOT 1.xxxx * 2^exp !)
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*/
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#define MAXEXP 1024
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#define MINEXP -1021
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#endif /* #ifndef __assembler */
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#if defined(_M_IX86)
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/* Control word for computation of transcendentals */
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#define ICW 0x133f
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#define IMCW 0xffff
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#define IMCW_EM 0x003f /* interrupt Exception Masks */
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#define IEM_INVALID 0x0001 /* invalid */
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#define IEM_DENORMAL 0x0002 /* denormal */
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#define IEM_ZERODIVIDE 0x0004 /* zero divide */
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#define IEM_OVERFLOW 0x0008 /* overflow */
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#define IEM_UNDERFLOW 0x0010 /* underflow */
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#define IEM_INEXACT 0x0020 /* inexact (precision) */
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#define IMCW_RC 0x0c00 /* Rounding Control */
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#define IRC_CHOP 0x0c00 /* chop */
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#define IRC_UP 0x0800 /* up */
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#define IRC_DOWN 0x0400 /* down */
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#define IRC_NEAR 0x0000 /* near */
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#define ISW_INVALID 0x0001 /* invalid */
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#define ISW_DENORMAL 0x0002 /* denormal */
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#define ISW_ZERODIVIDE 0x0004 /* zero divide */
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#define ISW_OVERFLOW 0x0008 /* overflow */
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#define ISW_UNDERFLOW 0x0010 /* underflow */
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#define ISW_INEXACT 0x0020 /* inexact (precision) */
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#define IMCW_PC 0x0300 /* Precision Control */
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#define IPC_24 0x0000 /* 24 bits */
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#define IPC_53 0x0200 /* 53 bits */
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#define IPC_64 0x0300 /* 64 bits */
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#define IMCW_IC 0x1000 /* Infinity Control */
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#define IIC_AFFINE 0x1000 /* affine */
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#define IIC_PROJECTIVE 0x0000 /* projective */
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#elif defined(_M_MRX000)
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#define ICW 0x00000f80 /* Internal CW for transcendentals */
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#define IMCW 0xffffff83 /* Internal CW Mask */
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#define IMCW_EM 0x00000f80 /* interrupt Exception Masks */
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#define IEM_INVALID 0x00000800 /* invalid */
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#define IEM_ZERODIVIDE 0x00000400 /* zero divide */
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#define IEM_OVERFLOW 0x00000200 /* overflow */
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#define IEM_UNDERFLOW 0x00000100 /* underflow */
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#define IEM_INEXACT 0x00000080 /* inexact (precision) */
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#define IMCW_RC 0x00000003 /* Rounding Control */
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#define IRC_CHOP 0x00000001 /* chop */
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#define IRC_UP 0x00000002 /* up */
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#define IRC_DOWN 0x00000003 /* down */
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#define IRC_NEAR 0x00000000 /* near */
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#define ISW_INVALID (1<<6) /* invalid */
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#define ISW_ZERODIVIDE (1<<5) /* zero divide */
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#define ISW_OVERFLOW (1<<4) /* overflow */
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#define ISW_UNDERFLOW (1<<3) /* underflow */
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#define ISW_INEXACT (1<<2) /* inexact (precision) */
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#elif defined(_M_ALPHA)
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//
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// ICW is the Internal Control Word for transcendentals: all five exceptions
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// are masked and round to nearest mode is set. IMCW is the mask: all bits
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// are set, except for the ISW bits.
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//
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#define ICW (IEM_INEXACT | IEM_UNDERFLOW | IEM_OVERFLOW | IEM_ZERODIVIDE | IEM_INVALID | IRC_NEAR)
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#define ISW (ISW_INEXACT | ISW_UNDERFLOW | ISW_OVERFLOW | ISW_ZERODIVIDE | ISW_INVALID)
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#define IMCW (0xffffffff ^ ISW)
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//
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// The defines for the internal control word match the format of the Alpha
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// AXP software FPCR except for the rounding mode which is obtained from the
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// Alpha AXP hardware FPCR and shifted right 32 bits.
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//
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//
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// Internal Exception Mask bits.
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// Each bit _disables_ an exception (they are not _enable_ bits).
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//
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#define IMCW_EM 0x0000003e /* interrupt Exception Masks */
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#define IEM_INEXACT 0x00000020 /* inexact (precision) */
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#define IEM_UNDERFLOW 0x00000010 /* underflow */
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#define IEM_OVERFLOW 0x00000008 /* overflow */
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#define IEM_ZERODIVIDE 0x00000004 /* zero divide */
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#define IEM_INVALID 0x00000002 /* invalid */
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//
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// Internal Rounding Control values.
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//
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#define IMCW_RC (0x3 << 26) /* Rounding Control */
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#define IRC_CHOP (0x0 << 26) /* chop */
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#define IRC_DOWN (0x1 << 26) /* down */
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#define IRC_NEAR (0x2 << 26) /* near */
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#define IRC_UP (0x3 << 26) /* up */
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//
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// Internal Status Word bits.
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//
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#define ISW_INEXACT 0x00200000 /* inexact (precision) */
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#define ISW_UNDERFLOW 0x00100000 /* underflow */
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#define ISW_OVERFLOW 0x00080000 /* overflow */
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#define ISW_ZERODIVIDE 0x00040000 /* zero divide */
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#define ISW_INVALID 0x00020000 /* invalid */
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#elif defined(_M_PPC)
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#define IMCW_EM 0x000000f8 /* Exception Enable Mask */
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#define IEM_INVALID 0x00000080 /* invalid */
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#define IEM_OVERFLOW 0x00000040 /* overflow */
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#define IEM_UNDERFLOW 0x00000020 /* underflow */
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#define IEM_ZERODIVIDE 0x00000010 /* zero divide */
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#define IEM_INEXACT 0x00000008 /* inexact (precision) */
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#define IMCW_RC 0x00000003 /* Rounding Control Mask */
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#define IRC_NEAR 0x00000000 /* near */
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#define IRC_CHOP 0x00000001 /* chop */
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#define IRC_UP 0x00000002 /* up */
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#define IRC_DOWN 0x00000003 /* down */
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#define IMCW_SW 0x3E000000 /* Status Mask */
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#define ISW_INVALID 0x20000000 /* invalid summary */
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#define ISW_OVERFLOW 0x10000000 /* overflow */
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#define ISW_UNDERFLOW 0x08000000 /* underflow */
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#define ISW_ZERODIVIDE 0x04000000 /* zero divide */
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#define ISW_INEXACT 0x02000000 /* inexact (precision) */
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#define IMCW_VX 0x01F80700 /* Invalid Cause Mask */
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#define IVX_SNAN 0x01000000 /* SNaN */
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#define IVX_ISI 0x00800000 /* infinity - infinity */
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#define IVX_IDI 0x00400000 /* infinity / infinity */
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#define IVX_ZDZ 0x00200000 /* zero / zero */
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#define IVX_IMZ 0x00100000 /* infinity * zero */
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#define IVX_VC 0x00080000 /* inv flpt compare */
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#define IVX_SOFT 0x00000400 /* software request */
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#define IVX_SQRT 0x00000200 /* sqrt of negative */
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#define IVX_CVI 0x00000100 /* inv integer convert */
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/* Internal CW for transcendentals */
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#define ICW (IMCW_EM)
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/* Internal CW Mask (non-status bits) */
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#define IMCW (0xffffffff & (~(IMCW_SW|IMCW_VX)))
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#elif defined(_M_M68K)
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#include "mac\m68k\trans.a"
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/* LATER -- we don't handle exception until Mac OS has better support on it */
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#define _except1(flags, op, arg1, res, cw) _errcode(flags), _rstorfp(cw), \
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_set_statfp(cw),(res)
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#define _except2(flags, op, arg1, arg2, res, cw) _errcode(flags), _rstorfp(cw), \
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_set_statfp(cw),(res)
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#define _handle_qnan1(opcode, x, savedcw) _set_errno(_DOMAIN), _rstorfp(savedcw), (x);
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#define _handle_qnan2(opcode, x, y, savedcw) _set_errno(_DOMAIN), _rstorfp(savedcw), (x+y);
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|
|
|
||
|
|
|
||
|
|
#elif defined(_M_MPPC)
|
||
|
|
|
||
|
|
/* Mac control information - included as part of trans.h
|
||
|
|
It is broken out to allow use with ASM68 files*/
|
||
|
|
|
||
|
|
/* Control word for computation of transcendentals */
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
#define ICW (IPC_64 + IRC_NEAR + IMCW_EM)
|
||
|
|
|
||
|
|
#define IMCW IMCW_RC + IMCW_PC
|
||
|
|
|
||
|
|
|
||
|
|
#define IMCW_EM 0x000000f8 /* interrupt Exception Masks */
|
||
|
|
#define IEM_INVALID 0x00000080 /* invalid */
|
||
|
|
#define IEM_ZERODIVIDE 0x00000010 /* zero divide */
|
||
|
|
#define IEM_OVERFLOW 0x00000040 /* overflow */
|
||
|
|
#define IEM_UNDERFLOW 0x00000020 /* underflow */
|
||
|
|
#define IEM_INEXACT 0x00000008 /* inexact (precision) */
|
||
|
|
|
||
|
|
|
||
|
|
#define IMCW_RC 0x00000003 /* Rounding Control */
|
||
|
|
#define IRC_CHOP 0x00000001 /* chop */
|
||
|
|
#define IRC_UP 0x00000002 /* up */
|
||
|
|
#define IRC_DOWN 0x00000003 /* down */
|
||
|
|
#define IRC_NEAR 0x00000000 /* near */
|
||
|
|
|
||
|
|
#define IMSW 0xffffff00 /* status bits mask */
|
||
|
|
#define ISW_INVALID 0x20000000 /* invalid */
|
||
|
|
#define ISW_ZERODIVIDE 0x04000000 /* zero divide */
|
||
|
|
#define ISW_OVERFLOW 0x10000000 /* overflow */
|
||
|
|
#define ISW_UNDERFLOW 0x08000000 /* underflow */
|
||
|
|
#define ISW_INEXACT 0x02000000 /* inexact (precision) */
|
||
|
|
|
||
|
|
#define IMCW_PC 0x0000 /* Precision Control */
|
||
|
|
#define IPC_24 0x0000 /* 24 bits */
|
||
|
|
#define IPC_53 0x0000 /* 53 bits */
|
||
|
|
#define IPC_64 0x0000 /* 64 bits */
|
||
|
|
|
||
|
|
|
||
|
|
/* LATER -- we don't handle exception until Mac OS has better support on it */
|
||
|
|
|
||
|
|
#define _except1(flags, op, arg1, res, cw) _errcode(flags), \
|
||
|
|
_set_statfp(cw),(res)
|
||
|
|
|
||
|
|
#define _except2(flags, op, arg1, arg2, res, cw) _errcode(flags), \
|
||
|
|
_set_statfp(cw),(res)
|
||
|
|
|
||
|
|
#define _handle_qnan1(opcode, x, savedcw) _set_errno(_DOMAIN), _rstorfp(savedcw), (x);
|
||
|
|
#define _handle_qnan2(opcode, x, y, savedcw) _set_errno(_DOMAIN), _rstorfp(savedcw), (x+y);
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifndef __assembler /* MIPS ONLY: Protect from assembler */
|
||
|
|
|
||
|
|
#define RETURN(fpcw,result) return _rstorfp(fpcw),(result)
|
||
|
|
|
||
|
|
#define RETURN_INEXACT1(op,arg1,res,cw) \
|
||
|
|
if (cw & IEM_INEXACT) { \
|
||
|
|
_rstorfp(cw); \
|
||
|
|
return res; \
|
||
|
|
} \
|
||
|
|
else { \
|
||
|
|
return _except1(FP_P, op, arg1, res, cw); \
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#define RETURN_INEXACT2(op,arg1,arg2,res,cw) \
|
||
|
|
if (cw & IEM_INEXACT) { \
|
||
|
|
_rstorfp(cw); \
|
||
|
|
return res; \
|
||
|
|
} \
|
||
|
|
else { \
|
||
|
|
return _except2(FP_P, op, arg1, arg2, res, cw); \
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
#ifdef _M_ALPHA
|
||
|
|
|
||
|
|
//
|
||
|
|
// Since fp32 is not compiled in IEEE exception mode perform Alpha NaN
|
||
|
|
// propagation in software to avoid hardware/kernel trap involvement.
|
||
|
|
//
|
||
|
|
|
||
|
|
extern double _nan2qnan(double);
|
||
|
|
|
||
|
|
#define _d_snan2(x,y) _nan2qnan(y)
|
||
|
|
#define _s2qnan(x) _nan2qnan(x)
|
||
|
|
|
||
|
|
#else
|
||
|
|
//handle NaN propagation
|
||
|
|
#define _d_snan2(x,y) ((x)+(y))
|
||
|
|
#define _s2qnan(x) ((x)+1.0)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#define _maskfp() _ctrlfp(ICW, IMCW)
|
||
|
|
#ifdef _M_ALPHA
|
||
|
|
#define _rstorfp(cw) 0
|
||
|
|
#else
|
||
|
|
#define _rstorfp(cw) _ctrlfp(cw, IMCW)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
|
||
|
|
#define ABS(x) ((x)<0 ? -(x) : (x) )
|
||
|
|
|
||
|
|
|
||
|
|
int _d_inttype(double);
|
||
|
|
|
||
|
|
#endif /* #ifndef __assembler */
|
||
|
|
|
||
|
|
#define _D_NOINT 0
|
||
|
|
#define _D_ODD 1
|
||
|
|
#define _D_EVEN 2
|
||
|
|
|
||
|
|
|
||
|
|
// IEEE exceptions
|
||
|
|
#define FP_O 0x01
|
||
|
|
#define FP_U 0x02
|
||
|
|
#define FP_Z 0x04
|
||
|
|
#define FP_I 0x08
|
||
|
|
#define FP_P 0x10
|
||
|
|
|
||
|
|
// An extra flag for matherr support
|
||
|
|
// Set together with FP_I from trig functions when the argument is too large
|
||
|
|
#define FP_TLOSS 0x20
|
||
|
|
|
||
|
|
|
||
|
|
#ifndef __assembler /* MIPS ONLY: Protect from assembler */
|
||
|
|
#ifdef B_END
|
||
|
|
#define SET_DBL(msw, lsw) msw, lsw
|
||
|
|
#else
|
||
|
|
#define SET_DBL(msw, lsw) lsw, msw
|
||
|
|
#endif
|
||
|
|
#endif /* #ifndef __assembler */
|
||
|
|
|
||
|
|
|
||
|
|
// special types
|
||
|
|
#define T_PINF 1
|
||
|
|
#define T_NINF 2
|
||
|
|
#define T_QNAN 3
|
||
|
|
#define T_SNAN 4
|
||
|
|
|
||
|
|
|
||
|
|
// exponent adjustment for IEEE overflow/underflow exceptions
|
||
|
|
// used before passing the result to the trap handler
|
||
|
|
|
||
|
|
#define IEEE_ADJUST 1536
|
||
|
|
|
||
|
|
// QNAN values
|
||
|
|
|
||
|
|
#define INT_NAN (~0)
|
||
|
|
|
||
|
|
#define QNAN_SQRT D_IND
|
||
|
|
#define QNAN_LOG D_IND
|
||
|
|
#define QNAN_LOG10 D_IND
|
||
|
|
#define QNAN_POW D_IND
|
||
|
|
#define QNAN_SINH D_IND
|
||
|
|
#define QNAN_COSH D_IND
|
||
|
|
#define QNAN_TANH D_IND
|
||
|
|
#define QNAN_SIN1 D_IND
|
||
|
|
#define QNAN_SIN2 D_IND
|
||
|
|
#define QNAN_COS1 D_IND
|
||
|
|
#define QNAN_COS2 D_IND
|
||
|
|
#define QNAN_TAN1 D_IND
|
||
|
|
#define QNAN_TAN2 D_IND
|
||
|
|
#define QNAN_ACOS D_IND
|
||
|
|
#define QNAN_ASIN D_IND
|
||
|
|
#define QNAN_ATAN2 D_IND
|
||
|
|
#define QNAN_CEIL D_IND
|
||
|
|
#define QNAN_FLOOR D_IND
|
||
|
|
#define QNAN_MODF D_IND
|
||
|
|
#define QNAN_LDEXP D_IND
|
||
|
|
#define QNAN_FMOD D_IND
|
||
|
|
#define QNAN_FREXP D_IND
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Function prototypes
|
||
|
|
*/
|
||
|
|
|
||
|
|
#ifndef __assembler /* MIPS ONLY: Protect from assembler */
|
||
|
|
|
||
|
|
double _set_exp(double x, int exp);
|
||
|
|
double _set_bexp(double x, int exp);
|
||
|
|
double _add_exp(double x, int exp);
|
||
|
|
double _frnd(double);
|
||
|
|
double _fsqrt(double);
|
||
|
|
#if !defined(_M_M68K) && !defined(_M_MPPC)
|
||
|
|
double _except1(int flags, int opcode, double arg, double res, unsigned int cw);
|
||
|
|
double _except2(int flags, int opcode, double arg1, double arg2, double res, unsigned int cw);
|
||
|
|
#endif
|
||
|
|
int _sptype(double);
|
||
|
|
int _get_exp(double);
|
||
|
|
double _decomp(double, int *);
|
||
|
|
int _powhlp(double x, double y, double * result);
|
||
|
|
extern unsigned int _fpstatus;
|
||
|
|
double _frnd(double);
|
||
|
|
double _exphlp(double, int *);
|
||
|
|
#if !defined(_M_M68K) && !defined(_M_MPPC)
|
||
|
|
double _handle_qnan1(unsigned int op, double arg, unsigned int cw);
|
||
|
|
double _handle_qnan2(unsigned int op,double arg1,double arg2,unsigned int cw);
|
||
|
|
#endif
|
||
|
|
unsigned int _clhwfp(void);
|
||
|
|
unsigned int _setfpcw(unsigned int);
|
||
|
|
int _errcode(unsigned int flags);
|
||
|
|
void _set_errno(int matherrtype);
|
||
|
|
int _handle_exc(unsigned int flags, double * presult, unsigned int cw);
|
||
|
|
unsigned int _clrfp(void);
|
||
|
|
unsigned int _ctrlfp(unsigned int,unsigned int);
|
||
|
|
unsigned int _statfp(void);
|
||
|
|
void _set_statfp(unsigned int);
|
||
|
|
|
||
|
|
#endif /* #ifndef __assembler */
|
||
|
|
|
||
|
|
#ifdef __cplusplus
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#define _INC_TRANS
|
||
|
|
#endif /* _INC_TRANS */
|