189 lines
6.8 KiB
C
189 lines
6.8 KiB
C
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/****************************************************************************
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** COPYRIGHT (C) 1994-1997 INTEL CORPORATION **
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** DEVELOPED FOR MICROSOFT BY INTEL CORP., HILLSBORO, OREGON **
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** HTTP://WWW.INTEL.COM/ **
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** THIS FILE IS PART OF THE INTEL ETHEREXPRESS PRO/100B(TM) AND **
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** ETHEREXPRESS PRO/100+(TM) NDIS 5.0 MINIPORT SAMPLE DRIVER **
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****************************************************************************/
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/****************************************************************************
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Module Name:
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e100_equ.h (equates.h)
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This driver runs on the following hardware:
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- 82558 based PCI 10/100Mb ethernet adapters
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(aka Intel EtherExpress(TM) PRO Adapters)
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Environment:
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Kernel Mode - Or whatever is the equivalent on WinNT
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Revision History
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- JCB 8/14/97 Example Driver Created
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- Dchen 11-01-99 Modified for the new sample driver
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*****************************************************************************/
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#ifndef _E100_EQU_H
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#define _E100_EQU_H
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//-------------------------------------------------------------------------
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// OEM Message Tags
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//-------------------------------------------------------------------------
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#define stringTag 0xFEFA // Length Byte After String
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#define lStringTag 0xFEFB // Length Byte Before String
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#define zStringTag 0xFEFC // Zero-Terminated String Tag
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#define nStringTag 0xFEFD // No Length Byte Or 0-Term
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//-------------------------------------------------------------------------
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// Adapter Types Supported
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//-------------------------------------------------------------------------
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#define FLASH32_EISA (0 * 4)
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#define FLASH32_PCI (1 * 4)
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#define D29C_EISA (2 * 4)
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#define D29C_PCI (3 * 4)
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#define D100_PCI (4 * 4)
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//-------------------------------------------------------------------------
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// Phy related constants
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//-------------------------------------------------------------------------
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#define PHY_503 0
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#define PHY_100_A 0x000003E0
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#define PHY_100_C 0x035002A8
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#define PHY_TX_ID 0x015002A8
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#define PHY_NSC_TX 0x5c002000
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#define PHY_OTHER 0xFFFF
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#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF
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#define PARALLEL_DETECT 0
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#define N_WAY 1
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#define RENEGOTIATE_TIME 35 // (3.5 Seconds)
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#define CONNECTOR_AUTO 0
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#define CONNECTOR_TPE 1
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#define CONNECTOR_MII 2
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//-------------------------------------------------------------------------
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// Ethernet Frame Sizes
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//-------------------------------------------------------------------------
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#define ETHERNET_ADDRESS_LENGTH 6
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#define ETHERNET_HEADER_SIZE 14
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#define MINIMUM_ETHERNET_PACKET_SIZE 60
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#define MAXIMUM_ETHERNET_PACKET_SIZE 1514
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#define MAX_MULTICAST_ADDRESSES 32
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#define TCB_BUFFER_SIZE 0XE0 // 224
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#define COALESCE_BUFFER_SIZE 2048
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#define ETH_MAX_COPY_LENGTH 0x80 // 128
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// Make receive area 1536 for 16 bit alignment.
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//#define RCB_BUFFER_SIZE MAXIMUM_ETHERNET_PACKET_SIZE
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#define RCB_BUFFER_SIZE 1520 // 0x5F0
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//- Area reserved for all Non Transmit command blocks
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#define MAX_NON_TX_CB_AREA 512
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//-------------------------------------------------------------------------
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// Ndis/Adapter driver constants
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//-------------------------------------------------------------------------
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#define MAX_PHYS_DESC 16
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#define MAX_RECEIVE_DESCRIPTORS 1024 // 0x400
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#define NUM_RMD 10
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//--------------------------------------------------------------------------
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// System wide Equates
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//--------------------------------------------------------------------------
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#define MAX_NUMBER_OF_EISA_SLOTS 15
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#define MAX_NUMBER_OF_PCI_SLOTS 15
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//--------------------------------------------------------------------------
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// Equates Added for NDIS 4
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//--------------------------------------------------------------------------
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#define NUM_BYTES_PROTOCOL_RESERVED_SECTION 16
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#define MAX_NUM_ALLOCATED_RFDS 64
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#define MIN_NUM_RFD 4
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#define MAX_ARRAY_SEND_PACKETS 8
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// limit our receive routine to indicating this many at a time
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#define MAX_ARRAY_RECEIVE_PACKETS 16
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#define MAC_RESERVED_SWRFDPTR 0
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#define MAX_PACKETS_TO_ADD 32
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//-------------------------------------------------------------------------
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//- Miscellaneous Equates
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//-------------------------------------------------------------------------
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#define CR 0x0D // Carriage Return
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#define LF 0x0A // Line Feed
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#ifndef FALSE
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#define FALSE 0
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#define TRUE 1
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#endif
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#define DRIVER_NULL ((ULONG)0xffffffff)
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#define DRIVER_ZERO 0
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//-------------------------------------------------------------------------
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// Bit Mask definitions
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//-------------------------------------------------------------------------
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#define BIT_0 0x0001
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#define BIT_1 0x0002
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#define BIT_2 0x0004
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#define BIT_3 0x0008
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#define BIT_4 0x0010
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#define BIT_5 0x0020
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#define BIT_6 0x0040
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#define BIT_7 0x0080
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#define BIT_8 0x0100
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#define BIT_9 0x0200
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#define BIT_10 0x0400
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#define BIT_11 0x0800
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#define BIT_12 0x1000
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#define BIT_13 0x2000
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#define BIT_14 0x4000
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#define BIT_15 0x8000
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#define BIT_24 0x01000000
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#define BIT_28 0x10000000
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#define BIT_0_2 0x0007
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#define BIT_0_3 0x000F
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#define BIT_0_4 0x001F
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#define BIT_0_5 0x003F
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#define BIT_0_6 0x007F
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#define BIT_0_7 0x00FF
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#define BIT_0_8 0x01FF
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#define BIT_0_13 0x3FFF
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#define BIT_0_15 0xFFFF
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#define BIT_1_2 0x0006
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#define BIT_1_3 0x000E
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#define BIT_2_5 0x003C
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#define BIT_3_4 0x0018
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#define BIT_4_5 0x0030
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#define BIT_4_6 0x0070
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#define BIT_4_7 0x00F0
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#define BIT_5_7 0x00E0
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#define BIT_5_9 0x03E0
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#define BIT_5_12 0x1FE0
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#define BIT_5_15 0xFFE0
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#define BIT_6_7 0x00c0
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#define BIT_7_11 0x0F80
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#define BIT_8_10 0x0700
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#define BIT_9_13 0x3E00
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#define BIT_12_15 0xF000
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#define BIT_16_20 0x001F0000
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#define BIT_21_25 0x03E00000
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#define BIT_26_27 0x0C000000
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// in order to make our custom oids hopefully somewhat unique
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// we will use 0xFF (indicating implementation specific OID)
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// A0 (first byte of non zero intel unique identifier)
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// C9 (second byte of non zero intel unique identifier)
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// XX (the custom OID number - providing 255 possible custom oids)
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#define OID_CUSTOM_DRIVER_SET 0xFFA0C901
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#define OID_CUSTOM_DRIVER_QUERY 0xFFA0C902
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#define OID_CUSTOM_ARRAY 0xFFA0C903
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#define OID_CUSTOM_STRING 0xFFA0C904
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#define CMD_BUS_MASTER BIT_2
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#endif // _E100_EQU_H
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