219 lines
6.6 KiB
C
219 lines
6.6 KiB
C
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/*++
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Copyright (c) 1993-1999 Digital Equipment Corporation
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Module Name:
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alpharef.h
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Abstract:
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This module defines the reference hardware definitions for Alpha AXP
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platforms. Any platform that adheres to these interfaces will be
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capable of running all of the common drivers.
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Author:
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Joe Notarangelo 15-Feb-1993
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Revision History:
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John DeRosa [DEC] 2-July-1993
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Added firmware vendor call definitions that are generic to all Alpha
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platforms.
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--*/
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#ifndef _ALPHAREF_
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#define _ALPHAREF_
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//
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// Define interesting device addresses.
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//
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#define KEYBOARD_PHYSICAL_BASE 0x60
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//
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// Define DMA device channels.
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//
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#define SCSI_CHANNEL 0x0 // SCSI DMA channel number
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#define FLOPPY_CHANNEL 0x2 // Floppy DMA channel
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#define SOUND_CHANNEL_A 0x2 // Sound DMA channel A
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#define SOUND_CHANNEL_B 0x3 // Sound DMA channel B
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//
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// Define the interrupt request levels.
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//
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#define FLOPPY_LEVEL 6 // The floppy
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#define CLOCK_LEVEL 5 // Interval clock level
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#define PROFILE_LEVEL 3 // Profiling level
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#define PCI_DEVICE_LEVEL 3 // PCI bus interrupt level
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#define EISA_DEVICE_LEVEL 3 // EISA bus interrupt level
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#define ISA_DEVICE_LEVEL 3 // ISA bus interrupt level
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#define DEVICE_LEVEL 3 // Generic device interrupt level
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#define DEVICE_LOW_LEVEL 3 // I/O device interrupt level low
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#define DEVICE_HIGH_LEVEL 4 // I/O device interrupt level high
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#define IPI_LEVEL 6 // Inter-processor interrupt level
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#define POWER_LEVEL 7 // Powerfail level
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#define EISA_NMI_LEVEL POWER_LEVEL // Eisa NMI failures
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#define CLOCK2_LEVEL CLOCK_LEVEL //
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//
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// Define EISA device interrupt vectors.
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//
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#define EISA_VECTORS 48
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//
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// Define the EISA interrupt request levels. Levels 1,8 and 13 are not
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// defined. Level 0 is also the timer. Level 2 is not assignable because
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// it receives the vector from the second PIC bank.
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//
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#define EISA_IRQL0_VECTOR (0 + EISA_VECTORS) // Eisa interrupt request level 0
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#define EISA_IRQL3_VECTOR (3 + EISA_VECTORS)
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#define EISA_IRQL4_VECTOR (4 + EISA_VECTORS)
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#define EISA_IRQL5_VECTOR (5 + EISA_VECTORS)
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#define EISA_IRQL6_VECTOR (6 + EISA_VECTORS)
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#define EISA_IRQL7_VECTOR (7 + EISA_VECTORS)
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#define EISA_IRQL9_VECTOR (9 + EISA_VECTORS)
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#define EISA_IRQL10_VECTOR (10 + EISA_VECTOR)
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#define EISA_IRQL11_VECTOR (11 + EISA_VECTORS)
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#define EISA_IRQL12_VECTOR (12 + EISA_VECTORS)
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#define EISA_IRQL14_VECTOR (14 + EISA_VECTORS)
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#define EISA_IRQL15_VECTOR (15 + EISA_VECTORS)
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#define MAXIMUM_EISA_VECTOR (16 + EISA_VECTORS) // maximum EISA vector
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//
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// The parallel port is at IRQL1 by default.
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//
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#define PARALLEL_VECTOR (1 + EISA_VECTORS) // Parallel device interrupt vector
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//
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// Define ISA device interrupt vectors.
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//
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#define ISA_VECTORS 48
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#define KEYBOARD_VECTOR 1
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#define MOUSE_VECTOR 12
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//
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// Define the EISA interrupt request levels. Levels 1,8 and 13 are not
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// defined. Level 0 is also the timer. Level 2 is not assignable because
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// it receives the vector from the second PIC bank.
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//
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#define ISA_IRQL0_VECTOR (0 + ISA_VECTORS)
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#define ISA_IRQL3_VECTOR (3 + ISA_VECTORS)
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#define ISA_IRQL4_VECTOR (4 + ISA_VECTORS)
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#define ISA_IRQL5_VECTOR (5 + ISA_VECTORS)
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#define ISA_IRQL6_VECTOR (6 + ISA_VECTORS)
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#define ISA_IRQL7_VECTOR (7 + ISA_VECTORS)
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#define ISA_IRQL9_VECTOR (9 + ISA_VECTORS)
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#define ISA_IRQL10_VECTOR (10 + ISA_VECTORS)
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#define ISA_IRQL11_VECTOR (11 + ISA_VECTORS)
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#define ISA_IRQL12_VECTOR (12 + ISA_VECTORS)
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#define ISA_IRQL14_VECTOR (14 + ISA_VECTORS)
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#define ISA_IRQL15_VECTOR (15 + ISA_VECTORS)
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#define MAXIMUM_ISA_VECTOR (16 + ISA_VECTORS) // maximum ISA vector
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//
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// Define PCI device interrupt vectors.
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//
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#define PCI_VECTORS 100
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#define MAXIMUM_PCI_VECTOR (64 + PCI_VECTORS) // maximum PCI vector
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//
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// Define I/O device interrupt level.
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//
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//
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// Define device interrupt vectors.
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//
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#define DEVICE_VECTORS 0 // starting builtin device vector
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#define PASSIVE_VECTOR (0) // Passive release vector
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#define APC_VECTOR (1) // APC Interrupt vector
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#define DISPATCH_VECTOR (2) // Dispatch Interrupt vector
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#define SCI_VECTOR (3 + DEVICE_VECTORS) // SCI Interrupt vector
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#define SERIAL_VECTOR (4 + DEVICE_VECTORS) // Serial device 1 interrupt vector
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#define CLOCK_VECTOR (5 + DEVICE_VECTORS) // Clock interrupt vector
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#define PC0_VECTOR (6 + DEVICE_VECTORS) // Performance counter 0
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#define EISA_NMI_VECTOR (7 + DEVICE_VECTORS) // NMI vector
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#define PC1_VECTOR (8 + DEVICE_VECTORS) // Performance counter 1
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#define IPI_VECTOR (9 + DEVICE_VECTORS) // Inter-processor interrupt
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#define PIC_VECTOR (10 + DEVICE_VECTORS) // Programmable Interrupt Ctrler
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#define PC0_SECONDARY_VECTOR (11 + DEVICE_VECTORS) // Performance counter 0
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#define ERROR_VECTOR (12 + DEVICE_VECTORS) // Error interrupt vector
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#define PC1_SECONDARY_VECTOR (13 + DEVICE_VECTORS) // Performance counter 1
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#define HALT_VECTOR (14 + DEVICE_VECTORS) // Halt Button interrupt vector
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#define PC2_VECTOR (15 + DEVICE_VECTORS) // Performance counter 2
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#define PC2_SECONDARY_VECTOR (16 + DEVICE_VECTORS) // Performance counter 2
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#define PC4_VECTOR (17 + DEVICE_VECTORS) // Performance counter 4
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#define PC5_VECTOR (18 + DEVICE_VECTORS) // Performance counter 5
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#define CORRECTABLE_VECTOR (19 + DEVICE_VECTORS) //correctable
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#define UNUSED_VECTOR (20 + DEVICE_VECTORS) // Highest possible builtin vector
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#define MAXIMUM_BUILTIN_VECTOR UNUSED_VECTOR // maximum builtin vector
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//
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// The following vectors can be used for primary processor interrupt
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// dispatch.
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//
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#define PRIMARY_VECTORS (20)
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#define PRIMARY0_VECTOR (0 + PRIMARY_VECTORS)
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#define PRIMARY1_VECTOR (1 + PRIMARY_VECTORS)
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#define PRIMARY2_VECTOR (2 + PRIMARY_VECTORS)
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#define PRIMARY3_VECTOR (3 + PRIMARY_VECTORS)
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#define PRIMARY4_VECTOR (4 + PRIMARY_VECTORS)
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#define PRIMARY5_VECTOR (5 + PRIMARY_VECTORS)
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#define PRIMARY6_VECTOR (6 + PRIMARY_VECTORS)
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#define PRIMARY7_VECTOR (7 + PRIMARY_VECTORS)
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#define PRIMARY8_VECTOR (8 + PRIMARY_VECTORS)
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#define PRIMARY9_VECTOR (9 + PRIMARY_VECTORS)
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//
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// Define profile intervals.
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//
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#define DEFAULT_PROFILE_COUNT 0x40000000 // ~= 20 seconds @50mhz
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#define DEFAULT_PROFILE_INTERVAL (10 * 500) // 500 microseconds
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#define MAXIMUM_PROFILE_INTERVAL (10 * 1000 * 1000) // 1 second
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#define MINIMUM_PROFILE_INTERVAL (10 * 40) // 40 microseconds
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//
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// Define the QVA selector bits which indicate an address is a
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// "QVA" - quasi-virtual address.
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//
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#define QVA_ENABLE 0xA0000000
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#endif // _ALPHAREF_
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