/*++ Copyright (c) Microsoft Corporation. All rights reserved. Module Name: miniport.h Abstract: Type definitions for miniport drivers. Revision History: --*/ #ifndef _MINIPORT_ #define _MINIPORT_ #include "stddef.h" #define ASSERT( exp ) #ifndef FAR #define FAR #endif #ifndef IN #define IN #endif #ifndef OUT #define OUT #endif #ifndef OPTIONAL #define OPTIONAL #endif #ifndef NOTHING #define NOTHING #endif #ifndef CRITICAL #define CRITICAL #endif #ifndef ANYSIZE_ARRAY #define ANYSIZE_ARRAY 1 // winnt #endif // begin_winnt #if defined(_M_MRX000) && !(defined(MIDL_PASS) || defined(RC_INVOKED)) && defined(ENABLE_RESTRICTED) #define RESTRICTED_POINTER __restrict #else #define RESTRICTED_POINTER #endif #if defined(_M_MRX000) || defined(_M_ALPHA) || defined(_M_PPC) || defined(_M_IA64) || defined(_M_AMD64) #define UNALIGNED __unaligned #if defined(_WIN64) #define UNALIGNED64 __unaligned #else #define UNALIGNED64 #endif #else #define UNALIGNED #define UNALIGNED64 #endif #if defined(_WIN64) || defined(_M_ALPHA) #define MAX_NATURAL_ALIGNMENT sizeof(ULONGLONG) #define MEMORY_ALLOCATION_ALIGNMENT 16 #else #define MAX_NATURAL_ALIGNMENT sizeof(ULONG) #define MEMORY_ALLOCATION_ALIGNMENT 8 #endif // // TYPE_ALIGNMENT will return the alignment requirements of a given type for // the current platform. // #ifdef __cplusplus #if _MSC_VER >= 1300 #define TYPE_ALIGNMENT( t ) __alignof(t) #endif #else #define TYPE_ALIGNMENT( t ) \ FIELD_OFFSET( struct { char x; t test; }, test ) #endif #if defined(_WIN64) #define PROBE_ALIGNMENT( _s ) (TYPE_ALIGNMENT( _s ) > TYPE_ALIGNMENT( ULONG ) ? \ TYPE_ALIGNMENT( _s ) : TYPE_ALIGNMENT( ULONG )) #define PROBE_ALIGNMENT32( _s ) TYPE_ALIGNMENT( ULONG ) #else #define PROBE_ALIGNMENT( _s ) TYPE_ALIGNMENT( ULONG ) #endif // // C_ASSERT() can be used to perform many compile-time assertions: // type sizes, field offsets, etc. // // An assertion failure results in error C2118: negative subscript. // #define C_ASSERT(e) typedef char __C_ASSERT__[(e)?1:-1] #if !defined(_MAC) && (defined(_M_MRX000) || defined(_M_AMD64) || defined(_M_IA64)) && (_MSC_VER >= 1100) && !(defined(MIDL_PASS) || defined(RC_INVOKED)) #define POINTER_64 __ptr64 typedef unsigned __int64 POINTER_64_INT; #if defined(_WIN64) #define POINTER_32 __ptr32 #else #define POINTER_32 #endif #else #if defined(_MAC) && defined(_MAC_INT_64) #define POINTER_64 __ptr64 typedef unsigned __int64 POINTER_64_INT; #else #define POINTER_64 typedef unsigned long POINTER_64_INT; #endif #define POINTER_32 #endif #if defined(_IA64_) || defined(_AMD64_) #define FIRMWARE_PTR #else #define FIRMWARE_PTR POINTER_32 #endif #include // end_winnt #ifndef CONST #define CONST const #endif // begin_winnt #if (defined(_M_IX86) || defined(_M_IA64) || defined(_M_AMD64)) && !defined(MIDL_PASS) #define DECLSPEC_IMPORT __declspec(dllimport) #else #define DECLSPEC_IMPORT #endif #ifndef DECLSPEC_NORETURN #if (_MSC_VER >= 1200) && !defined(MIDL_PASS) #define DECLSPEC_NORETURN __declspec(noreturn) #else #define DECLSPEC_NORETURN #endif #endif #ifndef DECLSPEC_ALIGN #if (_MSC_VER >= 1300) && !defined(MIDL_PASS) #define DECLSPEC_ALIGN(x) __declspec(align(x)) #else #define DECLSPEC_ALIGN(x) #endif #endif #ifndef DECLSPEC_CACHEALIGN #define DECLSPEC_CACHEALIGN DECLSPEC_ALIGN(128) #endif #ifndef DECLSPEC_UUID #if (_MSC_VER >= 1100) && defined (__cplusplus) #define DECLSPEC_UUID(x) __declspec(uuid(x)) #else #define DECLSPEC_UUID(x) #endif #endif #ifndef DECLSPEC_NOVTABLE #if (_MSC_VER >= 1100) && defined(__cplusplus) #define DECLSPEC_NOVTABLE __declspec(novtable) #else #define DECLSPEC_NOVTABLE #endif #endif #ifndef DECLSPEC_SELECTANY #if (_MSC_VER >= 1100) #define DECLSPEC_SELECTANY __declspec(selectany) #else #define DECLSPEC_SELECTANY #endif #endif #ifndef NOP_FUNCTION #if (_MSC_VER >= 1210) #define NOP_FUNCTION __noop #else #define NOP_FUNCTION (void)0 #endif #endif #ifndef DECLSPEC_ADDRSAFE #if (_MSC_VER >= 1200) && (defined(_M_ALPHA) || defined(_M_AXP64)) #define DECLSPEC_ADDRSAFE __declspec(address_safe) #else #define DECLSPEC_ADDRSAFE #endif #endif #ifndef FORCEINLINE #if (_MSC_VER >= 1200) #define FORCEINLINE __forceinline #else #define FORCEINLINE __inline #endif #endif #ifndef DECLSPEC_DEPRECATED #if (_MSC_VER >= 1300) && !defined(MIDL_PASS) #define DECLSPEC_DEPRECATED __declspec(deprecated) #define DEPRECATE_SUPPORTED #else #define DECLSPEC_DEPRECATED #undef DEPRECATE_SUPPORTED #endif #endif // end_winnt #ifdef DEPRECATE_DDK_FUNCTIONS #ifdef _NTDDK_ #define DECLSPEC_DEPRECATED_DDK DECLSPEC_DEPRECATED #ifdef DEPRECATE_SUPPORTED #define PRAGMA_DEPRECATED_DDK 1 #endif #else #define DECLSPEC_DEPRECATED_DDK #define PRAGMA_DEPRECATED_DDK 1 #endif #else #define DECLSPEC_DEPRECATED_DDK #define PRAGMA_DEPRECATED_DDK 0 #endif // // Void // // begin_winnt typedef void *PVOID; typedef void * POINTER_64 PVOID64; // end_winnt #if defined(_M_IX86) #define FASTCALL _fastcall #else #define FASTCALL #endif // // Basics // #ifndef VOID #define VOID void typedef char CHAR; typedef short SHORT; typedef long LONG; #endif // // UNICODE (Wide Character) types // #ifndef _MAC typedef wchar_t WCHAR; // wc, 16-bit UNICODE character #else // some Macintosh compilers don't define wchar_t in a convenient location, or define it as a char typedef unsigned short WCHAR; // wc, 16-bit UNICODE character #endif typedef WCHAR *PWCHAR; typedef WCHAR *LPWCH, *PWCH; typedef CONST WCHAR *LPCWCH, *PCWCH; typedef WCHAR *NWPSTR; typedef WCHAR *LPWSTR, *PWSTR; typedef WCHAR UNALIGNED *LPUWSTR, *PUWSTR; typedef CONST WCHAR *LPCWSTR, *PCWSTR; typedef CONST WCHAR UNALIGNED *LPCUWSTR, *PCUWSTR; // // ANSI (Multi-byte Character) types // typedef CHAR *PCHAR; typedef CHAR *LPCH, *PCH; typedef CONST CHAR *LPCCH, *PCCH; typedef CHAR *NPSTR; typedef CHAR *LPSTR, *PSTR; typedef CONST CHAR *LPCSTR, *PCSTR; // // Neutral ANSI/UNICODE types and macros // #ifdef UNICODE // r_winnt #ifndef _TCHAR_DEFINED typedef WCHAR TCHAR, *PTCHAR; typedef WCHAR TUCHAR, *PTUCHAR; #define _TCHAR_DEFINED #endif /* !_TCHAR_DEFINED */ typedef LPWSTR LPTCH, PTCH; typedef LPWSTR PTSTR, LPTSTR; typedef LPCWSTR PCTSTR, LPCTSTR; typedef LPUWSTR PUTSTR, LPUTSTR; typedef LPCUWSTR PCUTSTR, LPCUTSTR; typedef LPWSTR LP; #define __TEXT(quote) L##quote // r_winnt #else /* UNICODE */ // r_winnt #ifndef _TCHAR_DEFINED typedef char TCHAR, *PTCHAR; typedef unsigned char TUCHAR, *PTUCHAR; #define _TCHAR_DEFINED #endif /* !_TCHAR_DEFINED */ typedef LPSTR LPTCH, PTCH; typedef LPSTR PTSTR, LPTSTR, PUTSTR, LPUTSTR; typedef LPCSTR PCTSTR, LPCTSTR, PCUTSTR, LPCUTSTR; #define __TEXT(quote) quote // r_winnt #endif /* UNICODE */ // r_winnt #define TEXT(quote) __TEXT(quote) // r_winnt // end_winnt typedef double DOUBLE; typedef struct _QUAD { // QUAD is for those times we want double DoNotUseThisField; // an 8 byte aligned 8 byte long structure } QUAD; // which is NOT really a floating point // number. Use DOUBLE if you want an FP // number. // // Pointer to Basics // typedef SHORT *PSHORT; // winnt typedef LONG *PLONG; // winnt typedef QUAD *PQUAD; // // Unsigned Basics // // Tell windef.h that some types are already defined. #define BASETYPES typedef unsigned char UCHAR; typedef unsigned short USHORT; typedef unsigned long ULONG; typedef QUAD UQUAD; // // Pointer to Unsigned Basics // typedef UCHAR *PUCHAR; typedef USHORT *PUSHORT; typedef ULONG *PULONG; typedef UQUAD *PUQUAD; // // Signed characters // typedef signed char SCHAR; typedef SCHAR *PSCHAR; #ifndef NO_STRICT #ifndef STRICT #define STRICT 1 #endif #endif // // Handle to an Object // // begin_winnt #ifdef STRICT typedef void *HANDLE; #define DECLARE_HANDLE(name) struct name##__ { int unused; }; typedef struct name##__ *name #else typedef PVOID HANDLE; #define DECLARE_HANDLE(name) typedef HANDLE name #endif typedef HANDLE *PHANDLE; // // Flag (bit) fields // typedef UCHAR FCHAR; typedef USHORT FSHORT; typedef ULONG FLONG; // Component Object Model defines, and macros #ifndef _HRESULT_DEFINED #define _HRESULT_DEFINED typedef LONG HRESULT; #endif // !_HRESULT_DEFINED #ifdef __cplusplus #define EXTERN_C extern "C" #else #define EXTERN_C extern #endif #if defined(_WIN32) || defined(_MPPC_) // Win32 doesn't support __export #ifdef _68K_ #define STDMETHODCALLTYPE __cdecl #else #define STDMETHODCALLTYPE __stdcall #endif #define STDMETHODVCALLTYPE __cdecl #define STDAPICALLTYPE __stdcall #define STDAPIVCALLTYPE __cdecl #else #define STDMETHODCALLTYPE __export __stdcall #define STDMETHODVCALLTYPE __export __cdecl #define STDAPICALLTYPE __export __stdcall #define STDAPIVCALLTYPE __export __cdecl #endif #define STDAPI EXTERN_C HRESULT STDAPICALLTYPE #define STDAPI_(type) EXTERN_C type STDAPICALLTYPE #define STDMETHODIMP HRESULT STDMETHODCALLTYPE #define STDMETHODIMP_(type) type STDMETHODCALLTYPE // The 'V' versions allow Variable Argument lists. #define STDAPIV EXTERN_C HRESULT STDAPIVCALLTYPE #define STDAPIV_(type) EXTERN_C type STDAPIVCALLTYPE #define STDMETHODIMPV HRESULT STDMETHODVCALLTYPE #define STDMETHODIMPV_(type) type STDMETHODVCALLTYPE // end_winnt // // Low order two bits of a handle are ignored by the system and available // for use by application code as tag bits. The remaining bits are opaque // and used to store a serial number and table index. // #define OBJ_HANDLE_TAGBITS 0x00000003L // // Cardinal Data Types [0 - 2**N-2) // typedef char CCHAR; // winnt typedef short CSHORT; typedef ULONG CLONG; typedef CCHAR *PCCHAR; typedef CSHORT *PCSHORT; typedef CLONG *PCLONG; // // __int64 is only supported by 2.0 and later midl. // __midl is set by the 2.0 midl and not by 1.0 midl. // #define _ULONGLONG_ #if (!defined (_MAC) && (!defined(MIDL_PASS) || defined(__midl)) && (!defined(_M_IX86) || (defined(_INTEGRAL_MAX_BITS) && _INTEGRAL_MAX_BITS >= 64))) typedef __int64 LONGLONG; typedef unsigned __int64 ULONGLONG; #define MAXLONGLONG (0x7fffffffffffffff) #else #if defined(_MAC) && defined(_MAC_INT_64) typedef __int64 LONGLONG; typedef unsigned __int64 ULONGLONG; #define MAXLONGLONG (0x7fffffffffffffff) #else typedef double LONGLONG; typedef double ULONGLONG; #endif //_MAC and int64 #endif typedef LONGLONG *PLONGLONG; typedef ULONGLONG *PULONGLONG; // Update Sequence Number typedef LONGLONG USN; #if defined(MIDL_PASS) typedef struct _LARGE_INTEGER { #else // MIDL_PASS typedef union _LARGE_INTEGER { struct { ULONG LowPart; LONG HighPart; }; struct { ULONG LowPart; LONG HighPart; } u; #endif //MIDL_PASS LONGLONG QuadPart; } LARGE_INTEGER; typedef LARGE_INTEGER *PLARGE_INTEGER; #if defined(MIDL_PASS) typedef struct _ULARGE_INTEGER { #else // MIDL_PASS typedef union _ULARGE_INTEGER { struct { ULONG LowPart; ULONG HighPart; }; struct { ULONG LowPart; ULONG HighPart; } u; #endif //MIDL_PASS ULONGLONG QuadPart; } ULARGE_INTEGER; typedef ULARGE_INTEGER *PULARGE_INTEGER; // // Physical address. // typedef LARGE_INTEGER PHYSICAL_ADDRESS, *PPHYSICAL_ADDRESS; // // Boolean // typedef UCHAR BOOLEAN; // winnt typedef BOOLEAN *PBOOLEAN; // winnt // // Constants // #define FALSE 0 #define TRUE 1 #ifndef NULL #ifdef __cplusplus #define NULL 0 #define NULL64 0 #else #define NULL ((void *)0) #define NULL64 ((void * POINTER_64)0) #endif #endif // NULL // // Calculate the byte offset of a field in a structure of type type. // #define FIELD_OFFSET(type, field) ((LONG)(LONG_PTR)&(((type *)0)->field)) #if(_WIN32_WINNT > 0x0500) // // Calculate the size of a field in a structure of type type, without // knowing or stating the type of the field. // #define RTL_FIELD_SIZE(type, field) (sizeof(((type *)0)->field)) // // Calculate the size of a structure of type type up through and // including a field. // #define RTL_SIZEOF_THROUGH_FIELD(type, field) \ (FIELD_OFFSET(type, field) + RTL_FIELD_SIZE(type, field)) // // RTL_CONTAINS_FIELD usage: // // if (RTL_CONTAINS_FIELD(pBlock, pBlock->cbSize, dwMumble)) { // safe to use pBlock->dwMumble // #define RTL_CONTAINS_FIELD(Struct, Size, Field) \ ( (((PCHAR)(&(Struct)->Field)) + sizeof((Struct)->Field)) <= (((PCHAR)(Struct))+(Size)) ) // // Return the number of elements in a statically sized array. // ULONG Buffer[100]; // RTL_NUMBER_OF(Buffer) == 100 // This is also popularly known as: NUMBER_OF, ARRSIZE, _countof, NELEM, etc. // #define RTL_NUMBER_OF(A) (sizeof(A)/sizeof((A)[0])) // // An expression that yields the type of a field in a struct. // #define RTL_FIELD_TYPE(type, field) (((type*)0)->field) // RTL_ to avoid collisions in the global namespace. // // Given typedef struct _FOO { BYTE Bar[123]; } FOO; // RTL_NUMBER_OF_FIELD(FOO, Bar) == 123 // #define RTL_NUMBER_OF_FIELD(type, field) (RTL_NUMBER_OF(RTL_FIELD_TYPE(type, field))) // // eg: // typedef struct FOO { // ULONG Integer; // PVOID Pointer; // } FOO; // // RTL_PADDING_BETWEEN_FIELDS(FOO, Integer, Pointer) == 0 for Win32, 4 for Win64 // #define RTL_PADDING_BETWEEN_FIELDS(T, F1, F2) \ ((FIELD_OFFSET(T, F2) > FIELD_OFFSET(T, F1)) \ ? (FIELD_OFFSET(T, F2) - FIELD_OFFSET(T, F1) - RTL_FIELD_SIZE(T, F1)) \ : (FIELD_OFFSET(T, F1) - FIELD_OFFSET(T, F2) - RTL_FIELD_SIZE(T, F2))) // RTL_ to avoid collisions in the global namespace. #if defined(__cplusplus) #define RTL_CONST_CAST(type) const_cast #else #define RTL_CONST_CAST(type) (type) #endif // end_winnt // // This works "generically" for Unicode and Ansi/Oem strings. // Usage: // const static UNICODE_STRING FooU = RTL_CONSTANT_STRING(L"Foo"); // const static STRING Foo = RTL_CONSTANT_STRING( "Foo"); // instead of the slower: // UNICODE_STRING FooU; // STRING Foo; // RtlInitUnicodeString(&FooU, L"Foo"); // RtlInitString(&Foo , "Foo"); // #define RTL_CONSTANT_STRING(s) { sizeof( s ) - sizeof( (s)[0] ), sizeof( s ), s } // begin_winnt // like sizeof // usually this would be * CHAR_BIT, but we don't necessarily have #include #define RTL_BITS_OF(sizeOfArg) (sizeof(sizeOfArg) * 8) #define RTL_BITS_OF_FIELD(type, field) (RTL_BITS_OF(RTL_FIELD_TYPE(type, field))) #endif /* _WIN32_WINNT > 0x0500 */ // // Calculate the address of the base of the structure given its type, and an // address of a field within the structure. // #define CONTAINING_RECORD(address, type, field) ((type *)( \ (PCHAR)(address) - \ (ULONG_PTR)(&((type *)0)->field))) // // Interrupt Request Level (IRQL) // typedef UCHAR KIRQL; typedef KIRQL *PKIRQL; // // Macros used to eliminate compiler warning generated when formal // parameters or local variables are not declared. // // Use DBG_UNREFERENCED_PARAMETER() when a parameter is not yet // referenced but will be once the module is completely developed. // // Use DBG_UNREFERENCED_LOCAL_VARIABLE() when a local variable is not yet // referenced but will be once the module is completely developed. // // Use UNREFERENCED_PARAMETER() if a parameter will never be referenced. // // DBG_UNREFERENCED_PARAMETER and DBG_UNREFERENCED_LOCAL_VARIABLE will // eventually be made into a null macro to help determine whether there // is unfinished work. // #if ! defined(lint) #define UNREFERENCED_PARAMETER(P) (P) #define DBG_UNREFERENCED_PARAMETER(P) (P) #define DBG_UNREFERENCED_LOCAL_VARIABLE(V) (V) #else // lint // Note: lint -e530 says don't complain about uninitialized variables for // this varible. Error 527 has to do with unreachable code. // -restore restores checking to the -save state #define UNREFERENCED_PARAMETER(P) \ /*lint -save -e527 -e530 */ \ { \ (P) = (P); \ } \ /*lint -restore */ #define DBG_UNREFERENCED_PARAMETER(P) \ /*lint -save -e527 -e530 */ \ { \ (P) = (P); \ } \ /*lint -restore */ #define DBG_UNREFERENCED_LOCAL_VARIABLE(V) \ /*lint -save -e527 -e530 */ \ { \ (V) = (V); \ } \ /*lint -restore */ #endif // lint // // Macro used to eliminate compiler warning 4715 within a switch statement // when all possible cases have already been accounted for. // // switch (a & 3) { // case 0: return 1; // case 1: return Foo(); // case 2: return Bar(); // case 3: return 1; // DEFAULT_UNREACHABLE; // #if (_MSC_VER > 1200) #define DEFAULT_UNREACHABLE default: __assume(0) #else // // Older compilers do not support __assume(), and there is no other free // method of eliminating the warning. // #define DEFAULT_UNREACHABLE #endif // end_winnt // // Define standard min and max macros // #ifndef NOMINMAX #ifndef min #define min(a,b) (((a) < (b)) ? (a) : (b)) #endif #ifndef max #define max(a,b) (((a) > (b)) ? (a) : (b)) #endif #endif // NOMINMAX #ifdef _X86_ // // Disable these two pragmas that evaluate to "sti" "cli" on x86 so that driver // writers to not leave them inadvertantly in their code. // #if !defined(MIDL_PASS) #if !defined(RC_INVOKED) #if _MSC_VER >= 1200 #pragma warning(push) #endif #pragma warning(disable:4164) // disable C4164 warning so that apps that // build with /Od don't get weird errors ! #ifdef _M_IX86 #pragma function(_enable) #pragma function(_disable) #endif #if _MSC_VER >= 1200 #pragma warning(pop) #else #pragma warning(default:4164) // reenable C4164 warning #endif #endif #endif #endif //_X86_ // // Define the I/O bus interface types. // typedef enum _INTERFACE_TYPE { InterfaceTypeUndefined = -1, Internal, Isa, Eisa, MicroChannel, TurboChannel, PCIBus, VMEBus, NuBus, PCMCIABus, CBus, MPIBus, MPSABus, ProcessorInternal, InternalPowerBus, PNPISABus, PNPBus, MaximumInterfaceType }INTERFACE_TYPE, *PINTERFACE_TYPE; // // Define the DMA transfer widths. // typedef enum _DMA_WIDTH { Width8Bits, Width16Bits, Width32Bits, MaximumDmaWidth }DMA_WIDTH, *PDMA_WIDTH; // // Define DMA transfer speeds. // typedef enum _DMA_SPEED { Compatible, TypeA, TypeB, TypeC, TypeF, MaximumDmaSpeed }DMA_SPEED, *PDMA_SPEED; // // Define Interface reference/dereference routines for // Interfaces exported by IRP_MN_QUERY_INTERFACE // typedef VOID (*PINTERFACE_REFERENCE)(PVOID Context); typedef VOID (*PINTERFACE_DEREFERENCE)(PVOID Context); // end_wdm // // Define types of bus information. // typedef enum _BUS_DATA_TYPE { ConfigurationSpaceUndefined = -1, Cmos, EisaConfiguration, Pos, CbusConfiguration, PCIConfiguration, VMEConfiguration, NuBusConfiguration, PCMCIAConfiguration, MPIConfiguration, MPSAConfiguration, PNPISAConfiguration, SgiInternalConfiguration, MaximumBusDataType } BUS_DATA_TYPE, *PBUS_DATA_TYPE; #include // // Interrupt modes. // typedef enum _KINTERRUPT_MODE { LevelSensitive, Latched } KINTERRUPT_MODE; // // Structures used by the kernel drivers to describe which ports must be // hooked out directly from the V86 emulator to the driver. // typedef enum _EMULATOR_PORT_ACCESS_TYPE { Uchar, Ushort, Ulong } EMULATOR_PORT_ACCESS_TYPE, *PEMULATOR_PORT_ACCESS_TYPE; // // Access Modes // #define EMULATOR_READ_ACCESS 0x01 #define EMULATOR_WRITE_ACCESS 0x02 typedef struct _EMULATOR_ACCESS_ENTRY { ULONG BasePort; ULONG NumConsecutivePorts; EMULATOR_PORT_ACCESS_TYPE AccessType; UCHAR AccessMode; UCHAR StringSupport; PVOID Routine; } EMULATOR_ACCESS_ENTRY, *PEMULATOR_ACCESS_ENTRY; typedef struct _PCI_SLOT_NUMBER { union { struct { ULONG DeviceNumber:5; ULONG FunctionNumber:3; ULONG Reserved:24; } bits; ULONG AsULONG; } u; } PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER; #define PCI_TYPE0_ADDRESSES 6 #define PCI_TYPE1_ADDRESSES 2 #define PCI_TYPE2_ADDRESSES 5 typedef struct _PCI_COMMON_CONFIG { USHORT VendorID; // (ro) USHORT DeviceID; // (ro) USHORT Command; // Device control USHORT Status; UCHAR RevisionID; // (ro) UCHAR ProgIf; // (ro) UCHAR SubClass; // (ro) UCHAR BaseClass; // (ro) UCHAR CacheLineSize; // (ro+) UCHAR LatencyTimer; // (ro+) UCHAR HeaderType; // (ro) UCHAR BIST; // Built in self test union { struct _PCI_HEADER_TYPE_0 { ULONG BaseAddresses[PCI_TYPE0_ADDRESSES]; ULONG CIS; USHORT SubVendorID; USHORT SubSystemID; ULONG ROMBaseAddress; UCHAR CapabilitiesPtr; UCHAR Reserved1[3]; ULONG Reserved2; UCHAR InterruptLine; // UCHAR InterruptPin; // (ro) UCHAR MinimumGrant; // (ro) UCHAR MaximumLatency; // (ro) } type0; } u; UCHAR DeviceSpecific[192]; } PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG; #define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific)) #define PCI_MAX_DEVICES 32 #define PCI_MAX_FUNCTION 8 #define PCI_MAX_BRIDGE_NUMBER 0xFF #define PCI_INVALID_VENDORID 0xFFFF // // Bit encodings for PCI_COMMON_CONFIG.HeaderType // #define PCI_MULTIFUNCTION 0x80 #define PCI_DEVICE_TYPE 0x00 #define PCI_BRIDGE_TYPE 0x01 #define PCI_CARDBUS_BRIDGE_TYPE 0x02 #define PCI_CONFIGURATION_TYPE(PciData) \ (((PPCI_COMMON_CONFIG)(PciData))->HeaderType & ~PCI_MULTIFUNCTION) #define PCI_MULTIFUNCTION_DEVICE(PciData) \ ((((PPCI_COMMON_CONFIG)(PciData))->HeaderType & PCI_MULTIFUNCTION) != 0) // // Bit encodings for PCI_COMMON_CONFIG.Command // #define PCI_ENABLE_IO_SPACE 0x0001 #define PCI_ENABLE_MEMORY_SPACE 0x0002 #define PCI_ENABLE_BUS_MASTER 0x0004 #define PCI_ENABLE_SPECIAL_CYCLES 0x0008 #define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010 #define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020 #define PCI_ENABLE_PARITY 0x0040 // (ro+) #define PCI_ENABLE_WAIT_CYCLE 0x0080 // (ro+) #define PCI_ENABLE_SERR 0x0100 // (ro+) #define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 // (ro) // // Bit encodings for PCI_COMMON_CONFIG.Status // #define PCI_STATUS_CAPABILITIES_LIST 0x0010 // (ro) #define PCI_STATUS_66MHZ_CAPABLE 0x0020 // (ro) #define PCI_STATUS_UDF_SUPPORTED 0x0040 // (ro) #define PCI_STATUS_FAST_BACK_TO_BACK 0x0080 // (ro) #define PCI_STATUS_DATA_PARITY_DETECTED 0x0100 #define PCI_STATUS_DEVSEL 0x0600 // 2 bits wide #define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800 #define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000 #define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000 #define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000 #define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000 // // The NT PCI Driver uses a WhichSpace parameter on its CONFIG_READ/WRITE // routines. The following values are defined- // #define PCI_WHICHSPACE_CONFIG 0x0 #define PCI_WHICHSPACE_ROM 0x52696350 // end_wdm // // PCI Capability IDs // #define PCI_CAPABILITY_ID_POWER_MANAGEMENT 0x01 #define PCI_CAPABILITY_ID_AGP 0x02 #define PCI_CAPABILITY_ID_MSI 0x05 // // All PCI Capability structures have the following header. // // CapabilityID is used to identify the type of the structure (is // one of the PCI_CAPABILITY_ID values above. // // Next is the offset in PCI Configuration space (0x40 - 0xfc) of the // next capability structure in the list, or 0x00 if there are no more // entries. // typedef struct _PCI_CAPABILITIES_HEADER { UCHAR CapabilityID; UCHAR Next; } PCI_CAPABILITIES_HEADER, *PPCI_CAPABILITIES_HEADER; // // Power Management Capability // typedef struct _PCI_PMC { UCHAR Version:3; UCHAR PMEClock:1; UCHAR Rsvd1:1; UCHAR DeviceSpecificInitialization:1; UCHAR Rsvd2:2; struct _PM_SUPPORT { UCHAR Rsvd2:1; UCHAR D1:1; UCHAR D2:1; UCHAR PMED0:1; UCHAR PMED1:1; UCHAR PMED2:1; UCHAR PMED3Hot:1; UCHAR PMED3Cold:1; } Support; } PCI_PMC, *PPCI_PMC; typedef struct _PCI_PMCSR { USHORT PowerState:2; USHORT Rsvd1:6; USHORT PMEEnable:1; USHORT DataSelect:4; USHORT DataScale:2; USHORT PMEStatus:1; } PCI_PMCSR, *PPCI_PMCSR; typedef struct _PCI_PMCSR_BSE { UCHAR Rsvd1:6; UCHAR D3HotSupportsStopClock:1; // B2_B3# UCHAR BusPowerClockControlEnabled:1; // BPCC_EN } PCI_PMCSR_BSE, *PPCI_PMCSR_BSE; typedef struct _PCI_PM_CAPABILITY { PCI_CAPABILITIES_HEADER Header; // // Power Management Capabilities (Offset = 2) // union { PCI_PMC Capabilities; USHORT AsUSHORT; } PMC; // // Power Management Control/Status (Offset = 4) // union { PCI_PMCSR ControlStatus; USHORT AsUSHORT; } PMCSR; // // PMCSR PCI-PCI Bridge Support Extensions // union { PCI_PMCSR_BSE BridgeSupport; UCHAR AsUCHAR; } PMCSR_BSE; // // Optional read only 8 bit Data register. Contents controlled by // DataSelect and DataScale in ControlStatus. // UCHAR Data; } PCI_PM_CAPABILITY, *PPCI_PM_CAPABILITY; // // AGP Capability // typedef struct _PCI_AGP_CAPABILITY { PCI_CAPABILITIES_HEADER Header; USHORT Minor:4; USHORT Major:4; USHORT Rsvd1:8; struct _PCI_AGP_STATUS { ULONG Rate:3; ULONG Rsvd1:1; ULONG FastWrite:1; ULONG FourGB:1; ULONG Rsvd2:3; ULONG SideBandAddressing:1; // SBA ULONG Rsvd3:14; ULONG RequestQueueDepthMaximum:8; // RQ } AGPStatus; struct _PCI_AGP_COMMAND { ULONG Rate:3; ULONG Rsvd1:1; ULONG FastWriteEnable:1; ULONG FourGBEnable:1; ULONG Rsvd2:2; ULONG AGPEnable:1; ULONG SBAEnable:1; ULONG Rsvd3:14; ULONG RequestQueueDepth:8; } AGPCommand; } PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY; #define PCI_AGP_RATE_1X 0x1 #define PCI_AGP_RATE_2X 0x2 #define PCI_AGP_RATE_4X 0x4 // // MSI (Message Signalled Interrupts) Capability // typedef struct _PCI_MSI_CAPABILITY { PCI_CAPABILITIES_HEADER Header; struct _PCI_MSI_MESSAGE_CONTROL { USHORT MSIEnable:1; USHORT MultipleMessageCapable:3; USHORT MultipleMessageEnable:3; USHORT CapableOf64Bits:1; USHORT Reserved:8; } MessageControl; union { struct _PCI_MSI_MESSAGE_ADDRESS { ULONG_PTR Reserved:2; // always zero, DWORD aligned address ULONG_PTR Address:30; } Register; ULONG_PTR Raw; } MessageAddress; // // The rest of the Capability structure differs depending on whether // 32bit or 64bit addressing is being used. // // (The CapableOf64Bits bit above determines this) // union { // For 64 bit devices struct _PCI_MSI_64BIT_DATA { ULONG MessageUpperAddress; USHORT MessageData; } Bit64; // For 32 bit devices struct _PCI_MSI_32BIT_DATA { USHORT MessageData; ULONG Unused; } Bit32; } Data; } PCI_MSI_CAPABILITY, *PPCI_PCI_CAPABILITY; // begin_wdm // // Base Class Code encodings for Base Class (from PCI spec rev 2.1). // #define PCI_CLASS_PRE_20 0x00 #define PCI_CLASS_MASS_STORAGE_CTLR 0x01 #define PCI_CLASS_NETWORK_CTLR 0x02 #define PCI_CLASS_DISPLAY_CTLR 0x03 #define PCI_CLASS_MULTIMEDIA_DEV 0x04 #define PCI_CLASS_MEMORY_CTLR 0x05 #define PCI_CLASS_BRIDGE_DEV 0x06 #define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07 #define PCI_CLASS_BASE_SYSTEM_DEV 0x08 #define PCI_CLASS_INPUT_DEV 0x09 #define PCI_CLASS_DOCKING_STATION 0x0a #define PCI_CLASS_PROCESSOR 0x0b #define PCI_CLASS_SERIAL_BUS_CTLR 0x0c #define PCI_CLASS_WIRELESS_CTLR 0x0d #define PCI_CLASS_INTELLIGENT_IO_CTLR 0x0e #define PCI_CLASS_SATELLITE_COMMS_CTLR 0x0f #define PCI_CLASS_ENCRYPTION_DECRYPTION 0x10 #define PCI_CLASS_DATA_ACQ_SIGNAL_PROC 0x11 // 0d thru fe reserved #define PCI_CLASS_NOT_DEFINED 0xff // // Sub Class Code encodings (PCI rev 2.1). // // Class 00 - PCI_CLASS_PRE_20 #define PCI_SUBCLASS_PRE_20_NON_VGA 0x00 #define PCI_SUBCLASS_PRE_20_VGA 0x01 // Class 01 - PCI_CLASS_MASS_STORAGE_CTLR #define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00 #define PCI_SUBCLASS_MSC_IDE_CTLR 0x01 #define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02 #define PCI_SUBCLASS_MSC_IPI_CTLR 0x03 #define PCI_SUBCLASS_MSC_RAID_CTLR 0x04 #define PCI_SUBCLASS_MSC_OTHER 0x80 // Class 02 - PCI_CLASS_NETWORK_CTLR #define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00 #define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01 #define PCI_SUBCLASS_NET_FDDI_CTLR 0x02 #define PCI_SUBCLASS_NET_ATM_CTLR 0x03 #define PCI_SUBCLASS_NET_ISDN_CTLR 0x04 #define PCI_SUBCLASS_NET_OTHER 0x80 // Class 03 - PCI_CLASS_DISPLAY_CTLR // N.B. Sub Class 00 could be VGA or 8514 depending on Interface byte #define PCI_SUBCLASS_VID_VGA_CTLR 0x00 #define PCI_SUBCLASS_VID_XGA_CTLR 0x01 #define PCI_SUBLCASS_VID_3D_CTLR 0x02 #define PCI_SUBCLASS_VID_OTHER 0x80 // Class 04 - PCI_CLASS_MULTIMEDIA_DEV #define PCI_SUBCLASS_MM_VIDEO_DEV 0x00 #define PCI_SUBCLASS_MM_AUDIO_DEV 0x01 #define PCI_SUBCLASS_MM_TELEPHONY_DEV 0x02 #define PCI_SUBCLASS_MM_OTHER 0x80 // Class 05 - PCI_CLASS_MEMORY_CTLR #define PCI_SUBCLASS_MEM_RAM 0x00 #define PCI_SUBCLASS_MEM_FLASH 0x01 #define PCI_SUBCLASS_MEM_OTHER 0x80 // Class 06 - PCI_CLASS_BRIDGE_DEV #define PCI_SUBCLASS_BR_HOST 0x00 #define PCI_SUBCLASS_BR_ISA 0x01 #define PCI_SUBCLASS_BR_EISA 0x02 #define PCI_SUBCLASS_BR_MCA 0x03 #define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04 #define PCI_SUBCLASS_BR_PCMCIA 0x05 #define PCI_SUBCLASS_BR_NUBUS 0x06 #define PCI_SUBCLASS_BR_CARDBUS 0x07 #define PCI_SUBCLASS_BR_RACEWAY 0x08 #define PCI_SUBCLASS_BR_OTHER 0x80 // Class 07 - PCI_CLASS_SIMPLE_COMMS_CTLR // N.B. Sub Class 00 and 01 additional info in Interface byte #define PCI_SUBCLASS_COM_SERIAL 0x00 #define PCI_SUBCLASS_COM_PARALLEL 0x01 #define PCI_SUBCLASS_COM_MULTIPORT 0x02 #define PCI_SUBCLASS_COM_MODEM 0x03 #define PCI_SUBCLASS_COM_OTHER 0x80 // Class 08 - PCI_CLASS_BASE_SYSTEM_DEV // N.B. See Interface byte for additional info. #define PCI_SUBCLASS_SYS_INTERRUPT_CTLR 0x00 #define PCI_SUBCLASS_SYS_DMA_CTLR 0x01 #define PCI_SUBCLASS_SYS_SYSTEM_TIMER 0x02 #define PCI_SUBCLASS_SYS_REAL_TIME_CLOCK 0x03 #define PCI_SUBCLASS_SYS_GEN_HOTPLUG_CTLR 0x04 #define PCI_SUBCLASS_SYS_OTHER 0x80 // Class 09 - PCI_CLASS_INPUT_DEV #define PCI_SUBCLASS_INP_KEYBOARD 0x00 #define PCI_SUBCLASS_INP_DIGITIZER 0x01 #define PCI_SUBCLASS_INP_MOUSE 0x02 #define PCI_SUBCLASS_INP_SCANNER 0x03 #define PCI_SUBCLASS_INP_GAMEPORT 0x04 #define PCI_SUBCLASS_INP_OTHER 0x80 // Class 0a - PCI_CLASS_DOCKING_STATION #define PCI_SUBCLASS_DOC_GENERIC 0x00 #define PCI_SUBCLASS_DOC_OTHER 0x80 // Class 0b - PCI_CLASS_PROCESSOR #define PCI_SUBCLASS_PROC_386 0x00 #define PCI_SUBCLASS_PROC_486 0x01 #define PCI_SUBCLASS_PROC_PENTIUM 0x02 #define PCI_SUBCLASS_PROC_ALPHA 0x10 #define PCI_SUBCLASS_PROC_POWERPC 0x20 #define PCI_SUBCLASS_PROC_COPROCESSOR 0x40 // Class 0c - PCI_CLASS_SERIAL_BUS_CTLR #define PCI_SUBCLASS_SB_IEEE1394 0x00 #define PCI_SUBCLASS_SB_ACCESS 0x01 #define PCI_SUBCLASS_SB_SSA 0x02 #define PCI_SUBCLASS_SB_USB 0x03 #define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04 #define PCI_SUBCLASS_SB_SMBUS 0x05 // Class 0d - PCI_CLASS_WIRELESS_CTLR #define PCI_SUBCLASS_WIRELESS_IRDA 0x00 #define PCI_SUBCLASS_WIRELESS_CON_IR 0x01 #define PCI_SUBCLASS_WIRELESS_RF 0x10 #define PCI_SUBCLASS_WIRELESS_OTHER 0x80 // Class 0e - PCI_CLASS_INTELLIGENT_IO_CTLR #define PCI_SUBCLASS_INTIO_I2O 0x00 // Class 0f - PCI_CLASS_SATELLITE_CTLR #define PCI_SUBCLASS_SAT_TV 0x01 #define PCI_SUBCLASS_SAT_AUDIO 0x02 #define PCI_SUBCLASS_SAT_VOICE 0x03 #define PCI_SUBCLASS_SAT_DATA 0x04 // Class 10 - PCI_CLASS_ENCRYPTION_DECRYPTION #define PCI_SUBCLASS_CRYPTO_NET_COMP 0x00 #define PCI_SUBCLASS_CRYPTO_ENTERTAINMENT 0x10 #define PCI_SUBCLASS_CRYPTO_OTHER 0x80 // Class 11 - PCI_CLASS_DATA_ACQ_SIGNAL_PROC #define PCI_SUBCLASS_DASP_DPIO 0x00 #define PCI_SUBCLASS_DASP_OTHER 0x80 // end_ntndis // // Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses // #define PCI_ADDRESS_IO_SPACE 0x00000001 // (ro) #define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006 // (ro) #define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008 // (ro) #define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc #define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0 #define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800 #define PCI_TYPE_32BIT 0 #define PCI_TYPE_20BIT 2 #define PCI_TYPE_64BIT 4 // // Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses // #define PCI_ROMADDRESS_ENABLED 0x00000001 // // Reference notes for PCI configuration fields: // // ro these field are read only. changes to these fields are ignored // // ro+ these field are intended to be read only and should be initialized // by the system to their proper values. However, driver may change // these settings. // // --- // // All resources comsumed by a PCI device start as unitialized // under NT. An uninitialized memory or I/O base address can be // determined by checking it's corrisponding enabled bit in the // PCI_COMMON_CONFIG.Command value. An InterruptLine is unitialized // if it contains the value of -1. // // // Graphics support routines. // typedef VOID (*PBANKED_SECTION_ROUTINE) ( IN ULONG ReadBank, IN ULONG WriteBank, IN PVOID Context ); // // WMI minor function codes under IRP_MJ_SYSTEM_CONTROL // #define IRP_MN_QUERY_ALL_DATA 0x00 #define IRP_MN_QUERY_SINGLE_INSTANCE 0x01 #define IRP_MN_CHANGE_SINGLE_INSTANCE 0x02 #define IRP_MN_CHANGE_SINGLE_ITEM 0x03 #define IRP_MN_ENABLE_EVENTS 0x04 #define IRP_MN_DISABLE_EVENTS 0x05 #define IRP_MN_ENABLE_COLLECTION 0x06 #define IRP_MN_DISABLE_COLLECTION 0x07 #define IRP_MN_REGINFO 0x08 #define IRP_MN_EXECUTE_METHOD 0x09 // Minor code 0x0a is reserved #define IRP_MN_REGINFO_EX 0x0b // workaround overloaded definition (rpc generated headers all define INTERFACE // to match the class name). #undef INTERFACE typedef struct _INTERFACE { USHORT Size; USHORT Version; PVOID Context; PINTERFACE_REFERENCE InterfaceReference; PINTERFACE_DEREFERENCE InterfaceDereference; // interface specific entries go here } INTERFACE, *PINTERFACE; // // Defines the Type in the RESOURCE_DESCRIPTOR // // NOTE: For all CM_RESOURCE_TYPE values, there must be a // corresponding ResType value in the 32-bit ConfigMgr headerfile // (cfgmgr32.h). Values in the range [0x6,0x80) use the same values // as their ConfigMgr counterparts. CM_RESOURCE_TYPE values with // the high bit set (i.e., in the range [0x80,0xFF]), are // non-arbitrated resources. These correspond to the same values // in cfgmgr32.h that have their high bit set (however, since // cfgmgr32.h uses 16 bits for ResType values, these values are in // the range [0x8000,0x807F). Note that ConfigMgr ResType values // cannot be in the range [0x8080,0xFFFF), because they would not // be able to map into CM_RESOURCE_TYPE values. (0xFFFF itself is // a special value, because it maps to CmResourceTypeDeviceSpecific.) // typedef int CM_RESOURCE_TYPE; // CmResourceTypeNull is reserved #define CmResourceTypeNull 0 // ResType_All or ResType_None (0x0000) #define CmResourceTypePort 1 // ResType_IO (0x0002) #define CmResourceTypeInterrupt 2 // ResType_IRQ (0x0004) #define CmResourceTypeMemory 3 // ResType_Mem (0x0001) #define CmResourceTypeDma 4 // ResType_DMA (0x0003) #define CmResourceTypeDeviceSpecific 5 // ResType_ClassSpecific (0xFFFF) #define CmResourceTypeBusNumber 6 // ResType_BusNumber (0x0006) // end_wdm #define CmResourceTypeMaximum 7 // begin_wdm #define CmResourceTypeNonArbitrated 128 // Not arbitrated if 0x80 bit set #define CmResourceTypeConfigData 128 // ResType_Reserved (0x8000) #define CmResourceTypeDevicePrivate 129 // ResType_DevicePrivate (0x8001) #define CmResourceTypePcCardConfig 130 // ResType_PcCardConfig (0x8002) #define CmResourceTypeMfCardConfig 131 // ResType_MfCardConfig (0x8003) // // Defines the ShareDisposition in the RESOURCE_DESCRIPTOR // typedef enum _CM_SHARE_DISPOSITION { CmResourceShareUndetermined = 0, // Reserved CmResourceShareDeviceExclusive, CmResourceShareDriverExclusive, CmResourceShareShared } CM_SHARE_DISPOSITION; // // Define the bit masks for Flags when type is CmResourceTypeInterrupt // #define CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE 0 #define CM_RESOURCE_INTERRUPT_LATCHED 1 // // Define the bit masks for Flags when type is CmResourceTypeMemory // #define CM_RESOURCE_MEMORY_READ_WRITE 0x0000 #define CM_RESOURCE_MEMORY_READ_ONLY 0x0001 #define CM_RESOURCE_MEMORY_WRITE_ONLY 0x0002 #define CM_RESOURCE_MEMORY_PREFETCHABLE 0x0004 #define CM_RESOURCE_MEMORY_COMBINEDWRITE 0x0008 #define CM_RESOURCE_MEMORY_24 0x0010 #define CM_RESOURCE_MEMORY_CACHEABLE 0x0020 // // Define the bit masks for Flags when type is CmResourceTypePort // #define CM_RESOURCE_PORT_MEMORY 0x0000 #define CM_RESOURCE_PORT_IO 0x0001 #define CM_RESOURCE_PORT_10_BIT_DECODE 0x0004 #define CM_RESOURCE_PORT_12_BIT_DECODE 0x0008 #define CM_RESOURCE_PORT_16_BIT_DECODE 0x0010 #define CM_RESOURCE_PORT_POSITIVE_DECODE 0x0020 #define CM_RESOURCE_PORT_PASSIVE_DECODE 0x0040 #define CM_RESOURCE_PORT_WINDOW_DECODE 0x0080 // // Define the bit masks for Flags when type is CmResourceTypeDma // #define CM_RESOURCE_DMA_8 0x0000 #define CM_RESOURCE_DMA_16 0x0001 #define CM_RESOURCE_DMA_32 0x0002 #define CM_RESOURCE_DMA_8_AND_16 0x0004 #define CM_RESOURCE_DMA_BUS_MASTER 0x0008 #define CM_RESOURCE_DMA_TYPE_A 0x0010 #define CM_RESOURCE_DMA_TYPE_B 0x0020 #define CM_RESOURCE_DMA_TYPE_F 0x0040 #include "pshpack1.h" // // Define Mca POS data block for slot // typedef struct _CM_MCA_POS_DATA { USHORT AdapterId; UCHAR PosData1; UCHAR PosData2; UCHAR PosData3; UCHAR PosData4; } CM_MCA_POS_DATA, *PCM_MCA_POS_DATA; // // Memory configuration of eisa data block structure // typedef struct _EISA_MEMORY_TYPE { UCHAR ReadWrite: 1; UCHAR Cached : 1; UCHAR Reserved0 :1; UCHAR Type:2; UCHAR Shared:1; UCHAR Reserved1 :1; UCHAR MoreEntries : 1; } EISA_MEMORY_TYPE, *PEISA_MEMORY_TYPE; typedef struct _EISA_MEMORY_CONFIGURATION { EISA_MEMORY_TYPE ConfigurationByte; UCHAR DataSize; USHORT AddressLowWord; UCHAR AddressHighByte; USHORT MemorySize; } EISA_MEMORY_CONFIGURATION, *PEISA_MEMORY_CONFIGURATION; // // Interrupt configurationn of eisa data block structure // typedef struct _EISA_IRQ_DESCRIPTOR { UCHAR Interrupt : 4; UCHAR Reserved :1; UCHAR LevelTriggered :1; UCHAR Shared : 1; UCHAR MoreEntries : 1; } EISA_IRQ_DESCRIPTOR, *PEISA_IRQ_DESCRIPTOR; typedef struct _EISA_IRQ_CONFIGURATION { EISA_IRQ_DESCRIPTOR ConfigurationByte; UCHAR Reserved; } EISA_IRQ_CONFIGURATION, *PEISA_IRQ_CONFIGURATION; // // DMA description of eisa data block structure // typedef struct _DMA_CONFIGURATION_BYTE0 { UCHAR Channel : 3; UCHAR Reserved : 3; UCHAR Shared :1; UCHAR MoreEntries :1; } DMA_CONFIGURATION_BYTE0; typedef struct _DMA_CONFIGURATION_BYTE1 { UCHAR Reserved0 : 2; UCHAR TransferSize : 2; UCHAR Timing : 2; UCHAR Reserved1 : 2; } DMA_CONFIGURATION_BYTE1; typedef struct _EISA_DMA_CONFIGURATION { DMA_CONFIGURATION_BYTE0 ConfigurationByte0; DMA_CONFIGURATION_BYTE1 ConfigurationByte1; } EISA_DMA_CONFIGURATION, *PEISA_DMA_CONFIGURATION; // // Port description of eisa data block structure // typedef struct _EISA_PORT_DESCRIPTOR { UCHAR NumberPorts : 5; UCHAR Reserved :1; UCHAR Shared :1; UCHAR MoreEntries : 1; } EISA_PORT_DESCRIPTOR, *PEISA_PORT_DESCRIPTOR; typedef struct _EISA_PORT_CONFIGURATION { EISA_PORT_DESCRIPTOR Configuration; USHORT PortAddress; } EISA_PORT_CONFIGURATION, *PEISA_PORT_CONFIGURATION; // // Eisa slot information definition // N.B. This structure is different from the one defined // in ARC eisa addendum. // typedef struct _CM_EISA_SLOT_INFORMATION { UCHAR ReturnCode; UCHAR ReturnFlags; UCHAR MajorRevision; UCHAR MinorRevision; USHORT Checksum; UCHAR NumberFunctions; UCHAR FunctionInformation; ULONG CompressedId; } CM_EISA_SLOT_INFORMATION, *PCM_EISA_SLOT_INFORMATION; // // Eisa function information definition // typedef struct _CM_EISA_FUNCTION_INFORMATION { ULONG CompressedId; UCHAR IdSlotFlags1; UCHAR IdSlotFlags2; UCHAR MinorRevision; UCHAR MajorRevision; UCHAR Selections[26]; UCHAR FunctionFlags; UCHAR TypeString[80]; EISA_MEMORY_CONFIGURATION EisaMemory[9]; EISA_IRQ_CONFIGURATION EisaIrq[7]; EISA_DMA_CONFIGURATION EisaDma[4]; EISA_PORT_CONFIGURATION EisaPort[20]; UCHAR InitializationData[60]; } CM_EISA_FUNCTION_INFORMATION, *PCM_EISA_FUNCTION_INFORMATION; // // The following defines the way pnp bios information is stored in // the registry \\HKEY_LOCAL_MACHINE\HARDWARE\Description\System\MultifunctionAdapter\x // key, where x is an integer number indicating adapter instance. The // "Identifier" of the key must equal to "PNP BIOS" and the // "ConfigurationData" is organized as follow: // // CM_PNP_BIOS_INSTALLATION_CHECK + // CM_PNP_BIOS_DEVICE_NODE for device 1 + // CM_PNP_BIOS_DEVICE_NODE for device 2 + // ... // CM_PNP_BIOS_DEVICE_NODE for device n // // // Pnp BIOS device node structure // typedef struct _CM_PNP_BIOS_DEVICE_NODE { USHORT Size; UCHAR Node; ULONG ProductId; UCHAR DeviceType[3]; USHORT DeviceAttributes; // followed by AllocatedResourceBlock, PossibleResourceBlock // and CompatibleDeviceId } CM_PNP_BIOS_DEVICE_NODE,*PCM_PNP_BIOS_DEVICE_NODE; // // Pnp BIOS Installation check // typedef struct _CM_PNP_BIOS_INSTALLATION_CHECK { UCHAR Signature[4]; // $PnP (ascii) UCHAR Revision; UCHAR Length; USHORT ControlField; UCHAR Checksum; ULONG EventFlagAddress; // Physical address USHORT RealModeEntryOffset; USHORT RealModeEntrySegment; USHORT ProtectedModeEntryOffset; ULONG ProtectedModeCodeBaseAddress; ULONG OemDeviceId; USHORT RealModeDataBaseAddress; ULONG ProtectedModeDataBaseAddress; } CM_PNP_BIOS_INSTALLATION_CHECK, *PCM_PNP_BIOS_INSTALLATION_CHECK; #include "poppack.h" // // Masks for EISA function information // #define EISA_FUNCTION_ENABLED 0x80 #define EISA_FREE_FORM_DATA 0x40 #define EISA_HAS_PORT_INIT_ENTRY 0x20 #define EISA_HAS_PORT_RANGE 0x10 #define EISA_HAS_DMA_ENTRY 0x08 #define EISA_HAS_IRQ_ENTRY 0x04 #define EISA_HAS_MEMORY_ENTRY 0x02 #define EISA_HAS_TYPE_ENTRY 0x01 #define EISA_HAS_INFORMATION EISA_HAS_PORT_RANGE + \ EISA_HAS_DMA_ENTRY + \ EISA_HAS_IRQ_ENTRY + \ EISA_HAS_MEMORY_ENTRY + \ EISA_HAS_TYPE_ENTRY // // Masks for EISA memory configuration // #define EISA_MORE_ENTRIES 0x80 #define EISA_SYSTEM_MEMORY 0x00 #define EISA_MEMORY_TYPE_RAM 0x01 // // Returned error code for EISA bios call // #define EISA_INVALID_SLOT 0x80 #define EISA_INVALID_FUNCTION 0x81 #define EISA_INVALID_CONFIGURATION 0x82 #define EISA_EMPTY_SLOT 0x83 #define EISA_INVALID_BIOS_CALL 0x86 // // Defines Resource Options // #define IO_RESOURCE_PREFERRED 0x01 #define IO_RESOURCE_DEFAULT 0x02 #define IO_RESOURCE_ALTERNATIVE 0x08 // // This structure defines one type of resource requested by the driver // typedef struct _IO_RESOURCE_DESCRIPTOR { UCHAR Option; UCHAR Type; // use CM_RESOURCE_TYPE UCHAR ShareDisposition; // use CM_SHARE_DISPOSITION UCHAR Spare1; USHORT Flags; // use CM resource flag defines USHORT Spare2; // align union { struct { ULONG Length; ULONG Alignment; PHYSICAL_ADDRESS MinimumAddress; PHYSICAL_ADDRESS MaximumAddress; } Port; struct { ULONG Length; ULONG Alignment; PHYSICAL_ADDRESS MinimumAddress; PHYSICAL_ADDRESS MaximumAddress; } Memory; struct { ULONG MinimumVector; ULONG MaximumVector; } Interrupt; struct { ULONG MinimumChannel; ULONG MaximumChannel; } Dma; struct { ULONG Length; ULONG Alignment; PHYSICAL_ADDRESS MinimumAddress; PHYSICAL_ADDRESS MaximumAddress; } Generic; struct { ULONG Data[3]; } DevicePrivate; // // Bus Number information. // struct { ULONG Length; ULONG MinBusNumber; ULONG MaxBusNumber; ULONG Reserved; } BusNumber; struct { ULONG Priority; // use LCPRI_Xxx values in cfg.h ULONG Reserved1; ULONG Reserved2; } ConfigData; } u; } IO_RESOURCE_DESCRIPTOR, *PIO_RESOURCE_DESCRIPTOR; #endif /* _MINIPORT_ */