566 lines
18 KiB
C
566 lines
18 KiB
C
/***
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*trans.h - definitions for computing transcendentals
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*
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* Copyright (c) 1991-2001, Microsoft Corporation. All rights reserved.
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*
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*Purpose:
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* Define constants and macros that are used for computing
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* transcendentals. Some of the definitions are machine dependent.
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* Double is assumed to conform to the IEEE 754 std format.
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*
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*Revision History:
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* 08-14-91 GDP written
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* 10-29-91 GDP removed unused prototypes, added _frnd
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* 01-20-92 GDP significant changes -- IEEE exc. support
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* 03-27-92 GDP put IEEE definitions in fpieee.h
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* 03-31-92 GDP add internal constants for _ctrlfp, _statfp
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* 05-08-92 PLM added M68K switch
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* 05-18-92 XY added exception macro under M68K switch
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* 06-23-92 GDP added macro for negative zero
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* 09-06-92 GDP include cruntime.h, calling convention macros
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* 07-16-93 SRW ALPHA Merge
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* 11-17-93 GJF Merged in NT SDK version. Replaced MIPS with
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* _M_MRX000, _ALPHA_ with _M_ALPHA, deleted old M68K
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* stuff (obsolete).
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* 01-13-94 RDL Added #ifndef _LANGUAGE_ASSEMBLY for asm includes.
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* 01-25-94 GJF Merged in 01-13 change above from Roger Lanser (from
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* fp32 tree on \\orville\razzle).
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* 03-11-94 GJF Picked up latest changes from Dec (from fp32 tree
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* on \\orville\razzle for Alpha build).
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* 10-02-94 BWT PPC merge
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* 02-06-95 JWM Mac merge
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* 02-07-95 JWM powhlp() prototype restored to Intel version.
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* 10-07-97 RDL Added IA64.
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* 05-13-99 PML Remove _CRTAPI1
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* 05-17-99 PML Remove all Macintosh support.
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* 10-06-99 PML Add _W64 modifier to types which are 32 bits in Win32,
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* 64 bits in Win64.
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* 04-30-01 BWT AMD64 change from DaveC
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*
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*******************************************************************************/
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#ifndef _INC_TRANS
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef __assembler /* MIPS ONLY: Protect from assembler */
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#include <cruntime.h>
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/* Define __cdecl for non-Microsoft compilers */
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#if ( !defined(_MSC_VER) && !defined(__cdecl) )
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#define __cdecl
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#endif
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#if !defined(_W64)
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#if !defined(__midl) && (defined(_X86_) || defined(_M_IX86)) && _MSC_VER >= 1300
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#define _W64 __w64
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#else
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#define _W64
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#endif
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#endif
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#ifndef _INTPTR_T_DEFINED
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#ifdef _WIN64
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typedef __int64 intptr_t;
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#else
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typedef _W64 int intptr_t;
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#endif
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#define _INTPTR_T_DEFINED
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#endif
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#ifndef _UINTPTR_T_DEFINED
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#ifdef _WIN64
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typedef unsigned __int64 uintptr_t;
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#else
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typedef _W64 unsigned int uintptr_t;
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#endif
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#define _UINTPTR_T_DEFINED
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#endif
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#include <fpieee.h>
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#define D_BIASM1 0x3fe /* off by one to compensate for the implied bit */
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#ifdef B_END
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/* big endian */
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#define D_EXP(x) ((unsigned short *)&(x))
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#define D_HI(x) ((unsigned long *)&(x))
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#define D_LO(x) ((unsigned long *)&(x)+1)
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#else
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#define D_EXP(x) ((unsigned short *)&(x)+3)
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#define D_HI(x) ((unsigned long *)&(x)+1)
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#define D_LO(x) ((unsigned long *)&(x))
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#endif
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/* return the int representation of the exponent
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* if x = .f * 2^n, 0.5<=f<1, return n (unbiased)
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* e.g. INTEXP(3.0) == 2
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*/
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#define INTEXP(x) ((signed short)((*D_EXP(x) & 0x7ff0) >> 4) - D_BIASM1)
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/* check for infinity, NAN */
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#define D_ISINF(x) ((*D_HI(x) & 0x7fffffff) == 0x7ff00000 && *D_LO(x) == 0)
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#define IS_D_SPECIAL(x) ((*D_EXP(x) & 0x7ff0) == 0x7ff0)
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#define IS_D_NAN(x) (IS_D_SPECIAL(x) && !D_ISINF(x))
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#ifdef _M_MRX000
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#define IS_D_SNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff8)
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#define IS_D_QNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff0 && \
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(*D_HI(x) << 13 || *D_LO(x)))
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#else
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#define IS_D_QNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff8)
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#define IS_D_SNAN(x) ((*D_EXP(x) & 0x7ff8) == 0x7ff0 && \
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(*D_HI(x) << 13 || *D_LO(x)))
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#endif
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#define IS_D_DENORM(x) ((*D_EXP(x) & 0x7ff0) == 0 && \
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(*D_HI(x) << 12 || *D_LO(x)))
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#define IS_D_INF(x) (*D_HI(x) == 0x7ff00000 && *D_LO(x) == 0)
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#define IS_D_MINF(x) (*D_HI(x) == 0xfff00000 && *D_LO(x) == 0)
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#ifdef _M_MRX000
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#define D_IND_HI 0x7ff7ffff
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#define D_IND_LO 0xffffffff
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#else
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#define D_IND_HI 0xfff80000
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#define D_IND_LO 0x0
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#endif
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typedef union {
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long lng[2];
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double dbl;
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} _dbl;
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extern _dbl _d_inf;
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extern _dbl _d_ind;
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extern _dbl _d_max;
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extern _dbl _d_min;
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extern _dbl _d_mzero;
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#define D_INF (_d_inf.dbl)
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#define D_IND (_d_ind.dbl)
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#define D_MAX (_d_max.dbl)
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#define D_MIN (_d_min.dbl)
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#define D_MZERO (_d_mzero.dbl) /* minus zero */
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/* min and max exponents for normalized numbers in the
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* form: 0.xxxxx... * 2^exp (NOT 1.xxxx * 2^exp !)
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*/
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#define MAXEXP 1024
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#define MINEXP -1021
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#endif /* #ifndef __assembler */
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#if defined(_M_IX86)
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/* Control word for computation of transcendentals */
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#define ICW 0x133f
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#define IMCW 0xffff
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#define IMCW_EM 0x003f /* interrupt Exception Masks */
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#define IEM_INVALID 0x0001 /* invalid */
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#define IEM_DENORMAL 0x0002 /* denormal */
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#define IEM_ZERODIVIDE 0x0004 /* zero divide */
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#define IEM_OVERFLOW 0x0008 /* overflow */
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#define IEM_UNDERFLOW 0x0010 /* underflow */
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#define IEM_INEXACT 0x0020 /* inexact (precision) */
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#define IMCW_RC 0x0c00 /* Rounding Control */
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#define IRC_CHOP 0x0c00 /* chop */
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#define IRC_UP 0x0800 /* up */
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#define IRC_DOWN 0x0400 /* down */
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#define IRC_NEAR 0x0000 /* near */
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#define ISW_INVALID 0x0001 /* invalid */
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#define ISW_DENORMAL 0x0002 /* denormal */
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#define ISW_ZERODIVIDE 0x0004 /* zero divide */
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#define ISW_OVERFLOW 0x0008 /* overflow */
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#define ISW_UNDERFLOW 0x0010 /* underflow */
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#define ISW_INEXACT 0x0020 /* inexact (precision) */
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#define IMCW_PC 0x0300 /* Precision Control */
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#define IPC_24 0x0000 /* 24 bits */
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#define IPC_53 0x0200 /* 53 bits */
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#define IPC_64 0x0300 /* 64 bits */
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#define IMCW_IC 0x1000 /* Infinity Control */
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#define IIC_AFFINE 0x1000 /* affine */
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#define IIC_PROJECTIVE 0x0000 /* projective */
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#elif defined(_M_AMD64)
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/* Control word for computation of transcendentals */
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#define ICW (IMCW_EM | IRC_NEAR)
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#define ISW (ISW_INEXACT | ISW_UNDERFLOW | ISW_OVERFLOW | ISW_ZERODIVIDE | ISW_INVALID | ISW_DENORMAL)
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#define IMCW (0xffff ^ ISW)
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#define IMCW_EM 0x1f80 /* interrupt Exception Masks */
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#define IEM_INVALID 0x0080 /* invalid */
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#define IEM_DENORMAL 0x0100 /* denormal */
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#define IEM_ZERODIVIDE 0x0200 /* zero divide */
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#define IEM_OVERFLOW 0x0400 /* overflow */
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#define IEM_UNDERFLOW 0x0800 /* underflow */
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#define IEM_INEXACT 0x1000 /* inexact (precision) */
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#define IMCW_RC 0x6000 /* Rounding Control */
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#define IRC_CHOP 0x6000 /* chop */
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#define IRC_UP 0x4000 /* up */
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#define IRC_DOWN 0x2000 /* down */
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#define IRC_NEAR 0x0000 /* near */
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#define ISW_INVALID 0x0001 /* invalid */
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#define ISW_DENORMAL 0x0002 /* denormal */
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#define ISW_ZERODIVIDE 0x0004 /* zero divide */
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#define ISW_OVERFLOW 0x0008 /* overflow */
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#define ISW_UNDERFLOW 0x0010 /* underflow */
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#define ISW_INEXACT 0x0020 /* inexact (precision) */
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#elif defined(_M_IA64)
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/* Control word for computation of transcendentals */
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#define ICW (IMCW_EM | IRC_NEAR | IPC_64)
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#define ISW (ISW_INEXACT | ISW_UNDERFLOW | ISW_OVERFLOW | ISW_ZERODIVIDE | ISW_INVALID | ISW_DENORMAL)
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#define IMCW (0xffffffff ^ ISW)
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#define IMCW_EM 0x003f /* interrupt Exception Masks */
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#define IEM_INVALID 0x0001 /* invalid */
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#define IEM_DENORMAL 0x0002 /* denormal */
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#define IEM_ZERODIVIDE 0x0004 /* zero divide */
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#define IEM_OVERFLOW 0x0008 /* overflow */
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#define IEM_UNDERFLOW 0x0010 /* underflow */
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#define IEM_INEXACT 0x0020 /* inexact (precision) */
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#define IMCW_RC 0x0c00 /* Rounding Control */
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#define IRC_CHOP 0x0c00 /* chop */
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#define IRC_UP 0x0800 /* up */
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#define IRC_DOWN 0x0400 /* down */
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#define IRC_NEAR 0x0000 /* near */
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#define ISW_INVALID 0x02000 /* invalid */
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#define ISW_DENORMAL 0x04000 /* denormal */
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#define ISW_ZERODIVIDE 0x08000 /* zero divide */
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#define ISW_OVERFLOW 0x10000 /* overflow */
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#define ISW_UNDERFLOW 0x20000 /* underflow */
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#define ISW_INEXACT 0x40000 /* inexact (precision) */
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#define IMCW_PC 0x0300 /* Precision Control */
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#define IPC_24 0x0000 /* 24 bits */
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#define IPC_53 0x0200 /* 53 bits */
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#define IPC_64 0x0300 /* 64 bits */
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#elif defined(_M_MRX000)
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#define ICW 0x00000f80 /* Internal CW for transcendentals */
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#define IMCW 0xffffff83 /* Internal CW Mask */
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#define IMCW_EM 0x00000f80 /* interrupt Exception Masks */
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#define IEM_INVALID 0x00000800 /* invalid */
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#define IEM_ZERODIVIDE 0x00000400 /* zero divide */
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#define IEM_OVERFLOW 0x00000200 /* overflow */
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#define IEM_UNDERFLOW 0x00000100 /* underflow */
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#define IEM_INEXACT 0x00000080 /* inexact (precision) */
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#define IMCW_RC 0x00000003 /* Rounding Control */
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#define IRC_CHOP 0x00000001 /* chop */
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#define IRC_UP 0x00000002 /* up */
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#define IRC_DOWN 0x00000003 /* down */
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#define IRC_NEAR 0x00000000 /* near */
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#define ISW_INVALID (1<<6) /* invalid */
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#define ISW_ZERODIVIDE (1<<5) /* zero divide */
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#define ISW_OVERFLOW (1<<4) /* overflow */
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#define ISW_UNDERFLOW (1<<3) /* underflow */
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#define ISW_INEXACT (1<<2) /* inexact (precision) */
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#elif defined(_M_ALPHA)
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//
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// ICW is the Internal Control Word for transcendentals: all five exceptions
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// are masked and round to nearest mode is set. IMCW is the mask: all bits
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// are set, except for the ISW bits.
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//
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#define ICW (IEM_INEXACT | IEM_UNDERFLOW | IEM_OVERFLOW | IEM_ZERODIVIDE | IEM_INVALID | IRC_NEAR)
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#define ISW (ISW_INEXACT | ISW_UNDERFLOW | ISW_OVERFLOW | ISW_ZERODIVIDE | ISW_INVALID)
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#define IMCW (0xffffffff ^ ISW)
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//
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// The defines for the internal control word match the format of the Alpha
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// AXP software FPCR except for the rounding mode which is obtained from the
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// Alpha AXP hardware FPCR and shifted right 32 bits.
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//
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//
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// Internal Exception Mask bits.
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// Each bit _disables_ an exception (they are not _enable_ bits).
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//
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#define IMCW_EM 0x0000003e /* interrupt Exception Masks */
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#define IEM_INEXACT 0x00000020 /* inexact (precision) */
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#define IEM_UNDERFLOW 0x00000010 /* underflow */
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#define IEM_OVERFLOW 0x00000008 /* overflow */
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#define IEM_ZERODIVIDE 0x00000004 /* zero divide */
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#define IEM_INVALID 0x00000002 /* invalid */
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//
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// Internal Rounding Control values.
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//
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#define IMCW_RC (0x3 << 26) /* Rounding Control */
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#define IRC_CHOP (0x0 << 26) /* chop */
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#define IRC_DOWN (0x1 << 26) /* down */
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#define IRC_NEAR (0x2 << 26) /* near */
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#define IRC_UP (0x3 << 26) /* up */
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//
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// Internal Status Word bits.
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//
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#define ISW_INEXACT 0x00200000 /* inexact (precision) */
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#define ISW_UNDERFLOW 0x00100000 /* underflow */
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#define ISW_OVERFLOW 0x00080000 /* overflow */
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#define ISW_ZERODIVIDE 0x00040000 /* zero divide */
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#define ISW_INVALID 0x00020000 /* invalid */
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#elif defined(_M_PPC)
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#define IMCW_EM 0x000000f8 /* Exception Enable Mask */
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#define IEM_INVALID 0x00000080 /* invalid */
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#define IEM_OVERFLOW 0x00000040 /* overflow */
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#define IEM_UNDERFLOW 0x00000020 /* underflow */
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#define IEM_ZERODIVIDE 0x00000010 /* zero divide */
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#define IEM_INEXACT 0x00000008 /* inexact (precision) */
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#define IMCW_RC 0x00000003 /* Rounding Control Mask */
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#define IRC_NEAR 0x00000000 /* near */
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#define IRC_CHOP 0x00000001 /* chop */
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#define IRC_UP 0x00000002 /* up */
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#define IRC_DOWN 0x00000003 /* down */
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#define IMCW_SW 0x3E000000 /* Status Mask */
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#define ISW_INVALID 0x20000000 /* invalid summary */
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#define ISW_OVERFLOW 0x10000000 /* overflow */
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#define ISW_UNDERFLOW 0x08000000 /* underflow */
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#define ISW_ZERODIVIDE 0x04000000 /* zero divide */
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#define ISW_INEXACT 0x02000000 /* inexact (precision) */
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#define IMCW_VX 0x01F80700 /* Invalid Cause Mask */
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#define IVX_SNAN 0x01000000 /* SNaN */
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#define IVX_ISI 0x00800000 /* infinity - infinity */
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#define IVX_IDI 0x00400000 /* infinity / infinity */
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#define IVX_ZDZ 0x00200000 /* zero / zero */
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#define IVX_IMZ 0x00100000 /* infinity * zero */
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#define IVX_VC 0x00080000 /* inv flpt compare */
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#define IVX_SOFT 0x00000400 /* software request */
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#define IVX_SQRT 0x00000200 /* sqrt of negative */
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#define IVX_CVI 0x00000100 /* inv integer convert */
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/* Internal CW for transcendentals */
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#define ICW (IMCW_EM)
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/* Internal CW Mask (non-status bits) */
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#define IMCW (0xffffffff & (~(IMCW_SW|IMCW_VX)))
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#endif
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#ifndef __assembler /* MIPS ONLY: Protect from assembler */
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#define RETURN(fpcw,result) return _rstorfp(fpcw),(result)
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#define RETURN_INEXACT1(op,arg1,res,cw) \
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if (cw & IEM_INEXACT) { \
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_rstorfp(cw); \
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return res; \
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} \
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else { \
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return _except1(FP_P, op, arg1, res, cw); \
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}
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#define RETURN_INEXACT2(op,arg1,arg2,res,cw) \
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if (cw & IEM_INEXACT) { \
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_rstorfp(cw); \
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return res; \
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} \
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else { \
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return _except2(FP_P, op, arg1, arg2, res, cw); \
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}
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#ifdef _M_ALPHA
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//
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// Since fp32 is not compiled in IEEE exception mode perform Alpha NaN
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// propagation in software to avoid hardware/kernel trap involvement.
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//
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extern double _nan2qnan(double);
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#define _d_snan2(x,y) _nan2qnan(y)
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#define _s2qnan(x) _nan2qnan(x)
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#else
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//handle NaN propagation
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#define _d_snan2(x,y) ((x)+(y))
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#define _s2qnan(x) ((x)+1.0)
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#endif
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#define _maskfp() _ctrlfp(ICW, IMCW)
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#ifdef _M_ALPHA
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#define _rstorfp(cw) 0
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#else
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#define _rstorfp(cw) _ctrlfp(cw, IMCW)
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#endif
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#define ABS(x) ((x)<0 ? -(x) : (x) )
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int _d_inttype(double);
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#endif /* #ifndef __assembler */
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#define _D_NOINT 0
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#define _D_ODD 1
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#define _D_EVEN 2
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// IEEE exceptions
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#define FP_O 0x01
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#define FP_U 0x02
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#define FP_Z 0x04
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#define FP_I 0x08
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#define FP_P 0x10
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// An extra flag for matherr support
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// Set together with FP_I from trig functions when the argument is too large
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#define FP_TLOSS 0x20
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#ifndef __assembler /* MIPS ONLY: Protect from assembler */
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#ifdef B_END
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#define SET_DBL(msw, lsw) msw, lsw
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#else
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#define SET_DBL(msw, lsw) lsw, msw
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#endif
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#endif /* #ifndef __assembler */
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// special types
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#define T_PINF 1
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#define T_NINF 2
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#define T_QNAN 3
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#define T_SNAN 4
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// exponent adjustment for IEEE overflow/underflow exceptions
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// used before passing the result to the trap handler
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#define IEEE_ADJUST 1536
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// QNAN values
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#define INT_NAN (~0)
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#define QNAN_SQRT D_IND
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#define QNAN_LOG D_IND
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#define QNAN_LOG10 D_IND
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#define QNAN_POW D_IND
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#define QNAN_SINH D_IND
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#define QNAN_COSH D_IND
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#define QNAN_TANH D_IND
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#define QNAN_SIN1 D_IND
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#define QNAN_SIN2 D_IND
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#define QNAN_COS1 D_IND
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#define QNAN_COS2 D_IND
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#define QNAN_TAN1 D_IND
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#define QNAN_TAN2 D_IND
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#define QNAN_ACOS D_IND
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#define QNAN_ASIN D_IND
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#define QNAN_ATAN2 D_IND
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#define QNAN_CEIL D_IND
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#define QNAN_FLOOR D_IND
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#define QNAN_MODF D_IND
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#define QNAN_LDEXP D_IND
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#define QNAN_FMOD D_IND
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#define QNAN_FREXP D_IND
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/*
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* Function prototypes
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*/
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#ifndef __assembler /* MIPS ONLY: Protect from assembler */
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double _set_exp(double x, int exp);
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double _set_bexp(double x, int exp);
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double _add_exp(double x, int exp);
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double _frnd(double);
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double _fsqrt(double);
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double _except1(int flags, int opcode, double arg, double res, uintptr_t cw);
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double _except2(int flags, int opcode, double arg1, double arg2, double res, uintptr_t cw);
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int _sptype(double);
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int _get_exp(double);
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double _decomp(double, int *);
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int _powhlp(double x, double y, double * result);
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extern unsigned int _fpstatus;
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double _frnd(double);
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double _exphlp(double, int *);
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double _handle_qnan1(unsigned int op, double arg, uintptr_t cw);
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double _handle_qnan2(unsigned int op,double arg1,double arg2,uintptr_t cw);
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unsigned int _clhwfp(void);
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unsigned int _setfpcw(uintptr_t);
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int _errcode(unsigned int flags);
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void _set_errno(int matherrtype);
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int _handle_exc(unsigned int flags, double * presult, uintptr_t cw);
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uintptr_t _clrfp(void);
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uintptr_t _ctrlfp(uintptr_t,uintptr_t);
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uintptr_t _statfp(void);
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void _set_statfp(uintptr_t);
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#endif /* #ifndef __assembler */
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#ifdef __cplusplus
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}
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#endif
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#define _INC_TRANS
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#endif /* _INC_TRANS */
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