194 lines
4.5 KiB
C
194 lines
4.5 KiB
C
#ifndef _PCI22_H
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#define _PCI22_H
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/*++
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Copyright (c) 1999 Intel Corporation
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Module Name:
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pci22.h
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Abstract:
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Support for PCI 2.2 standard.
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Revision History
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--*/
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#ifdef SOFT_SDV
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#define PCI_MAX_BUS 1
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#else
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#define PCI_MAX_BUS 255
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#endif
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#define PCI_MAX_DEVICE 31
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#define PCI_MAX_FUNC 7
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/*
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* Command
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*/
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#define PCI_VGA_PALETTE_SNOOP_DISABLED 0x20
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#pragma pack(1)
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typedef struct {
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT16 Command;
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UINT16 Status;
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UINT8 RevisionID;
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UINT8 ClassCode[3];
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UINT8 CacheLineSize;
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UINT8 LaytencyTimer;
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UINT8 HeaderType;
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UINT8 BIST;
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} PCI_DEVICE_INDEPENDENT_REGION;
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typedef struct {
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UINT32 Bar[6];
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UINT32 CISPtr;
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UINT16 SubsystemVendorID;
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UINT16 SubsystemID;
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UINT32 ExpansionRomBar;
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UINT32 Reserved[2];
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UINT8 InterruptLine;
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UINT8 InterruptPin;
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UINT8 MinGnt;
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UINT8 MaxLat;
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} PCI_DEVICE_HEADER_TYPE_REGION;
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typedef struct {
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PCI_DEVICE_INDEPENDENT_REGION Hdr;
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PCI_DEVICE_HEADER_TYPE_REGION Device;
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} PCI_TYPE00;
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typedef struct {
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UINT32 Bar[2];
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UINT8 PrimaryBus;
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UINT8 SecondaryBus;
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UINT8 SubordinateBus;
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UINT8 SecondaryLatencyTimer;
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UINT8 IoBase;
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UINT8 IoLimit;
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UINT16 SecondaryStatus;
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UINT16 MemoryBase;
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UINT16 MemoryLimit;
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UINT16 PrefetchableMemoryBase;
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UINT16 PrefetchableMemoryLimit;
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UINT32 PrefetchableBaseUpper32;
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UINT32 PrefetchableLimitUpper32;
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UINT16 IoBaseUpper16;
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UINT16 IoLimitUpper16;
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UINT32 Reserved;
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UINT32 ExpansionRomBAR;
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UINT8 InterruptLine;
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UINT8 InterruptPin;
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UINT16 BridgeControl;
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} PCI_BRIDGE_CONTROL_REGISTER;
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#define PCI_CLASS_DISPLAY_CTRL 0x03
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#define PCI_CLASS_VGA 0x00
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#define PCI_CLASS_BRIDGE 0x06
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#define PCI_CLASS_ISA 0x01
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#define PCI_CLASS_ISA_POSITIVE_DECODE 0x80
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#define PCI_CLASS_NETWORK 0x02
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#define PCI_CLASS_ETHERNET 0x00
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#define HEADER_TYPE_DEVICE 0x00
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#define HEADER_TYPE_PCI_TO_PCI_BRIDGE 0x01
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#define HEADER_TYPE_MULTI_FUNCTION 0x80
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#define HEADER_LAYOUT_CODE 0x7f
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#define IS_PCI_BRIDGE(_p) ((((_p)->Hdr.HeaderType) & HEADER_LAYOUT_CODE) == HEADER_TYPE_PCI_TO_PCI_BRIDGE)
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#define IS_PCI_MULTI_FUNC(_p) (((_p)->Hdr.HeaderType) & HEADER_TYPE_MULTI_FUNCTION)
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typedef struct {
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PCI_DEVICE_INDEPENDENT_REGION Hdr;
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PCI_BRIDGE_CONTROL_REGISTER Bridge;
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} PCI_TYPE01;
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typedef struct {
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UINT8 Register;
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UINT8 Function;
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UINT8 Device;
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UINT8 Bus;
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UINT8 Reserved[4];
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} DEFIO_PCI_ADDR;
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typedef struct {
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UINT32 Reg : 8;
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UINT32 Func : 3;
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UINT32 Dev : 5;
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UINT32 Bus : 8;
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UINT32 Reserved: 7;
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UINT32 Enable : 1;
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} PCI_CONFIG_ACCESS_CF8;
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#pragma pack()
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#define EFI_ROOT_BRIDGE_LIST 'eprb'
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typedef struct {
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UINTN Signature;
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UINT16 BridgeNumber;
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UINT16 PrimaryBus;
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UINT16 SubordinateBus;
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EFI_DEVICE_PATH *DevicePath;
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LIST_ENTRY Link;
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} PCI_ROOT_BRIDGE_ENTRY;
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#define PCI_EXPANSION_ROM_HEADER_SIGNATURE 0xaa55
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#define EFI_PCI_EXPANSION_ROM_HEADER_EFISIGNATURE 0x0EF1
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#define PCI_DATA_STRUCTURE_SIGNATURE EFI_SIGNATURE_32('P','C','I','R')
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#pragma pack(1)
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typedef struct {
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UINT16 Signature; /* 0xaa55 */
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UINT8 Reserved[0x16];
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UINT16 PcirOffset;
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} PCI_EXPANSION_ROM_HEADER;
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typedef struct {
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UINT16 Signature; /* 0xaa55 */
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UINT16 InitializationSize;
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UINT16 EfiSignature; /* 0x0EF1 */
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UINT16 EfiSubsystem;
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UINT16 EfiMachineType;
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UINT8 Reserved[0x0A];
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UINT16 EfiImageHeaderOffset;
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UINT16 PcirOffset;
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} EFI_PCI_EXPANSION_ROM_HEADER;
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typedef struct {
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UINT32 Signature; /* "PCIR" */
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UINT16 VendorId;
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UINT16 DeviceId;
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UINT16 Reserved0;
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UINT16 Length;
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UINT8 Revision;
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UINT8 ClassCode[3];
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UINT16 ImageLength;
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UINT16 CodeRevision;
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UINT8 CodeType;
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UINT8 Indicator;
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UINT16 Reserved1;
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} PCI_DATA_STRUCTURE;
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#pragma pack()
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#endif
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