838 lines
25 KiB
NASM
838 lines
25 KiB
NASM
title "Irql Processing"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; spirql.asm
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;
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; Abstract:
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;
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; SystemPro IRQL
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;
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; This module implements the code necessary to raise and lower i386
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; Irql and dispatch software interrupts with the 8259 PIC.
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;
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; Author:
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;
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; Shie-Lin Tzong (shielint) 8-Jan-1990
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; John Vert (jvert) 27-Nov-1991
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; Moved from kernel into HAL
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc ; calling convention macros
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include i386\ix8259.inc
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include i386\kimacro.inc
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include i386\spmp.inc
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.list
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EXTRNP _KeBugCheck,1,IMPORT
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extrn _HalpApcInterrupt:near
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extrn _HalpDispatchInterrupt:near
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extrn _HalpSWNonPrimaryClockTick:near
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extrn _HalpApcInterrupt2ndEntry:NEAR
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extrn _HalpDispatchInterrupt2ndEntry:NEAR
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extrn _HalpSWNonPrimaryClockTick2ndEntry:NEAR
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extrn _KiUnexpectedInterrupt:near
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;
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; Initialization control words equates for the PICs
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;
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ICW1_ICW4_NEEDED equ 01H
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ICW1_CASCADE equ 00H
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ICW1_INTERVAL8 equ 00H
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ICW1_LEVEL_TRIG equ 08H
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ICW1_EDGE_TRIG equ 00H
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ICW1_ICW equ 10H
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ICW4_8086_MODE equ 001H
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ICW4_NORM_EOI equ 000H
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ICW4_NON_BUF_MODE equ 000H
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ICW4_SPEC_FULLY_NESTED equ 010H
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ICW4_NOT_SPEC_FULLY_NESTED equ 000H
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OCW2_NON_SPECIFIC_EOI equ 020H
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OCW2_SPECIFIC_EOI equ 060H
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OCW2_SET_PRIORITY equ 0c0H
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PIC_SLAVE_IRQ equ 2
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PIC1_BASE equ 30H
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PIC2_BASE equ 38H
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;
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; Interrupt flag bit maks for EFLAGS
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;
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EFLAGS_IF equ 200H
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EFLAGS_SHIFT equ 9
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;
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; Define the constants of Edge level Pic control.
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;
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; Background: Compaq Belize systems have an 8259 per processor and
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; their own private Edge Level control registers (4d0,4d1).
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;
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EDGELEVEL_CONTROL_1 equ 4D0H
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EDGELEVEL_CONTROL_2 equ 4D1H
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;
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_TEXT SEGMENT DWORD PUBLIC 'DATA'
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;
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; PICsInitializationString - Master PIC initialization command string
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;
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PICsInitializationString dw PIC1_PORT0
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;
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; Master PIC initialization command
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;
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db ICW1_ICW + ICW1_EDGE_TRIG + ICW1_INTERVAL8 +\
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ICW1_CASCADE + ICW1_ICW4_NEEDED
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db PIC1_BASE
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db 1 SHL PIC_SLAVE_IRQ
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db ICW4_NOT_SPEC_FULLY_NESTED + \
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ICW4_NON_BUF_MODE + \
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ICW4_NORM_EOI + \
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ICW4_8086_MODE
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;
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; Slave PIC initialization command strings
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;
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dw PIC2_PORT0
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db ICW1_ICW + ICW1_EDGE_TRIG + ICW1_INTERVAL8 +\
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ICW1_CASCADE + ICW1_ICW4_NEEDED
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db PIC2_BASE
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db PIC_SLAVE_IRQ
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db ICW4_NOT_SPEC_FULLY_NESTED + \
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ICW4_NON_BUF_MODE + \
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ICW4_NORM_EOI + \
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ICW4_8086_MODE
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dw 0 ; end of string
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PS2PICsInitializationString dw PIC1_PORT0
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;
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; Master PIC initialization command
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;
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db ICW1_ICW + ICW1_LEVEL_TRIG + ICW1_INTERVAL8 +\
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ICW1_CASCADE + ICW1_ICW4_NEEDED
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db PIC1_BASE
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db 1 SHL PIC_SLAVE_IRQ
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db ICW4_NOT_SPEC_FULLY_NESTED + \
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ICW4_NON_BUF_MODE + \
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ICW4_NORM_EOI + \
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ICW4_8086_MODE
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;
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; Slave PIC initialization command strings
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;
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dw PIC2_PORT0
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db ICW1_ICW + ICW1_LEVEL_TRIG + ICW1_INTERVAL8 +\
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ICW1_CASCADE + ICW1_ICW4_NEEDED
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db PIC2_BASE
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db PIC_SLAVE_IRQ
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db ICW4_NOT_SPEC_FULLY_NESTED + \
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ICW4_NON_BUF_MODE + \
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ICW4_NORM_EOI + \
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ICW4_8086_MODE
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dw 0 ; end of string
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align 4
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public KiI8259MaskTable
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KiI8259MaskTable label dword
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dd 00000000000000000000000000000000B ; irql 0
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dd 00000000000000000000000000000000B ; irql 1
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dd 00000000000000000000000000000000B ; irql 2
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dd 00000000000000000000000000000000B ; irql 3
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dd 00000000000000000000000000000000B ; irql 4
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dd 11111111110000000000000000000000B ; irql 5
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dd 11111111111000000000000000000000B ; irql 6
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dd 11111111111100000000000000000000B ; irql 7
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dd 11111111111110000000000000000000B ; irql 8
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dd 11111111111111000000000000000000B ; irql 9
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dd 11111111111111100000000000000000B ; irql 10
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dd 11111111111111110000000000000000B ; irql 11
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dd 11111111111111111000000000000000B ; irql 12
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dd 11111111111111111100000000000000B ; irql 13
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dd 11111111111111111100000000000000B ; irql 14
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dd 11111111111111111101000000000000B ; irql 15
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dd 11111111111111111101100000000000B ; irql 16
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dd 11111111111111111101110000000000B ; irql 17
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dd 11111111111111111101111000000000B ; irql 18
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dd 11111111111111111101111000000000B ; irql 19
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dd 11111111111111111101111010000000B ; irql 20
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dd 11111111111111111101111011000000B ; irql 21
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dd 11111111111111111101111011100000B ; irql 22
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dd 11111111111111111101111011110000B ; irql 23
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dd 11111111111111111101111011111000B ; irql 24
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dd 11111111111111111101111011111000B ; irql 25
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dd 11111111111111111101111011111010B ; irql 26
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dd 11111111111111111101111111111010B ; irql 27
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dd 11111111111111111101111111111011B ; irql 28
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dd 11111111111111111111111111111011B ; irql 29
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dd 11111111111111111111111111111011B ; irql 30
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dd 11111111111111111111111111111011B ; irql 31
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; |
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; 32109876543210
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; |
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; + - Raise SystemPros IPI vector (13)
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; to IPI_LEVEL
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align 4
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;
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; The following tables define the addresses of software interrupt routers
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;
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;
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; Use this table if there is NO machine state frame on stack already
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;
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public SWInterruptHandlerTable
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SWInterruptHandlerTable label dword
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dd offset FLAT:_KiUnexpectedInterrupt ; irql 0
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dd offset FLAT:_HalpApcInterrupt ; irql 1
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dd offset FLAT:_HalpDispatchInterrupt ; irql 2
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dd offset FLAT:_KiUnexpectedInterrupt ; irql 3
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dd offset FLAT:_HalpSWNonPrimaryClockTick ; irql 4
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;
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; Use this table if there is a machine state frame on stack already
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;
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public SWInterruptHandlerTable2
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SWInterruptHandlerTable2 label dword
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dd offset FLAT:_KiUnexpectedInterrupt ; irql 0
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dd offset FLAT:_HalpApcInterrupt2ndEntry ; irql 1
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dd offset FLAT:_HalpDispatchInterrupt2ndEntry ; irql 2
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dd offset FLAT:_KiUnexpectedInterrupt ; irql 3
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dd offset FLAT:_HalpSWNonPrimaryClockTick2ndEntry ; irql 4
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;
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; The following table picks up the highest pending software irq level
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; from software irr
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;
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public SWInterruptLookUpTable
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SWInterruptLookUpTable label byte
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db 0 ; SWIRR=0, so highest pending SW irql= 0
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db 0 ; SWIRR=1, so highest pending SW irql= 0
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db 1 ; SWIRR=2, so highest pending SW irql= 1
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db 1 ; SWIRR=3, so highest pending SW irql= 1
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db 2 ; SWIRR=4, so highest pending SW irql= 2
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db 2 ; SWIRR=5, so highest pending SW irql= 2
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db 2 ; SWIRR=6, so highest pending SW irql= 2
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db 2 ; SWIRR=7, so highest pending SW irql= 2
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db 3 ; SWIRR=8, so highest pending SW irql= 3
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db 3 ; SWIRR=9, so highest pending SW irql= 3
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db 3 ; SWIRR=A, so highest pending SW irql= 3
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db 3 ; SWIRR=B, so highest pending SW irql= 3
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db 3 ; SWIRR=C, so highest pending SW irql= 3
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db 3 ; SWIRR=D, so highest pending SW irql= 3
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db 3 ; SWIRR=E, so highest pending SW irql= 3
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db 3 ; SWIRR=F, so highest pending SW irql= 3
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db 4 ; SWIRR=10, so highest pending SW irql= 4
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db 4 ; SWIRR=11, so highest pending SW irql= 4
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db 4 ; SWIRR=12, so highest pending SW irql= 4
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db 4 ; SWIRR=13, so highest pending SW irql= 4
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db 4 ; SWIRR=14, so highest pending SW irql= 4
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db 4 ; SWIRR=15, so highest pending SW irql= 4
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db 4 ; SWIRR=16, so highest pending SW irql= 4
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db 4 ; SWIRR=17, so highest pending SW irql= 4
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db 4 ; SWIRR=18, so highest pending SW irql= 4
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db 4 ; SWIRR=19, so highest pending SW irql= 4
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db 4 ; SWIRR=1A, so highest pending SW irql= 4
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db 4 ; SWIRR=1B, so highest pending SW irql= 4
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db 4 ; SWIRR=1C, so highest pending SW irql= 4
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db 4 ; SWIRR=1D, so highest pending SW irql= 4
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db 4 ; SWIRR=1E, so highest pending SW irql= 4
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db 4 ; SWIRR=1F, so highest pending SW irql= 4
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_TEXT ends
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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;
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; Only P0 has its Edge Level masks on port 4d0 and port 4d1 setup
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; correctly. We hold the P0 values here for the other processors.
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;
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align 4
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public _SpP0EdgeLevelValue
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_SpP0EdgeLevelValue dw 0
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_DATA ENDS
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:FLAT, FS:NOTHING, GS:NOTHING
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PAGE
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SUBTTL "Raise Irql"
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;++
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;
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; KIRQL
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; FASTCALL
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; KfRaiseIrql (
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; IN KIRQL NewIrql
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; )
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;
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; Routine Description:
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;
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; This routine is used to raise IRQL to the specified value.
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; Also, a mask will be used to mask off all the lower lever 8259
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; interrupts.
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;
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; Arguments:
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;
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; (cl) = NewIrql - the new irql to be raised to
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;
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; Return Value:
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;
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; OldIrql - the addr of a variable which old irql should be stored
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;
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;--
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cPublicFastCall KfRaiseIrql,1
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cPublicFpo 0,0
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xor eax, eax ; avoid partial stall
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mov al, fs:PcIrql ; get current irql
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pushfd ; save caller's eflags
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cPublicFpo 0,1
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if DBG
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cmp al,cl ; old > new?
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jbe short Kri99 ; no, we're OK
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movzx eax, al
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movzx ecx, cl
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push ecx ; put new irql where we can find it
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push eax ; put old irql where we can find it
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mov byte ptr fs:PcIrql,0 ; avoid recursive error
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stdCall _KeBugCheck, <IRQL_NOT_GREATER_OR_EQUAL>
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align 4
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Kri99:
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endif
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cli ; disable interrupt
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cmp byte ptr fs:PcHal.PcrPic, 0
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je PxRaiseIrql ; dispatch according to processor
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@@:
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; P0RaiseIrql
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cmp cl,DISPATCH_LEVEL ; software level?
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mov fs:PcIrql, cl ; set the new irql
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jbe short kri10 ; go skip setting 8259 hardware
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movzx ecx, cl
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mov dl, al ; Save OldIrql
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mov eax, KiI8259MaskTable[ecx*4]; get pic masks for the new irql
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or eax, fs:PcIDR ; mask irqs which are disabled
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SET_8259_MASK ; set 8259 masks
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mov al, dl ; Restore OldIrql
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kri10: popfd ; restore flags (including interrupts)
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fstRET KfRaiseIrql
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align 4
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PxRaiseIrql:
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;
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; Even though SystemPro P2 cannot touch 8259 ports, we still need to
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; make sure interrupts are off when requested to raise to IPI_LEVEL or
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; above.
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;
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cmp cl, IPI_LEVEL ; If raise to IPI_LEVEL?
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jb short @f ; if ne, don't edit flag
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and dword ptr [esp], NOT EFLAGS_IF ; clear IF bit in return EFLAGS
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align 4
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@@:
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mov fs:PcIrql, cl ; set the new irql
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popfd ; restore flags (including interrupts)
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fstRET KfRaiseIrql
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fstENDP KfRaiseIrql
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;++
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;
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; VOID
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; KIRQL
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; KeRaiseIrqlToDpcLevel (
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; )
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;
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; Routine Description:
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;
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; This routine is used to raise IRQL to DPC level.
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; The APIC TPR is used to block all lower-priority HW interrupts.
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;
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; Arguments:
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;
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; Return Value:
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;
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; OldIrql - the addr of a variable which old irql should be stored
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;
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;--
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cPublicProc _KeRaiseIrqlToDpcLevel,0
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cPublicFpo 0, 0
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mov ecx, DISPATCH_LEVEL
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jmp @KfRaiseIrql
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stdENDP _KeRaiseIrqlToDpcLevel
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;++
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;
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; VOID
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; KIRQL
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; KeRaiseIrqlToSynchLevel (
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; )
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;
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; Routine Description:
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;
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; This routine is used to raise IRQL to SYNC level.
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; The APIC TPR is used to block all lower-priority HW interrupts.
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;
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; Arguments:
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;
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; Return Value:
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;
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; OldIrql - the addr of a variable which old irql should be stored
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;
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;--
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cPublicProc _KeRaiseIrqlToSynchLevel,0
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mov ecx, SYNCH_LEVEL
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jmp @KfRaiseIrql
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stdENDP _KeRaiseIrqlToSynchLevel
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page ,132
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subttl "Lower irql"
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;++
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;
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; VOID
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; FASTCALL
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; KfLowerIrql (
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; IN KIRQL NewIrql
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; )
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;
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; Routine Description:
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;
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; This routine is used to lower IRQL to the specified value.
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; The IRQL and PIRQL will be updated accordingly. Also, this
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; routine checks to see if any software interrupt should be
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; generated. The following condition will cause software
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; interrupt to be simulated:
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; any software interrupt which has higher priority than
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; current IRQL's is pending.
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;
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; NOTE: This routine simulates software interrupt as long as
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; any pending SW interrupt level is higher than the current
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; IRQL, even when interrupts are disabled.
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;
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; Arguments:
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;
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; (cl) = NewIrql - the new irql to be set.
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;
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; Return Value:
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;
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; None.
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;
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;--
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cPublicFastCall KfLowerIrql,1
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pushfd ; save caller's eflags
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if DBG
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cmp cl,fs:PcIrql
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jbe short Kli99
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movzx ecx, cl
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push ecx ; new irql for debugging
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push fs:PcIrql ; old irql for debugging
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mov byte ptr fs:PcIrql,HIGH_LEVEL ; avoid recursive error
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stdCall _KeBugCheck, <IRQL_NOT_LESS_OR_EQUAL>
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align 4
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Kli99:
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endif
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cli
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cmp byte ptr fs:PcHal.PcrPic, 0
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je PxLowerIrql ; dispatch according to processor
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@@:
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; P1LowerIrql:
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cmp byte ptr fs:PcIrql,DISPATCH_LEVEL ; Software level?
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jbe short kli02 ; yes, go skip setting 8259 hw
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movzx ecx, cl
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mov eax, KiI8259MaskTable[ecx*4]; get pic masks for the new irql
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or eax, fs:PcIDR ; mask irqs which are disabled
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SET_8259_MASK ; set 8259 masks
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kli02: mov fs:PcIrql, cl ; set the new irql
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mov eax, fs:PcIRR ; get SW interrupt request register
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mov al, SWInterruptLookUpTable[eax] ; get the highest pending
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; software interrupt level
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cmp al, cl ; Is highest SW int level > irql?
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ja short Kli10 ; yes, go simulate interrupt
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popfd ; restore flags, including ints
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fstRET KfLowerIrql
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; When we come to Kli10, (eax) = soft interrupt index
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align 4
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Kli10:
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call SWInterruptHandlerTable[eax*4] ; SIMULATE INTERRUPT
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; to the appropriate handler
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popfd
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fstRET KfLowerIrql
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PxLowerIrql:
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cmp cl, IPI_LEVEL ; If lower to IPI_LEVEL?
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; cy = yes
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sbb edx, edx ; edx = 0 (nc), -1 (cy)
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and edx, EFLAGS_IF
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or dword ptr [esp], edx ; set EFLAG_IF if irql<IPI_LEVEL
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mov fs:PcIrql, cl ; set the new irql
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mov eax, fs:PcIRR ; get SW interrupt request register
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mov al, SWInterruptLookUpTable[eax] ; get the highest pending
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; software interrupt level
|
|
cmp al, cl ; Is highest SW int level > irql?
|
|
ja short Kli10 ; yes, go simulate interrupt
|
|
|
|
popfd ; restore flags, including ints
|
|
fstRET KfLowerIrql
|
|
|
|
fstENDP KfLowerIrql
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpEndSystemInterrupt
|
|
; IN KIRQL NewIrql,
|
|
; IN ULONG Vector
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine is used to lower IRQL to the specified value.
|
|
; The IRQL and PIRQL will be updated accordingly. Also, this
|
|
; routine checks to see if any software interrupt should be
|
|
; generated. The following condition will cause software
|
|
; interrupt to be simulated:
|
|
; any software interrupt which has higher priority than
|
|
; current IRQL's is pending.
|
|
;
|
|
; NOTE: This routine simulates software interrupt as long as
|
|
; any pending SW interrupt level is higher than the current
|
|
; IRQL, even when interrupts are disabled.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; NewIrql - the new irql to be set.
|
|
;
|
|
; Vector - Vector number of the interrupt
|
|
;
|
|
; Note that esp+8 is the beginning of interrupt/trap frame and upon
|
|
; entering to this routine the interrupts are off.
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None.
|
|
;
|
|
;--
|
|
|
|
HeiNewIrql equ [esp + 4]
|
|
|
|
cPublicProc _HalEndSystemInterrupt ,2
|
|
|
|
xor ecx, ecx
|
|
mov cl, byte ptr HeiNewIrql ; get new irql value
|
|
|
|
cmp byte ptr fs:PcHal.PcrPic, 0
|
|
je short Hei02
|
|
|
|
; P1LowerIrql:
|
|
cmp byte ptr fs:PcIrql, DISPATCH_LEVEL ; Software level?
|
|
jbe short Hei02 ; yes, go skip setting 8259 hw
|
|
|
|
mov eax, KiI8259MaskTable[ecx*4]; get pic masks for the new irql
|
|
or eax, fs:PcIDR ; mask irqs which are disabled
|
|
SET_8259_MASK ; set 8259 masks
|
|
|
|
;
|
|
; Unlike KeLowerIrql, we don't check if the the irql is lowered to
|
|
; below IPI level and enable interrupt for second processor. This is because
|
|
; the correct interrupt flag is already stored in the TsEflags of Trap frame.
|
|
;
|
|
|
|
align 4
|
|
Hei02: mov fs:PcIrql, cl ; set the new irql
|
|
mov eax, fs:PcIRR ; get SW interrupt request register
|
|
mov al, SWInterruptLookUpTable[eax] ; get the highest pending
|
|
; software interrupt level
|
|
cmp al, cl ; Is highest SW int level > irql?
|
|
ja short Hei10 ; yes, go simulate interrupt
|
|
|
|
stdRET _HalEndSystemInterrupt ; cRetURN
|
|
|
|
; When we come to Kli10, (eax) = soft interrupt index
|
|
align 4
|
|
Hei10: add esp, 12
|
|
jmp SWInterruptHandlerTable2[eax*4] ; SIMULATE INTERRUPT
|
|
; to the appropriate handler
|
|
stdENDP _HalEndSystemInterrupt
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpEndSoftwareInterrupt
|
|
; IN KIRQL NewIrql,
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine is used to lower IRQL from software interrupt
|
|
; level to the specified value.
|
|
; The IRQL and PIRQL will be updated accordingly. Also, this
|
|
; routine checks to see if any software interrupt should be
|
|
; generated. The following condition will cause software
|
|
; interrupt to be simulated:
|
|
; any software interrupt which has higher priority than
|
|
; current IRQL's is pending.
|
|
;
|
|
; NOTE: This routine simulates software interrupt as long as
|
|
; any pending SW interrupt level is higher than the current
|
|
; IRQL, even when interrupts are disabled.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; NewIrql - the new irql to be set.
|
|
;
|
|
; Note that esp+8 is the beginning of interrupt/trap frame and upon
|
|
; entering to this routine the interrupts are off.
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None.
|
|
;
|
|
;--
|
|
|
|
HesNewIrql equ [esp + 4]
|
|
|
|
cPublicProc _HalpEndSoftwareInterrupt,1
|
|
cPublicFpo 1,0
|
|
mov ecx, [esp+4]
|
|
fstCall KfLowerIrql
|
|
cli
|
|
stdRet _HalpEndSoftwareInterrupt
|
|
stdENDP _HalpEndSoftwareInterrupt
|
|
|
|
page ,132
|
|
subttl "Get current irql"
|
|
|
|
;++
|
|
;
|
|
; KIRQL
|
|
; KeGetCurrentIrql (VOID)
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine returns to current IRQL.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None.
|
|
;
|
|
; Return Value:
|
|
;
|
|
; The current IRQL.
|
|
;
|
|
;--
|
|
|
|
cPublicProc _KeGetCurrentIrql ,0
|
|
movzx eax,byte ptr fs:PcIrql ; Current irql is in the PCR
|
|
stdRET _KeGetCurrentIrql
|
|
stdENDP _KeGetCurrentIrql
|
|
|
|
|
|
;++
|
|
;
|
|
; KIRQL
|
|
; HalpDisableAllInterrupts (VOID)
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine is called during a system crash. The hal needs all
|
|
; interrupts disabled.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None.
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None - all interrupts are masked off
|
|
;
|
|
;--
|
|
|
|
cPublicProc _HalpDisableAllInterrupts,0
|
|
|
|
;
|
|
; Raising to HIGH_LEVEL disables interrupts for the SystemPro HAL
|
|
;
|
|
|
|
mov ecx, HIGH_LEVEL
|
|
fstCall KfRaiseIrql
|
|
stdRET _HalpDisableAllInterrupts
|
|
|
|
stdENDP _HalpDisableAllInterrupts
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpReenableInterrupts (
|
|
; IN KIRQL Irql
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; Restores irql level.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; Irql - Irql state to restore to.
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None
|
|
;
|
|
;--
|
|
|
|
HriNewIrql equ [esp + 4]
|
|
|
|
cPublicProc _HalpReenableInterrupts,1
|
|
cPublicFpo 1, 0
|
|
|
|
movzx ecx, byte ptr HriNewIrql
|
|
fstCall KfLowerIrql
|
|
|
|
stdRET _HalpReenableInterrupts
|
|
|
|
stdENDP _HalpReenableInterrupts
|
|
|
|
|
|
page ,132
|
|
subttl "Interrupt Controller Chip Initialization"
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpInitializePICs (
|
|
; )
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine sends the 8259 PIC initialization commands and
|
|
; masks all the interrupts on 8259s.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None.
|
|
;
|
|
;--
|
|
cPublicProc _HalpInitializePICs ,1
|
|
|
|
pushfd
|
|
push esi ; save caller's esi
|
|
cli ; disable interrupt
|
|
lea esi, PICsInitializationString
|
|
|
|
lodsw ; (AX) = PIC port 0 address
|
|
Hip10: movzx edx, ax
|
|
outsb ; output ICW1
|
|
IODelay
|
|
inc edx ; (DX) = PIC port 1 address
|
|
outsb ; output ICW2
|
|
IODelay
|
|
outsb ; output ICW3
|
|
IODelay
|
|
outsb ; output ICW4
|
|
IODelay
|
|
mov al, 0FFH ; mask all 8259 irqs
|
|
out dx,al ; write mask to PIC
|
|
lodsw
|
|
cmp ax, 0 ; end of init string?
|
|
jne short Hip10 ; go init next PIC
|
|
|
|
;
|
|
; If P0 then squirrel away 4d0 and 4d1 for the other processor to use.
|
|
;
|
|
|
|
cmp byte ptr fs:PcHal.PcrNumber, 0 ; Is this processor 0
|
|
jne short Hip16
|
|
|
|
mov dx, EDGELEVEL_CONTROL_2 ; Yes then save 4d0-4d1
|
|
in al, dx
|
|
shl eax, 8
|
|
mov dx, EDGELEVEL_CONTROL_1
|
|
in al, dx
|
|
mov _SpP0EdgeLevelValue, ax
|
|
|
|
jmp short Hip18
|
|
|
|
;
|
|
; If not P0 then program 4d0 and 4d1 to the values P0 used for them!
|
|
;
|
|
Hip16:
|
|
mov ax, _SpP0EdgeLevelValue
|
|
mov dx, EDGELEVEL_CONTROL_1
|
|
out dx, al
|
|
inc edx
|
|
shr eax, 8
|
|
mov dx, EDGELEVEL_CONTROL_2
|
|
out dx, al
|
|
|
|
Hip18:
|
|
|
|
pop esi ; restore caller's esi
|
|
popfd ; restore interrupts
|
|
stdRET _HalpInitializePICs
|
|
stdENDP _HalpInitializePICs
|
|
|
|
|
|
_TEXT ends
|
|
end
|