592 lines
20 KiB
C
592 lines
20 KiB
C
/*++
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Copyright (c) 1993 Digital Equipment Corporation
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Module Name:
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trigger.c
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Abstract:
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This module implements functions that handle synchronous and asynchronous
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arithmetic exceptions. The Alpha SRM specifies certain code generation
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rules which if followed allow this code (in conjunction with internal
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processor register state) to effect a precise, synchronous exception
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given an imprecise, asynchronous exception. This capability is required
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for software emulation of the IEEE single and double floating operations.
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Author:
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Thomas Van Baak (tvb) 5-Mar-1993
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Environment:
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Kernel mode only.
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Revision History:
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--*/
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#include "ki.h"
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#pragma hdrstop
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#include "alphaops.h"
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//
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// Define forward referenced function prototypes.
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//
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BOOLEAN
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KiLocateTriggerPc (
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IN OUT PEXCEPTION_RECORD ExceptionRecord,
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IN OUT PKTRAP_FRAME TrapFrame
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);
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//
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// Define debugging macros.
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//
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#if DBG
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extern ULONG RtlDebugFlags;
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#define DBGPRINT ((RtlDebugFlags & 0x4) != 0) && DbgPrint
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#else
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#define DBGPRINT 0 && DbgPrint
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#endif
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//
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// Define non-IEEE (a/k/a `high performance') arithmetic exception types.
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// The PALcode exception record is extended by one word and the 4th word
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// contains the reason the arithmetic exception is not an IEEE exception.
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//
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#define NON_IEEE(ExceptionRecord, Reason) \
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(ExceptionRecord)->NumberParameters = 4; \
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(ExceptionRecord)->ExceptionInformation[3] = (Reason);
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#define TRIGGER_FLOATING_REGISTER_MASK_CLEAR 1
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#define TRIGGER_INTEGER_REGISTER_MASK_SET 2
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#define TRIGGER_NO_SOFTWARE_COMPLETION 3
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#define TRIGGER_INVALID_INSTRUCTION_FOUND 4
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#define TRIGGER_INSTRUCTION_FETCH_ERROR 5
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#define TRIGGER_INSTRUCTION_NOT_FOUND 6
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#define TRIGGER_SOURCE_IS_DESTINATION 7
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#define TRIGGER_WRONG_INSTRUCTION 8
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BOOLEAN
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KiFloatingException (
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IN OUT PEXCEPTION_RECORD ExceptionRecord,
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IN OUT PKEXCEPTION_FRAME ExceptionFrame,
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IN OUT PKTRAP_FRAME TrapFrame,
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IN BOOLEAN ImpreciseTrap,
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IN OUT PULONG SoftFpcrCopy
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)
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/*++
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Routine Description:
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This function is called to emulate a floating operation and convert the
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exception status to the proper value. If the exception is a fault, the
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faulting floating point instruction is emulated. If the exception is an
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imprecise trap, an attempt is made to locate and to emulate the original
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trapping floating point instruction.
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Arguments:
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ExceptionRecord - Supplies a pointer to an exception record.
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ExceptionFrame - Supplies a pointer to an exception frame.
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TrapFrame - Supplies a pointer to a trap frame.
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ImpreciseTrap - Supplies a boolean value that specifies whether the
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exception is an imprecise trap.
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SoftFpcrCopy - Supplies a pointer to a longword variable that receives
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a copy of the software FPCR.
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Return Value:
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A value of TRUE is returned if the floating exception is successfully
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emulated. Otherwise, a value of FALSE is returned.
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--*/
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{
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BOOLEAN Status;
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PSW_FPCR SoftwareFpcr;
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PTEB Teb;
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try {
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//
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// Obtain a copy of the software FPCR longword from the TEB.
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//
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Teb = NtCurrentTeb();
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*SoftFpcrCopy = Teb->FpSoftwareStatusRegister;
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SoftwareFpcr = (PSW_FPCR)SoftFpcrCopy;
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DBGPRINT("KiFloatingException: SoftFpcr = %.8lx\n", *SoftFpcrCopy);
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#if DBG
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//
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// If the floating emulation inhibit flag is set, then bypass all
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// software emulation by the kernel and return FALSE to raise the
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// original PALcode exception.
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//
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// N.B. This is for user-mode development and testing and is not
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// part of the API.
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//
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if (SoftwareFpcr->NoSoftwareEmulation != 0) {
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DBGPRINT("KiFloatingException: NoSoftwareEmulation\n");
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return FALSE;
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}
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#endif
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//
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// If the arithmetic exception is an imprecise trap, the address of
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// the trapping instruction is somewhere before the exception address.
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//
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// Otherwise the exception is a fault and the address of the faulting
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// instruction is the exception address.
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//
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if (ImpreciseTrap != FALSE) {
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//
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// If the arithmetic trap ignore mode is enabled, then do not
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// spend time to locate or to emulate the trapping instruction,
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// leave unpredictable results in the destination register, do
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// not set correct IEEE sticky bits in the software FPCR, leave
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// the hardware FPCR sticky status bits as they are, and return
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// TRUE to continue execution. It is assumed that user code will
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// check the hardware FPCR exception status bits to determine if
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// the instruction succeeded or not (Insignia SoftPc feature).
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//
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if (SoftwareFpcr->ArithmeticTrapIgnore != 0) {
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return TRUE;
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}
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//
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// Attempt to locate the trapping instruction. If the instruction
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// stream is such that this is not possible or was not intended,
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// then set an exception code that best reflects the exception
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// summary register bits and return FALSE to raise the exception.
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//
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// Otherwise emulate the trigger instruction in order to compute
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// the correct destination result value, the correct IEEE status
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// bits, and raise any enabled IEEE exceptions.
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//
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if (KiLocateTriggerPc(ExceptionRecord, TrapFrame) == FALSE) {
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KiSetFloatingStatus(ExceptionRecord);
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return FALSE;
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}
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Status = KiEmulateFloating(ExceptionRecord,
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ExceptionFrame,
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TrapFrame,
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SoftwareFpcr);
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} else {
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//
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// Attempt to emulate the faulting instruction in order to perform
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// floating operations not supported by EV4, to compute the correct
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// destination result value, the correct IEEE status bits, and
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// raise any enabled IEEE exceptions.
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//
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Status = KiEmulateFloating(ExceptionRecord,
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ExceptionFrame,
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TrapFrame,
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SoftwareFpcr);
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//
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// If the emulation resulted in a floating point exception and
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// the arithmetic trap ignore mode is enabled, then set the return
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// value to TRUE to suppress the exception and continue execution.
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//
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if ((Status == FALSE) &&
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(SoftwareFpcr->ArithmeticTrapIgnore != 0) &&
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(ExceptionRecord->ExceptionCode != STATUS_ILLEGAL_INSTRUCTION)) {
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Status = TRUE;
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}
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}
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//
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// Store the updated software FPCR longword in the TEB.
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//
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Teb->FpSoftwareStatusRegister = *SoftFpcrCopy;
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DBGPRINT("KiFloatingException: SoftFpcr = %.8lx\n", *SoftFpcrCopy);
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} except (EXCEPTION_EXECUTE_HANDLER) {
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//
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// An exception occurred accessing the TEB.
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//
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ExceptionRecord->ExceptionCode = GetExceptionCode();
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return FALSE;
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}
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return Status;
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}
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BOOLEAN
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KiLocateTriggerPc (
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IN OUT PEXCEPTION_RECORD ExceptionRecord,
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IN OUT PKTRAP_FRAME TrapFrame
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)
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/*++
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Routine Description:
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This function is called to try to determine the precise location of the
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instruction that caused an arithmetic exception. The instruction that
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caused the trap to occur is known as the trigger instruction. On entry,
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the actual address of the trigger instruction is unknown and the exception
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address is the continuation address. The continuation address is the
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address of the instruction that would have executed had the trap not
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occurred. The instructions following the trigger instruction up to the
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continuation address are known as the trap shadow of the trigger
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instruction.
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Alpha AXP produces imprecise, asynchronous arithmetic exceptions. The
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exceptions are imprecise because the exception address when a trap is
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taken may be more than one instruction beyond the address of the
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instruction that actually caused the trap to occur.
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The arithmetic exceptions are traps (rather than faults) because the
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exception address is not the address of the trapping instruction
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itself, but the address of the next instruction to execute, which is
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always (at least) one instruction beyond the address of the trapping
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instruction.
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It is possible for multiple exceptions to occur and result in a single
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trap. This function only determines the address of the first trapping
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instruction.
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Unpredictable values may have been stored in the destination register
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of trapping instructions. Thus to insure that the trigger instruction
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can be located, and that the trigger instruction and any instructions
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in the trap shadow can be re-executed, certain restrictions are placed
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on the type of instructions or the mix of operands in the trap shadow.
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The code generation rules serve only to guarantee that the instruction
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backup algorithm and subsequent re-execution can always be successful.
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Hence the restrictions on such constructs as branches, jumps, and the
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re-use of source or destination operands within the trap shadow.
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Arguments:
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ExceptionRecord - Supplies a pointer to an exception record.
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TrapFrame - Supplies a pointer to a trap frame.
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Return Value:
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If the trigger PC was precisely determined, the exception address in
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the exception record is set to the trigger PC, the continuation address
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in the trap frame is updated, and a value of TRUE is returned. Otherwise
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no values are stored and a value of FALSE is returned.
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--*/
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{
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PEXC_SUM ExceptionSummary;
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ULONG Fa;
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ULONG Fb;
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ULONG Fc;
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ULONG FloatRegisterTrashMask;
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ULONG FloatRegisterWriteMask;
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ALPHA_INSTRUCTION Instruction;
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ULONG IntegerRegisterWriteMask;
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ULONG Opcode;
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ULONG_PTR TrapShadowLowLimit;
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ULONG_PTR TriggerPc;
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KPROCESSOR_MODE PreviousMode;
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//
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// Obtain a copy of the float and integer register write mask registers
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// and the exception summary register from the exception record built by
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// PALcode.
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//
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FloatRegisterWriteMask = (ULONG)ExceptionRecord->ExceptionInformation[0];
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IntegerRegisterWriteMask = (ULONG)ExceptionRecord->ExceptionInformation[1];
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ExceptionSummary = (PEXC_SUM)&(ExceptionRecord->ExceptionInformation[2]);
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DBGPRINT("KiLocateTriggerPc: WriteMask %.8lx.%.8lx, ExceptionSummary %.8lx\n",
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FloatRegisterWriteMask, IntegerRegisterWriteMask,
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*(PULONG)ExceptionSummary);
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//
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// Capture previous mode from trap frame not current thread.
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//
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PreviousMode = (KPROCESSOR_MODE)(((PSR *)(&TrapFrame->Psr))->MODE);
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if (FloatRegisterWriteMask == 0) {
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//
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// It should not be possible to have a floating point exception without
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// at least one of the destination float register bits set. The trap
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// shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: FloatRegisterWriteMask clear\n");
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NON_IEEE(ExceptionRecord, TRIGGER_FLOATING_REGISTER_MASK_CLEAR);
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return FALSE;
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}
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if (IntegerRegisterWriteMask != 0) {
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//
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// It is not possible to precisely locate the trigger instruction
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// when the integer overflow bit is set. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: IntegerRegisterMask set.\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INTEGER_REGISTER_MASK_SET);
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return FALSE;
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}
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if (ExceptionSummary->SoftwareCompletion == 0) {
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//
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// The exception summary software completion bit is the AND of the
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// /S bits of all trapping instructions in the trap shadow. Since
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// the software completion bit is not set, it can be assumed the
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// code that was executing does not want precise exceptions, or if
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// it does, the code does not comply with the Alpha AXP guidelines
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// for locating the trigger PC. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: SoftwareCompletion clear\n");
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NON_IEEE(ExceptionRecord, TRIGGER_NO_SOFTWARE_COMPLETION);
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return FALSE;
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}
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//
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// Search for the trigger instruction starting with the instruction before
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// the continuation PC (the instruction pointed to by Fir either did not
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// complete or did not even start). Limit the search to the arbitrary
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// limit of N instructions back from the current PC to prevent unbounded
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// searches. The search is complete when all trapping destination register
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// bits in the float write mask register have been accounted for.
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//
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FloatRegisterTrashMask = 0;
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TriggerPc = (ULONG_PTR)TrapFrame->Fir;
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TrapShadowLowLimit = TriggerPc - (500 * sizeof(ULONG));
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try {
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do {
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TriggerPc -= 4;
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if (TriggerPc < TrapShadowLowLimit) {
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//
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// The trigger PC is too far away from the exception PC to
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// be reasonable. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: Trap shadow too long\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INSTRUCTION_NOT_FOUND);
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return FALSE;
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}
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if (PreviousMode != KernelMode) {
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Instruction.Long = ProbeAndReadUlong((PULONG)TriggerPc);
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} else {
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Instruction.Long = *((PULONG)TriggerPc);
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}
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//
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// Examine the opcode of this instruction to determine if the
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// trap shadow is invalid.
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//
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Opcode = Instruction.Memory.Opcode;
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if (Opcode == JMP_OP) {
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//
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// This is one of the jump instructions: jump, return, or
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// either form of jsr. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: Jump within Trap Shadow\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INVALID_INSTRUCTION_FOUND);
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return FALSE;
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} else if ((Opcode >= BR_OP) && (Opcode <= BGT_OP)) {
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//
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// The instruction is one of 16 branch opcodes that consists
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// of BR, the 6 floating point branch, BSR, and the 8 integer
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// branch instructions. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: Branch within Trap Shadow\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INVALID_INSTRUCTION_FOUND);
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return FALSE;
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} else if ((Instruction.Memory.Opcode == MEMSPC_OP) &&
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((Instruction.Memory.MemDisp == TRAPB_FUNC) ||
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(Instruction.Memory.MemDisp == EXCB_FUNC))) {
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//
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// The instruction is a type of TRAPB instruction. The trap
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// shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: Trapb within Trap Shadow\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INVALID_INSTRUCTION_FOUND);
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return FALSE;
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} else if (Opcode == CALLPAL_OP) {
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//
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// The instruction is a Call PAL. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: Call PAL within Trap Shadow\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INVALID_INSTRUCTION_FOUND);
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return FALSE;
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} else if ((Opcode == IEEEFP_OP) || (Opcode == FPOP_OP)) {
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//
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// The instruction is an IEEE floating point instruction.
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// Decode the destination register of the floating point
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// instruction in order to check against the register mask.
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//
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Fc = Instruction.FpOp.Fc;
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if (Fc != FZERO_REG) {
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FloatRegisterTrashMask |= (1 << Fc);
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}
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FloatRegisterWriteMask &= ~(1 << Fc);
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}
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} while (FloatRegisterWriteMask != 0);
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//
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// If the instruction thought to be the trigger instruction does not
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// have the /S bit set, then the trap shadow is invalid (some other
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// instruction must have caused software completion bit to be set).
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//
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if ((Instruction.FpOp.Function & FP_TRAP_ENABLE_S) == 0) {
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DBGPRINT("KiLocateTriggerPc: Trigger instruction missing /S\n");
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NON_IEEE(ExceptionRecord, TRIGGER_WRONG_INSTRUCTION);
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return FALSE;
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}
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//
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// If either of the operand registers of the trigger instruction is
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// also the destination register of the trigger instruction or any
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// instruction in the trap shadow, then the trap shadow in invalid.
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// This is because the original value of the operand register(s) may
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// have been destroyed making it impossible to re-execute the trigger
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// instruction.
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//
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Fa = Instruction.FpOp.Fa;
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Fb = Instruction.FpOp.Fb;
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if ((FloatRegisterTrashMask & ((1 << Fa) | (1 << Fb))) != 0) {
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DBGPRINT("KiLocateTriggerPc: Source is destination\n");
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NON_IEEE(ExceptionRecord, TRIGGER_SOURCE_IS_DESTINATION);
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return FALSE;
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}
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} except (EXCEPTION_EXECUTE_HANDLER) {
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//
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// An exception occurred while fetching the value of the
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// next previous instruction. The trap shadow is invalid.
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//
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DBGPRINT("KiLocateTriggerPc: Instruction fetch error\n");
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NON_IEEE(ExceptionRecord, TRIGGER_INSTRUCTION_FETCH_ERROR);
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return FALSE;
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}
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//
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// The trigger instruction was successfully located. Set the precise
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// exception address in the exception record, set the new continuation
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// address in the trap frame, and return a value of TRUE.
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//
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DBGPRINT("KiLocateTriggerPc: Exception PC = %p, Trigger PC = %p\n",
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ExceptionRecord->ExceptionAddress, TriggerPc);
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ExceptionRecord->ExceptionAddress = (PVOID)TriggerPc;
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TrapFrame->Fir = (ULONGLONG)(LONG_PTR)(TriggerPc + 4);
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return TRUE;
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}
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VOID
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KiSetFloatingStatus (
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IN OUT PEXCEPTION_RECORD ExceptionRecord
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)
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/*++
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Routine Description:
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This function is called to convert the exception summary register bits
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into a status code value.
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Arguments:
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ExceptionRecord - Supplies a pointer to an exception record.
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Return Value:
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None.
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--*/
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{
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PEXC_SUM ExceptionSummary;
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//
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// Perform the following triage on the exception summary register to
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// report the type of exception, even if though the PC reported is
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// imprecise.
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//
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DBGPRINT("KiSetFloatingStatus: ExceptionSummary = %.8lx\n",
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ExceptionRecord->ExceptionInformation[2]);
|
||
|
||
ExceptionSummary = (PEXC_SUM)(&ExceptionRecord->ExceptionInformation[2]);
|
||
if (ExceptionSummary->InvalidOperation != 0) {
|
||
ExceptionRecord->ExceptionCode = STATUS_FLOAT_INVALID_OPERATION;
|
||
|
||
} else if (ExceptionSummary->DivisionByZero != 0) {
|
||
ExceptionRecord->ExceptionCode = STATUS_FLOAT_DIVIDE_BY_ZERO;
|
||
|
||
} else if (ExceptionSummary->Overflow != 0) {
|
||
ExceptionRecord->ExceptionCode = STATUS_FLOAT_OVERFLOW;
|
||
|
||
} else if (ExceptionSummary->Underflow != 0) {
|
||
ExceptionRecord->ExceptionCode = STATUS_FLOAT_UNDERFLOW;
|
||
|
||
} else if (ExceptionSummary->InexactResult != 0) {
|
||
ExceptionRecord->ExceptionCode = STATUS_FLOAT_INEXACT_RESULT;
|
||
|
||
} else if (ExceptionSummary->IntegerOverflow != 0) {
|
||
ExceptionRecord->ExceptionCode = STATUS_INTEGER_OVERFLOW;
|
||
|
||
} else {
|
||
ExceptionRecord->ExceptionCode = STATUS_FLOAT_STACK_CHECK;
|
||
}
|
||
}
|