113 lines
3.8 KiB
C
113 lines
3.8 KiB
C
/******************************
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Intel Confidential
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******************************/
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#ifndef _EM_STATE_H
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#define _EM_STATE_H
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/*****************************/
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/* Processor's State */
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/*****************************/
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#ifndef FPSR
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#define FPSR ps->state_AR[ar_fpsr].fpsr
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#endif
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#ifndef FPSR_value
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#define FPSR_value ps->state_AR[ar_fpsr].uint_value
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#endif
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#ifndef PSR
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#define PSR ps->state_PSR
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#endif
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#ifndef IP
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#define IP ps->state_IP
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#endif
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#ifndef AR
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#define AR ps->state_AR
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#endif
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#ifndef FR
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#define FR ps->state_FR
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#endif
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#ifndef GR
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#define GR ps->state_GR
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#endif
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#ifndef PR
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#define PR ps->state_PR
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#endif
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#ifndef MEM
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#define MEM ps->state_MEM
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#endif
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#ifndef UM
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#define UM ps->state_PSR
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#endif
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#define FPSR_traps (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>> 0)&0x3F)
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#define FPSR_sf0_flags (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>13)&0x3F)
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#define FPSR_sf1_flags (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>26)&0x3F)
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#define FPSR_sf2_flags (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>39)&0x3F)
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#define FPSR_sf3_flags (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>52)&0x3F)
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#define FPSR_sf0_controls (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>> 6)&0x7F)
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#define FPSR_sf1_controls (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>19)&0x7F)
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#define FPSR_sf2_controls (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>32)&0x7F)
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#define FPSR_sf3_controls (EM_uint_t)((ps->state_AR[ar_fpsr].uint_value>>45)&0x7F)
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#define GENERAL_FORM ps->state_form.general_form
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#define DATA_FORM ps->state_form.data_form
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#define CONTROL_FORM ps->state_form.control_form
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#define FP82_FLOATING_FORM ps->state_form.fp82_floating_form
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#define CLEAR_FORM ps->state_form.clear_form
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#define NO_CLEAR_FORM ps->state_form.no_clear_form
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#define HIGH_UNSIGNED_FORM ps->state_form.high_unsigned_form
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#define LOW_FORM ps->state_form.low_form
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#define HIGH_FORM ps->state_form.high_form
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#define NEG_SIGN_FORM ps->state_form.neg_sign_form
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#define SIGN_FORM ps->state_form.sign_form
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#define SIGN_EXP_FORM ps->state_form.sign_exp_form
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#define MIX_L_FORM ps->state_form.mix_l_form
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#define MIX_R_FORM ps->state_form.mix_r_form
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#define MIX_LR_FORM ps->state_form.mix_lr_form
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#define SXT_L_FORM ps->state_form.sxt_l_form
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#define SXT_R_FORM ps->state_form.sxt_r_form
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#define PACK_FORM ps->state_form.pack_form
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#define SWAP_FORM ps->state_form.swap_form
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#define SWAP_NL_FORM ps->state_form.swap_nl_form
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#define SWAP_NR_FORM ps->state_form.swap_nr_form
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#define SIGNED_FORM ps->state_form.signed_form
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#define TRUNC_FORM ps->state_form.trunc_form
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#define UNSIGNED_FORM ps->state_form.unsigned_form
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#define SINGLE_FORM ps->state_form.single_form
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#define DOUBLE_FORM ps->state_form.double_form
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#define EXPONENT_FORM ps->state_form.exponent_form
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#define SIGNIFICAND_FORM ps->state_form.significand_form
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#define NO_BASE_UPDATE_FORM ps->state_form.no_base_update_form
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#define REGISTER_BASE_UPDATE_FORM ps->state_form.register_base_update_form
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#define IMMEDIATE_BASE_UPDATE_FORM ps->state_form.immediate_base_update_form
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#define FCHECK_BRANCH_IMPLEMENTED ps->state_form.fcheck_branch_implemented
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/*
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The following concern software assistance. For an implementation-determined
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software assistance fault or trap to occur (when encountering
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denormals MERCED_RTL must be 1. An architecturally-mandated swa
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can still occur when MERCED_RTL is 0. Such an assist occurs in frcpa and
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fprcpa.
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*/
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#define MERCED_RTL ps->state_MERCED_RTL
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#endif /* _EM_STATE_H */
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