265 lines
5.8 KiB
ArmAsm
265 lines
5.8 KiB
ArmAsm
//++
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//
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// Module Name:
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//
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// proceessr.s
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//
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// Abstract:
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//
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// Hardware workarounds.
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//
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// Author:
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//
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// Allen M. Kay (allen.m.kay@intel.com) 4-April-2000
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//
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// Environment:
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//
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// Kernel mode only.
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//
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// Revision History:
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//
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//--
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#include "ksia64.h"
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#if _MERCED_A0_
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//
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// Merced Processor ERRATA Workaround
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//
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LEAF_ENTRY (KiProcessorWorkAround)
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mov t0 = 3
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;;
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mov t1 = cpuid[t0] // read cpuid3
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;;
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extr.u t1 = t1, 24, 8
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;;
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cmp.ne pt0 = 7, t1 // if the processor is not the Itanium processor
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;;
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(pt0) br.ret.spnt b0 // then just return
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;;
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Disable_L1_Bypass:
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tbit.nz pt0, pt1 = a0, DISABLE_L1_BYPASS
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(pt0) br.sptk CPL_bug_workaround
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mov t0 = 484
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mov t1 = 4
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;;
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mov msr[t0] = t1
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CPL_bug_workaround:
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tbit.nz pt0, pt1 = a0, DISABLE_CPL_FIX
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(pt0) br.sptk DisableFullDispersal
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mov t0 = 66
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;;
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mov t1 = msr[t0]
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;;
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dep t1 = 1, t1, 0, 4
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;;
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mov msr[t0] = t1
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DisableFullDispersal:
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tbit.z pt0, pt1 = a0, ENABLE_FULL_DISPERSAL
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mov t0 = 652
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;;
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// Single Dispersal
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(pt1) mov t1 = 0
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(pt0) mov t1 = 1
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;;
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mov msr[t0] = t1
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;;
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DisableBtb:
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tbit.nz pt0, pt1 = a0, DISABLE_BTB_FIX
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(pt0) br.sptk DisableTar
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// This change is needed to make WOW64 run (disable BTB)
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mov t1 = 224
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;;
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mov t0 = msr[t1] // Get the old value
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;;
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or t0 = 0x40, t0 // Or in bit 6
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;;
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mov msr[t1] = t0 // Put it back
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DisableTar:
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tbit.nz pt0, pt1 = a0, DISABLE_TAR_FIX
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(pt0) br.sptk DataBreakPoint
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// disable TAR to fix sighting 3739
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mov t0 = 51
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mov t1 = 1
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;;
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mov msr[t0] = t1
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DataBreakPoint:
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tbit.nz pt0, pt1 = a0, DISABLE_DATA_BP_FIX
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(pt0) br.sptk DetStallFix
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// this change is needed to enable data debug
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mov t0 = 387
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;;
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mov msr[t0] = r0
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;;
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DetStallFix:
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tbit.nz pt0, pt1 = a0, DISABLE_DET_STALL_FIX
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(pt0) br.sptk DisableIA32BranchFix
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//
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// BSB CADS spacing 7
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//
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mov t0 = 514
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movl t1 = 0x0930442325210445
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;;
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mov msr[t0] = t1;
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;;
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// p1_disable()
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mov t0 = 484
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mov t1 = 0xc
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;;
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mov msr[t0] = t1
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// trickle()
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mov t0 = 485
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mov t1 = 1
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;;
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mov msr[t0] = t1
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// Throttle L1 access in L0D
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mov t1 = 384
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;;
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mov t0 = msr[t1] // Get the old value
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;;
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dep t2 = 1, t0, 44, 1
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;;
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mov msr[t1] = t2 // Put it back
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// rse_disable()
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mov t1 = 258
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;;
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mov t0 = msr[t1] // Get the old value
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movl t2 = 0x4000
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;;
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or t0 = t2, t0 // Or in bit 44
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;;
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mov msr[t1] = t0 // Put it back
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;;
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DisableIA32BranchFix:
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tbit.nz pt0, pt1 = a0, DISABLE_IA32BR_FIX
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(pt0) br.sptk DisableIA32RsbFix
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// Occasionally the ia32 iVE gets confused between macro branches
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// and micro branches. This helps that confusion
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mov t1 = 204
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;;
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mov t0 = msr[t1] // Get the old value
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;;
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or t0 = 0x10, t0 // Or in bit 4
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;;
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mov msr[t1] = t0 // Put it back
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DisableIA32RsbFix:
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tbit.nz pt0, pt1 = a0, DISABLE_IA32RSB_FIX
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(pt0) br.sptk DisablePrefetchUnsafeFill
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// More ia32 confusion. This time on the ReturnStackBuffer
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mov t1 = 196
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movl t0 = 0x40000008 // Turn off the RSB
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;;
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mov msr[t1] = t0
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DisablePrefetchUnsafeFill:
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tbit.z pt0, pt1 = a0, DISABLE_UNSAFE_FILL
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(pt0) br.cond.sptk DisableStoreUpdate
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mov t1 = 80
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mov t0 = 8
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;;
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mov msr[t1] = t0
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DisableStoreUpdate:
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tbit.nz pt0, pt1 = a0, DISABLE_STORE_UPDATE
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(pt0) br.cond.sptk ErrataDone
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mov t1 = 384
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;;
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mov t0 = msr[t1]
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;;
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dep t0 = 1, t0, 18, 1
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;;
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mov msr[t1] = t0
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ErrataDone:
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#if 1
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tbit.nz pt0 = a0, DISABLE_INTERRUPTION_LOG
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(pt0) br.cond.sptk HistoryDone
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//
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// Configure the history buffer for capturing branches/interrupts
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//
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mov t1 = 674
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;;
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mov msr[t1] = r0 // HBC <- 0
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;;
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mov t0 = 675
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;;
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mov t1 = msr[t0]
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mov t2 = 2
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;;
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dep t1 = t2, t1, 0, 9
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;;
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mov msr[t0] = t1 // HBCF <- 2
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;;
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mov t1 = 12
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mov t0 = 0xfe8f
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;;
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mov pmc[t1] = t0
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;;
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mov t1 = 680
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mov t2 = 681
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mov t3 = 682
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mov t4 = 683
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mov t5 = 684
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mov t6 = 685
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mov t7 = 686
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mov t8 = 687
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;;
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.reg.val t1, 680
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mov msr[t1] = r0
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.reg.val t2, 681
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mov msr[t2] = r0
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.reg.val t3, 682
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mov msr[t3] = r0
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.reg.val t4, 683
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mov msr[t4] = r0
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.reg.val t5, 684
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mov msr[t5] = r0
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.reg.val t6, 685
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mov msr[t6] = r0
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.reg.val t7, 686
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mov msr[t7] = r0
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.reg.val t8, 687
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mov msr[t8] = r0
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HistoryDone:
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#endif
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LEAF_RETURN
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LEAF_EXIT (KiProcessorWorkAround)
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#endif
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