405 lines
8.4 KiB
C
405 lines
8.4 KiB
C
/*++
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Copyright (c) 1989 Microsoft Corporation
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Copyright (c) 1992 Digital Equipment Corporation
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Module Name:
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debugsup.c
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Abstract:
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This module contains routines which provide support for the
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kernel debugger.
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Author:
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Lou Perazzoli (loup) 02-Aug-90
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Joe Notarangelo 23-Apr-1992
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Revision History:
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--*/
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#include "mi.h"
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PVOID
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MmDbgReadCheck (
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IN PVOID VirtualAddress
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)
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/*++
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Routine Description:
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ALPHA implementation specific:
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This routine returns the virtual address which is valid (mapped)
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for read access.
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Arguments:
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VirtualAddress - Supplies the virtual address to check.
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Return Value:
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Returns NULL if the address is not valid or readable, otherwise
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returns the virtual address.
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Environment:
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Kernel mode IRQL at DISPATCH_LEVEL or greater.
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--*/
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{
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if ((VirtualAddress >= (PVOID)KSEG0_BASE) &&
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(VirtualAddress < (PVOID)KSEG2_BASE)) {
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return VirtualAddress;
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}
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if (!MmIsAddressValid (VirtualAddress)) {
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return NULL;
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}
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return VirtualAddress;
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}
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PVOID
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MmDbgWriteCheck (
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IN PVOID VirtualAddress,
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IN PHARDWARE_PTE Opaque
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)
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/*++
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Routine Description:
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ALPHA implementation specific:
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This routine returns the physical address for a virtual address
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which is valid (mapped) for write access.
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If the address is valid and writable and not within KSEG0
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the physical address within KSEG0 is returned. If the address
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is within KSEG0 then the called address is returned.
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NOTE: The physical address must only be used while the interrupt
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level on ALL processors is above DISPATCH_LEVEL, otherwise the
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binding between the virtual address and the physical address can
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change due to paging.
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Arguments:
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VirtualAddress - Supplies the virtual address to check.
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Opaque - Supplies a pointer to fill with an opaque value.
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Return Value:
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Returns NULL if the address is not valid or readable, otherwise
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returns the physical address of the corresponding virtual address.
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Environment:
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Kernel mode IRQL at DISPATCH_LEVEL or greater.
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--*/
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{
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MMPTE PteContents;
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PMMPTE PointerPte;
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PMMPTE InputPte;
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InputPte = (PMMPTE)Opaque;
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InputPte->u.Long = 0;
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if ((VirtualAddress >= (PVOID)KSEG0_BASE) &&
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(VirtualAddress < (PVOID)KSEG2_BASE)) {
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return VirtualAddress;
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}
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if (!MmIsAddressValid (VirtualAddress)) {
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return NULL;
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}
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PointerPte = MiGetPteAddress (VirtualAddress);
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if ((VirtualAddress <= MM_HIGHEST_USER_ADDRESS) &&
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(PointerPte->u.Hard.PageFrameNumber < MM_PAGES_IN_KSEG0)) {
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//
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// User mode - return the physical address. This prevents
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// copy on write faults for breakpoints on user-mode pages.
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// IGNORE write protection.
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//
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// N.B. - The physical address must be less than 1GB to allow this
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// short-cut mapping.
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//
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// N.B. - Any non-breakpoint modifications can get lost when the page
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// is paged out because the PTE is not marked modified when
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// the access is made through this alternate mapping.
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//
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return (PVOID)
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((ULONG)MmGetPhysicalAddress(VirtualAddress).LowPart + KSEG0_BASE);
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}
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if (PointerPte->u.Hard.Write == 0) {
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//
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// PTE is not writable, make it so.
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//
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PteContents = *PointerPte;
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*InputPte = PteContents;
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//
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// Modify the PTE to ensure write permissions.
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//
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PteContents.u.Hard.Write = 1;
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*PointerPte = PteContents;
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//
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// KeFillEntryTb is liable to IPI the other processors. This is
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// definitely NOT what we want as the other processors are frozen
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// in the debugger and we will deadlock if we try and IPI them.
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// Just flush the current processor instead.
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//
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// KeFillEntryTb ((PHARDWARE_PTE)PointerPte, VirtualAddress, TRUE);
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//
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KiFlushSingleTb(TRUE, VirtualAddress);
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}
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return VirtualAddress;
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}
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VOID
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MmDbgReleaseAddress (
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IN PVOID VirtualAddress,
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IN PHARDWARE_PTE Opaque
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)
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/*++
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Routine Description:
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i386/486 implementation specific:
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This routine resets the specified virtual address access permissions
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to its original state.
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Arguments:
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VirtualAddress - Supplies the virtual address to check.
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Opaque - Supplies an opaque pointer.
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Return Value:
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None.
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Environment:
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Kernel mode IRQL at DISPATCH_LEVEL or greater.
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--*/
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{
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MMPTE TempPte;
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PMMPTE PointerPte;
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PMMPTE InputPte;
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InputPte = (PMMPTE)Opaque;
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ASSERT (MmIsAddressValid (VirtualAddress));
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if (InputPte->u.Long != 0) {
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PointerPte = MiGetPteAddress (VirtualAddress);
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TempPte = *InputPte;
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*PointerPte = TempPte;
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//
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// KeFillEntryTb is liable to IPI the other processors. This is
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// definitely NOT what we want as the other processors are frozen
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// in the debugger and we will deadlock if we try and IPI them.
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// Just flush the current processor instead.
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//
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// KeFillEntryTb ((PHARDWARE_PTE)PointerPte, VirtualAddress, TRUE);
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//
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KiFlushSingleTb(TRUE, VirtualAddress);
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}
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return;
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}
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PVOID64
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MmDbgReadCheck64 (
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IN PVOID64 VirtualAddress
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)
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/*++
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Routine Description:
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ALPHA implementation specific:
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This routine returns the virtual address which is valid (mapped)
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for read access.
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If the address is valid and readable then the called address is returned.
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Arguments:
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VirtualAddress - Supplies the virtual address to check.
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Return Value:
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Returns NULL if the address is not valid or readable, otherwise
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returns the virtual address.
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Environment:
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Kernel mode IRQL at DISPATCH_LEVEL or greater.
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--*/
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{
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#ifdef VLM_SUPPORT
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if (!MmIsAddressValid64 (VirtualAddress)) {
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return NULL;
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}
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return VirtualAddress;
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#else
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return NULL;
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#endif
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}
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PVOID64
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MmDbgWriteCheck64 (
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IN PVOID64 VirtualAddress
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)
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/*++
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Routine Description:
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ALPHA implementation specific:
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This routine returns the physical address for a virtual address
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which is valid (mapped) for write access.
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If the address is valid and writable then the called address is returned.
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Arguments:
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VirtualAddress - Supplies the virtual address to check.
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Return Value:
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Returns NULL if the address is not valid or readable, otherwise
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returns the virtual address.
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Environment:
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Kernel mode IRQL at DISPATCH_LEVEL or greater.
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--*/
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{
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#ifdef VLM_SUPPORT
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PMMPTE PointerPte;
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if (!MmIsAddressValid64 (VirtualAddress)) {
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return NULL;
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}
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PointerPte = MiGetPteAddress64 (VirtualAddress);
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if (PointerPte->u.Hard.Write == 0) {
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return NULL;
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}
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return VirtualAddress;
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#else
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return NULL;
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#endif
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}
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PVOID64
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MmDbgTranslatePhysicalAddress64 (
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IN PHYSICAL_ADDRESS PhysicalAddress
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)
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/*++
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Routine Description:
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ALPHA implementation specific:
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The Alpha processor provides a direct-mapped address space called
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the superpage. The entire physical address space can be
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addressed via the superpage. This routine translates a physical
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address to its corresponding superpage address. Unfortunately,
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the base superpage address is processor-dependent. Therefore, we
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have to compute it based on the processor level. As new processors are
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released, this routine will need to be updated.
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This routine does not use PTEs.
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Arguments:
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PhysicalAddress - Supplies the physical address to translate.
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Return Value:
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The virtual (superpage) address which corresponds to the physical address.
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Environment:
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Kernel mode IRQL at DISPATCH_LEVEL or greater.
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--*/
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{
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switch (KeProcessorLevel) {
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case PROCESSOR_ALPHA_21064:
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case PROCESSOR_ALPHA_21066:
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case PROCESSOR_ALPHA_21068:
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PhysicalAddress.QuadPart &= 0x00000003ffffffff;
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PhysicalAddress.QuadPart |= 0xfffffc0000000000;
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break;
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case PROCESSOR_ALPHA_21164:
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case PROCESSOR_ALPHA_21164PC:
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PhysicalAddress.QuadPart &= 0x000000ffffffffff;
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PhysicalAddress.QuadPart |= 0xfffffc0000000000;
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break;
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case PROCESSOR_ALPHA_21264:
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PhysicalAddress.QuadPart &= 0x00000fffffffffff;
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PhysicalAddress.QuadPart |= 0xffff800000000000;
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break;
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default:
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return NULL64;
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}
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return (PVOID64)PhysicalAddress.QuadPart;
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}
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