522 lines
13 KiB
C
522 lines
13 KiB
C
/***************************************************************************
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* ADC.H *
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****************************************************************************
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*
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* Last change: 18 janvier 1994
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*
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* By: Patrice Gagnon
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*
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* Changes:
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*
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* Description: All definitions used for the ENCODER's test program.
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*
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****************************************************************************/
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/********************** DEFINES: IDENTIFICATION ************************/
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#define DENC_REG 0
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#define PSG_REG 1
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#define DAC_REG 2
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#define ADC_REG 3
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#define CTRL_REG 4
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#define MGA_DAC_LUT 0
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#define ENC_DENC_CLUT 1
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#define ENC_DAC_COL_LUT 2
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#define ENC_COL_LUT 3
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#define ALL_COL_LUT 4
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#define ENC_DAC_CUR_LUT 5
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#define ENC_ID_REV0 0x50
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#define PSG_ID 0x02
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#define BASE_VER 0x02
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#define DELUXE_VER 0x03
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#define PAL_STD 1
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#define NTSC_STD 2
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#define VAFC 0x10
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#define BLANC 0x00ffffff
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#define NOIR 0x00000000
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#define ROUGE 0x00ff0000
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#define VERT 0x0000ff00
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#define BLEU 0x000000ff
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#define RED_PATH 0
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#define GREEN_PATH 1
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#define BLUE_PATH 2
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#define WHITE_PATH 3
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#define ALPHA_PATH 4
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#define DEFAULT_REG 0
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#define PATH_REG 1
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#define VISU_ALPHA 2
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#define KEYING 3
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#define ONE_CHANGE 4
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#define ALL_REG 0xff
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#define BOTH_SENSE 3
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#define ONLY_DENC 2
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#define ONLY_DAC 1
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#define NONE 0
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#define MGA_SENSE 1
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#define MAX_LEVEL 0xfc
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#define MIN_LEVEL 0x00
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#define BLANCK_LEVEL 0x64
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#define WHITE_LEVEL 0xff
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#define RED_LEVEL 0xa4
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#define GREEN_LEVEL 0xd4
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#define BLUE_LEVEL 0x84
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#define SECUR_FACTOR 0x0c /* 57 mV of security */
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/******************** DEFINES: NUMBER OF REGISTER **********************/
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#define DENC_NBRE_REG 16
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#define PSG_NBRE_REG 23
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#define PSG_NBRE_FULL_REG 17
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#define PSG_NBRE_REG_A_CHAMP 3
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#define DAC_NBRE_REG 16+1 /* COMMAND3 addition */
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#define DAC_NBRE_REG_A_CHAMP 4+1 /* " " */
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#define DAC_NBRE_FULL_REG 12
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#define ADC_NBRE_REG 8-4 /* IOUT4-6 unused */
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#define ADC_NBRE_REG_A_CHAMP 1
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#define ADC_NBRE_FULL_REG 6-3 /* " " */
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/******************** DEFINES: CALCUL OF ADDRESSES *********************/
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#define BASE_ADDR1 0x240
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#define BASE_ADDR2 0x300
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#define BASE_ADDR3 0x340
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#define ENC_CTRL_OFFSET 0x00
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#define ENC_ID_OFFSET 0x02
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#define DENC_OFFSET 0x04
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#define PSG_OFFSET 0x08
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#define ADC_OFFSET 0x0c
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#define DAC_OFFSET 0x10
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#define DENC_CLUT_CTRL_RD ( DENC_OFFSET + 0x0 )
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#define DENC_CLUT_CTRL_WR ( DENC_OFFSET + 0x0 )
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#define DENC_CLUT_DATA ( DENC_OFFSET + 0x1 )
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#define DAC_LUT_CTRL_RD ( DAC_OFFSET + 0x3 )
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#define DAC_LUT_CTRL_WR ( DAC_OFFSET + 0x0 )
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#define DAC_LUT_DATA ( DAC_OFFSET + 0x1 )
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#define DAC_CUR_CTRL_RD ( DAC_OFFSET + 0x7 )
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#define DAC_CUR_CTRL_WR ( DAC_OFFSET + 0x4 )
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#define DAC_CUR_DATA ( DAC_OFFSET + 0x5 )
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#define DENC_ADDR_CTRL ( DENC_OFFSET + 0x2 )
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#define DENC_DATA_CTRL ( DENC_OFFSET + 0x3 )
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#define PSG_ADDR_CTRL ( PSG_OFFSET + 0x0 )
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#define PSG_DATA_CTRL ( PSG_OFFSET + 0x2 )
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/****************************** MACROS ***********************************/
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#define AUTO_INC (inw (dataPort) >> 9) & 0x1
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#define VERSION enc.board.id_reg.f.ver
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#define NOT_ENCODER (enc.board.id_reg.all & 0xf7) != ENC_ID_REV0
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#define VAFC_INPUT enc.board.ctrl_reg.f.vafc_input == IN_VAFC
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#define KEYING_EN enc.denc.index08.f.keye == ENABLE
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#define IN_NTSC enc.board.ctrl_reg.f.ntsc_en == NTSC_STD
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#define CLEAR_LUT(lutSel) initEveryLut (lutSel,1,0x00,0xff,0,0,0)
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/******************** DEFINES: FIELD *********************/
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#define ENC_FILTER ( (word)0x0004 )
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/************************* DENC'S STRUCTURE ******************************/
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/***** CONTROL TABLE *****/
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typedef struct
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{
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union /* INDEX 00 */
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{
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struct
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{
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byte mod : 2;
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byte ccir : 1;
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byte scbw : 1;
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byte fmt : 3;
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byte vtby : 1;
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} f;
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byte all;
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} index00;
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byte trer; /* INDEX 01 */
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byte treg; /* INDEX 02 */
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byte treb; /* INDEX 03 */
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union /* INDEX 04 */
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{
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struct
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{
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byte oef : 1;
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byte hlck : 1;
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byte hpll : 1;
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byte nint : 1;
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byte vtrc : 1;
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byte scen : 1;
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byte sysel : 2;
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} f;
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byte all;
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} index04;
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union /* INDEX 05 */
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{
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struct
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{
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byte gdc : 6;
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byte unused : 2;
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} f;
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byte all;
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} index05;
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byte idel; /* INDEX 06 */
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union /* INDEX 07 */
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{
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struct
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{
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byte pso : 6;
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byte unused : 2;
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} f;
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byte all;
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} index07;
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union /* INDEX 08 */
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{
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struct
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{
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byte srsn : 1;
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byte gpsw : 1;
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byte im : 1;
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byte coki : 1;
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byte cpr : 1;
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byte src : 1;
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byte keye : 1;
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byte dd : 1;
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} f;
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byte all;
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} index08;
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union /* INDEX 09 */
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{
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struct
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{
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byte rtce : 1;
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byte rtin : 1;
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byte rtsc : 1;
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byte iepi : 1;
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byte mpkc : 2;
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byte bame : 1;
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byte unused : 1;
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} f;
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byte all;
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} index09;
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byte chps; /* INDEX 0C */
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byte fsco; /* INDEX 0D */
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union /* INDEX 0E */
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{
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struct
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{
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byte std : 4;
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byte clck : 1;
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byte unused : 3;
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} f;
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byte all;
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} index0E;
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} DENC;
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/************************** PSG'S STRUCTURE ******************************/
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#define PSG_DPYCTL_IDX 0x0
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#define PSG_POLCTL_IDX 0x1
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#define PSG_EXTCTL_IDX 0x2
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#define PSG_V_TOTAL_IDX 0x3
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#define PSG_H_TOTAL_IDX 0x7
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#define PSG_HS_BURST_IDX 0x10 /* Horiz. start */
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#define PSG_HE_BURST_IDX 0x11 /* Horiz. end */
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#define PSG_VS_BURST_IDX 0x12 /* Vert. start */
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#define PSG_VE_BURST_IDX 0x13 /* Vert. end */
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#define PSG_VCOUNT_IDX 0x14
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#define PSG_HCOUNT_IDX 0x15
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#define PSG_SCOUNT_IDX 0x16
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typedef struct
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{
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union /* INDEX */
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{
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struct
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{
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word index_reg : 5;
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word chip_ver : 2;
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word chip_id : 5;
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word unused : 4;
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} f;
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word all;
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} index;
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union /* DPYCTL */
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{
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struct
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{
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word non_interlaced : 1;
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word run : 1;
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word divise_select : 2;
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word serrated_sync : 1;
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word equalization_pulses : 1;
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word video : 1;
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word video_read : 1; /* read back bit */
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word clamp_pulse : 1;
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word autoinc : 1;
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word unused : 6;
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} f;
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word all;
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} dpyctl;
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union /* POLCTL */
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{
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struct
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{
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word hori_sync : 1;
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word vert_sync : 1;
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word composite_sync : 1;
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word composite_blank : 1;
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word burst_pulse : 1;
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word clamp_pulse : 1;
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word internal_pclk : 1;
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word pclk : 1;
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word unused : 8;
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} f;
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word all;
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} polctl;
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union /* EXTCTL */
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{
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struct
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{
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word external_sync : 1;
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word hori_reset : 1;
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word scan_mode : 2;
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word hori_reset_input_pol : 1;
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word vert_reset_input_pol : 1;
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word field_scan_mode : 1;
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word unused : 9;
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} f;
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word all;
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} extctl;
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word vtotal;
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word vsblnk;
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word veblnk;
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word vesync;
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word htotal;
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word hsblnk;
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word heblnk;
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word hesync;
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word vssyncs;
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word sethcnt;
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word setvcnt;
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word hsclmp;
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word heclmp;
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word hsbrst;
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word hebrst;
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word vsbrst;
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word vebrst;
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word vcount;
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word hcount;
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word scount;
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} PSG;
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/*************************** DAC'S STRUCTURE *****************************/
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typedef struct
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{
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byte col_addr_wr;
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byte col_data;
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byte rd_msk;
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byte col_addr_rd;
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byte cur_addr_wr;
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byte cur_data;
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union /* COMMAND REGISTER 0 */
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{
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struct
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{
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byte power_down_en : 1;
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byte dac_resolution : 1;
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byte red_sync_en : 1;
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byte green_sync_en : 1;
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byte blue_sync_en : 1;
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byte setup_en : 1;
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byte clk_disable : 1;
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byte reserved : 1;
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} f;
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byte all;
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} command0;
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byte cur_addr_rd;
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union /* COMMAND REGISTER 1 */
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{
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struct
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{
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byte switch_ctrl : 1;
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byte switch_en : 1;
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byte multiplexing_rate : 1;
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byte color_format : 1;
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byte tc_bypass : 1;
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byte bit_par_pixel_sel : 2;
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byte reserved : 1;
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} f;
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byte all;
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} command1;
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union /* COMMAND REGISTER 2 */
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{
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struct
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{
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byte cursor_mode_sel : 2;
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byte palette_index_sel : 1;
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byte disp_mode_sel : 1;
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byte clksel_en : 1;
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byte portsel_mask : 1;
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byte test_path_en : 1;
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byte sclk_disable : 1;
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} f;
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byte all;
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} command2;
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union /* COMMAND REGISTER 3 */
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{
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struct
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{
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byte msb_add_cntr : 2;
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byte curs_sel : 1;
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byte clk_muliplier : 1;
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byte reserved : 4;
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} f;
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byte all;
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} command3;
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union /* STATUS */
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{
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struct
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{
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byte color_comp_add : 2;
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byte rw_access_status : 1;
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byte sense : 1;
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byte rev : 2;
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byte id : 2;
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} f;
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byte all;
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} status;
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byte ram_data;
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byte cur_x_low;
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byte cur_x_hi;
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byte cur_y_low;
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byte cur_y_hi;
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} DAC;
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/*************************** ADC'S STRUCTURE *****************************/
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typedef struct
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{
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union /* COMMAND REGISTER */
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{
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struct
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{
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byte sync_detect_lev : 1;
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byte reserved : 1;
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byte color_out_sel : 2;
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byte sync_detect_sel : 3;
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byte digitize_sel : 1;
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} f;
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byte all;
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} cmd_reg;
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byte iout0;
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byte iout1;
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byte iout2;
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/* byte iout3;
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byte iout4;
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byte iout5;
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byte reserved; */
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} ADC;
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/*********************** ENC CONFIG'S STRUCTURE **************************/
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typedef struct
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{
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union /* CTRL REGISTER */
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{
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struct
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{
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word vafc_input : 1;
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word ntsc_en : 1;
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word filter_en : 1;
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word genclock_en : 1;
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word genclock_pol : 1;
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word vidrst_pol : 1;
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word vidrst_en : 1;
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word hi_reg_bt254 : 1;
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word denc_mode : 1;
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word alpha_sync_en : 1;
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word clr_sense : 1;
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word reserved : 3;
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word dac_sense : 1;
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word denc_sense : 1;
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} f;
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word all;
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} ctrl_reg;
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union /* ID REGISTER */
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{
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struct
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{
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word rev : 3;
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word ver : 2;
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word id : 3;
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word dum : 8;
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} f;
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word all;
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} id_reg;
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} BOARD;
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/*************************** GENERAL STRUCTURE ***************************/
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typedef struct
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{
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DENC denc;
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PSG psg;
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DAC dac;
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ADC adc;
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BOARD board;
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} ENC_CONFIG;
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