224 lines
8.6 KiB
C
224 lines
8.6 KiB
C
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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vga.h
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Abstract:
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This module contains the definitions for the code that implements the
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VGA device driver.
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Author:
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Environment:
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Kernel mode
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Revision History:
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--*/
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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#define MEM_VGA 0xA0000
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#define MEM_VGA_SIZE 0x20000
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//
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// Index in the access range sturture for video memory
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// !!! This must match the VgaAccessRange structure !!!
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// !!! Memory is in the structure, index 2 (3rd entry) !!!
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#define VGA_MEMORY 2
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//
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// VGA port-related definitions.
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//
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//
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// Port definitions for filling the ACCSES_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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//
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// VGA register definitions
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//
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// ports in monochrome mode
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#define CRTC_ADDRESS_PORT_MONO 0x0004 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x0005 // Data registers in mono mode
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#define FEAT_CTRL_WRITE_PORT_MONO 0x000A // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x000A // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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#define ATT_ADDRESS_PORT 0x0010 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x0010 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x3C0
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#define ATT_DATA_READ_PORT 0x0011 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x0012 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x0012 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x0014 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x0015 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x0016 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x0017 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x0017 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x0018 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x0019 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x001A // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x001C // Miscellaneous Output reg read
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// port
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#define GRAPH_ADDRESS_PORT 0x001E // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x001F // and Data registers
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#define CRTC_ADDRESS_PORT_COLOR 0x0024 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x0025 // Data registers in color mode
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x002A // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x002A // Input Status 1 register read
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// port in color mode
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// VGA indexed register indexes.
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define IND_START_ADRS_H 0x0C // index in CRTC of Start Address (high)
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#define IND_START_ADRS_L 0x0D // index in CRTC of Start Address (low)
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#define IND_LINE_COMPARE 0x18 // index in CRTC of Line Compare (bit7-0)
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#define IND_LINE_COMPARE8 0x07 // index in CRTC of Line Compare (bit8)
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#define IND_LINE_COMPARE9 0x09 // index in CRTC of Line Compare (bit9)
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#define IND_SET_RESET 0x00 // index of Set/Reset Plane Color Register in Graph Ctrl
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#define IND_COLOR_DONT_CARE 0x07 // index of Color Don't Care Register in Graph Ctrl
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// IND_DATA_ROTATE : index of Data Rotate reg in GC
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//
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#define DR_ROT_CNT 0x07 // Data Rotate Count
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#define DR_SET 0x00 // Data Unmodified
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#define DR_AND 0x08 // Data ANDed with latches
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#define DR_OR 0x10 // Data ORed with latches
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#define DR_XOR 0x18 // Data XORed with latches
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//
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// IND_GRAPH_MODE : index of Mode reg in Graph Ctlr
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//
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#define M_PROC_WRITE 0x00 // Write processor data rotated
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#define M_LATCH_WRITE 0x01 // Write latched data
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#define M_COLOR_WRITE 0x02 // Write processor data as color
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#define M_AND_WRITE 0x03 // Write (procdata AND bitmask)
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#define M_DATA_READ 0x00 // Read selected plane
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#define M_COLOR_READ 0x08 // Read color compare
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Highest valid palette register index
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//
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#define VIDEO_MAX_PALETTE_REGISTER 0x0F
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