753 lines
16 KiB
C
753 lines
16 KiB
C
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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vgadata.c
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Abstract:
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This module contains all the global data used by the VGA driver.
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "dderror.h"
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#include "devioctl.h"
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#include "miniport.h"
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#include "ntddvdeo.h"
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#include "video.h"
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#include "vga.h"
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#include "cmdcnst.h"
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#if defined(ALLOC_PRAGMA)
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#pragma data_seg("PAGE_DATA")
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#endif
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//
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// Global to make sure driver is only loaded once.
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//
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ULONG VgaLoaded = 0;
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#if DBG
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ULONG giControlCode;
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ULONG gaIOControlCode[MAX_CONTROL_HISTORY];
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#endif
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//
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// This structure describes to which ports access is required.
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//
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VIDEO_ACCESS_RANGE VgaAccessRange[] = {
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{
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VGA_BASE_IO_PORT, 0x00000000, // 64-bit linear base address
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// of range
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VGA_START_BREAK_PORT - VGA_BASE_IO_PORT + 1, // # of ports
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1, // range is in I/O space
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1, // range should be visible
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1 // range should be shareable
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},
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{
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VGA_END_BREAK_PORT, 0x00000000,
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VGA_MAX_IO_PORT - VGA_END_BREAK_PORT + 1,
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1,
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1,
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1
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},
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{
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MEM_VGA, 0x00000000,
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MEM_VGA_SIZE,
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0,
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1,
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1
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},
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// HACK Allow our standard VGA to be used with ATI cards:
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// ATI uses an extra IO port at location 1CE on pretty much all of its
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// video boards
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{
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0x000001CE, 0x00000000,
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2,
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1,
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1,
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1
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},
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// Another HACK to fix ATI problems. During GUI mode setup
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// Network detection may touch ports in the 0x2e8 to 0x2ef range. ATI
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// decodes these ports, and the video goes out of sync when network
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// detection runs.
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//
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// NOTE: We don't need to add this to validator routines since the
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// ATI bios won't touch these registers.
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{
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0x000002E8, 0x00000000,
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8,
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1,
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1,
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1
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}
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};
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//
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// Validator Port list.
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// This structure describes all the ports that must be hooked out of the V86
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// emulator when a DOS app goes to full-screen mode.
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// The structure determines to which routine the data read or written to a
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// specific port should be sent.
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//
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EMULATOR_ACCESS_ENTRY VgaEmulatorAccessEntries[] = {
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//
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// Traps for byte OUTs.
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//
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{
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0x000003b0, // range start I/O address
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0xC, // range length
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Uchar, // access size to trap
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS, // types of access to trap
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FALSE, // does not support string accesses
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(PVOID)VgaValidatorUcharEntry // routine to which to trap
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},
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{
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0x000003c0, // range start I/O address
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0x20, // range length
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Uchar, // access size to trap
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS, // types of access to trap
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FALSE, // does not support string accesses
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(PVOID)VgaValidatorUcharEntry // routine to which to trap
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},
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//
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// Traps for word OUTs.
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//
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{
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0x000003b0,
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0x06,
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Ushort,
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS,
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FALSE,
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(PVOID)VgaValidatorUshortEntry
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},
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{
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0x000003c0,
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0x10,
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Ushort,
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS,
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FALSE,
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(PVOID)VgaValidatorUshortEntry
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},
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//
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// Traps for dword OUTs.
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//
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{
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0x000003b0,
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0x03,
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Ulong,
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS,
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FALSE,
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(PVOID)VgaValidatorUlongEntry
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},
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{
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0x000003c0,
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0x08,
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Ulong,
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS,
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FALSE,
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(PVOID)VgaValidatorUlongEntry
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},
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//
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// ATI hack for port 1CE
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//
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{
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0x000001ce,
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0x2,
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Uchar,
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS,
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FALSE,
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(PVOID)VgaValidatorUcharEntry
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},
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{
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0x000001ce,
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0x1,
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Ushort,
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EMULATOR_READ_ACCESS | EMULATOR_WRITE_ACCESS,
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FALSE,
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(PVOID)VgaValidatorUshortEntry
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}
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};
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//
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// Used to trap only the sequncer and the misc output registers
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//
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VIDEO_ACCESS_RANGE MinimalVgaValidatorAccessRange[] = {
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{
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VGA_BASE_IO_PORT, 0x00000000,
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VGA_START_BREAK_PORT - VGA_BASE_IO_PORT + 1,
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1,
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1, // <- enable range IOPM so that it is not trapped.
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1
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},
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{
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VGA_END_BREAK_PORT, 0x00000000,
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VGA_MAX_IO_PORT - VGA_END_BREAK_PORT + 1,
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1,
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1,
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1
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},
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{
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VGA_BASE_IO_PORT + MISC_OUTPUT_REG_WRITE_PORT, 0x00000000,
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0x00000001,
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1,
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0,
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1
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},
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{
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VGA_BASE_IO_PORT + SEQ_ADDRESS_PORT, 0x00000000,
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0x00000002,
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1,
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0,
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1
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},
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// HACK Allow our standard VGA to be used with ATI cards:
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// ATI uses an extra IO port at location 1CE on pretty much all of its
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// video boards
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{
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0x000001CE, 0x00000000,
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2,
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1,
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1,
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1
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}
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};
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//
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// Used to trap all registers
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//
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VIDEO_ACCESS_RANGE FullVgaValidatorAccessRange[] = {
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{
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VGA_BASE_IO_PORT, 0x00000000,
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VGA_START_BREAK_PORT - VGA_BASE_IO_PORT + 1,
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1,
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0, // <- disable range in the IOPM so that it is trapped.
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1
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},
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{
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VGA_END_BREAK_PORT, 0x00000000,
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VGA_MAX_IO_PORT - VGA_END_BREAK_PORT + 1,
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1,
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0,
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1
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},
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// HACK Allow our standard VGA to be used with ATI cards:
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// ATI uses an extra IO port at location 1CE on pretty much all of its
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// video boards
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{
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0x000001CE, 0x00000000,
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2,
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1,
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0,
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1
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}
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};
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//
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// Color graphics mode 0x12, 640x480 16 colors.
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#ifndef INT10_MODE_SET
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//
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USHORT VGA_640x480[] = {
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OWM, // start sync reset program up sequencer
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SEQ_ADDRESS_PORT,
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5,
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0x0100,0x0101,0x0f02,0x0003,0x0604,
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OB,
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MISC_OUTPUT_REG_WRITE_PORT, // Misc output register
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0xe3,
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OW, // Set chain mode in sync reset
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GRAPH_ADDRESS_PORT,
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0x0506,
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OB, // EndSyncResetCmd
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SEQ_ADDRESS_PORT,
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IND_SYNC_RESET,
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OB,
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SEQ_DATA_PORT,
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END_SYNC_RESET_VALUE,
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OW, // Unlock CRTC registers 0-7
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CRTC_ADDRESS_PORT_COLOR,
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0x0511,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS, // count
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0, // start index
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0x5F,0x4F,0x50,0x82,0x54,0x80,0x0B,0x3E,0x00,0x40,0x0,0x0,0x0,0x0,0x0,0x0,
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0xEA,0x8C,0xDF,0x28,0x0,0xE7,0x4,0xE3,0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, // program attribute controller registers
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ATT_ADDRESS_PORT, // port
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VGA_NUM_ATTRIB_CONT_PORTS, // count
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0, // start index
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0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3A,0x3B,0x3C,0x3D,0x3E,0x3F,
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0x01,0x0,0x0F,0x0,0x0,
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METAOUT+INDXOUT, // program graphics controller registers
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GRAPH_ADDRESS_PORT, // port
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VGA_NUM_GRAPH_CONT_PORTS, // count
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0, // start index
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0x00,0x0,0x0,0x0,0x0,0x0,0x05,0x0F,0x0FF,
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OB, // DAC mask registers
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DAC_PIXEL_MASK_PORT,
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0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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VIDEO_ENABLE,
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EOD
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};
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//
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// Color text mode, 720x480
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//
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USHORT VGA_TEXT_0[] = {
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OWM,
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SEQ_ADDRESS_PORT,
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5,
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0x0100,0x0001,0x0302,0x0003,0x0204, // program up sequencer
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OB,
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MISC_OUTPUT_REG_WRITE_PORT,
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0x67,
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OW,
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GRAPH_ADDRESS_PORT,
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0x0e06,
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// EndSyncResetCmd
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OB,
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SEQ_ADDRESS_PORT,
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IND_SYNC_RESET,
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OB,
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SEQ_DATA_PORT,
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END_SYNC_RESET_VALUE,
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OW,
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CRTC_ADDRESS_PORT_COLOR,
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0x0E11,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS, // count
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0, // start index
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0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4f,0xd,0xe,0x0,0x0,0x0,0x0,
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0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, //
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ATT_ADDRESS_PORT, // port
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VGA_NUM_ATTRIB_CONT_PORTS, // count
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0, // start index
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0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
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0x04,0x0,0x0F,0x8,0x0,
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METAOUT+INDXOUT, //
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GRAPH_ADDRESS_PORT, // port
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VGA_NUM_GRAPH_CONT_PORTS, // count
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0, // start index
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0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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VIDEO_ENABLE,
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EOD
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};
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#endif//!INT10_MODE_SET
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//
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// Color text mode, 640x480
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//
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USHORT VGA_TEXT_1[] = {
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OWM,
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SEQ_ADDRESS_PORT,
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5,
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0x0100,0x0101,0x0302,0x0003,0x0204, // program up sequencer
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OB,
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MISC_OUTPUT_REG_WRITE_PORT,
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0xa3,
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OW,
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GRAPH_ADDRESS_PORT,
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0x0e06,
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// EndSyncResetCmd
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OB,
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SEQ_ADDRESS_PORT,
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IND_SYNC_RESET,
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OB,
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SEQ_DATA_PORT,
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END_SYNC_RESET_VALUE,
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OW,
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CRTC_ADDRESS_PORT_COLOR,
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0x0511,
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METAOUT+INDXOUT, // program crtc registers
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CRTC_ADDRESS_PORT_COLOR,
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VGA_NUM_CRTC_PORTS, // count
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0, // start index
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0x5F,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,0x00,0x4d,0xb,0xc,0x0,0x0,0x0,0x0,
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0x83,0x85,0x5d,0x28,0x1f,0x63,0xba,0xa3,0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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METAOUT+ATCOUT, //
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ATT_ADDRESS_PORT, // port
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VGA_NUM_ATTRIB_CONT_PORTS, // count
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0, // start index
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0x0,0x1,0x2,0x3,0x4,0x5,0x14,0x7,0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
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0x00,0x0,0x0F,0x0,0x0,
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METAOUT+INDXOUT, //
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GRAPH_ADDRESS_PORT, // port
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VGA_NUM_GRAPH_CONT_PORTS, // count
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0, // start index
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0x00,0x0,0x0,0x0,0x0,0x10,0x0e,0x0,0x0FF,
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OB,
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DAC_PIXEL_MASK_PORT,
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0xFF,
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IB, // prepare atc for writing
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INPUT_STATUS_1_COLOR,
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OB, // turn video on.
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ATT_ADDRESS_PORT,
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VIDEO_ENABLE,
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EOD
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};
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USHORT ModeX200[] = {
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OW,
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SEQ_ADDRESS_PORT,
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0x0604,
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OWM,
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CRTC_ADDRESS_PORT_COLOR,
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2,
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0xe317,
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0x0014,
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EOD
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};
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USHORT ModeX240[] = {
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OWM,
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SEQ_ADDRESS_PORT,
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2,
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0x0604,
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0x0100,
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OB,
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MISC_OUTPUT_REG_WRITE_PORT,
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0xe3,
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OW,
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SEQ_ADDRESS_PORT,
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0x0300,
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OB,
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CRTC_ADDRESS_PORT_COLOR,
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0x11,
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METAOUT+MASKOUT,
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CRTC_DATA_PORT_COLOR,
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0x7f, 0x00,
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OWM,
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CRTC_ADDRESS_PORT_COLOR,
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10,
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0x0d06,
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0x3e07,
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0x4109,
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0xea10,
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0xac11,
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0xdf12,
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0x0014,
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0xe715,
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0x0616,
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0xe317,
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OW,
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SEQ_ADDRESS_PORT,
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0x0f02,
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EOD
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};
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USHORT ModeXDoubleScans[] = {
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OW, CRTC_ADDRESS_PORT_COLOR, 0x4009,
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EOD
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};
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//
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// We will dynamically build a list of supported modes, based on the VESA
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// modes the card supports.
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//
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PVIDEOMODE VgaModeList;
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//
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// Video mode table - contains information and commands for initializing each
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// mode. These entries must correspond with those in VIDEO_MODE_VGA. The first
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// entry is commented; the rest follow the same format, but are not so
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// heavily commented.
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//
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VIDEOMODE ModesVGA[] = {
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//
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// Mode index 0
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// Color text mode 3, 720x400, 9x16 char cell (VGA).
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//
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{
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VIDEO_MODE_COLOR |
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VIDEO_MODE_BANKED, // flags that this mode is a color mode, but not graphics
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4, // four planes
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1, // one bit of color per plane
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80, 25, // 80x25 text resolution
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720, 400, // 720x400 pixels on screen
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1, // Frequency in Hz
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160, 0x10000, // 160 bytes per scan line, 64K of CPU-addressable bitmap
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NoBanking, // no banking supported or needed in this mode
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#ifdef INT10_MODE_SET
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0x3,
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||
#else
|
||
VGA_TEXT_0, // pointer to the command strings
|
||
#endif
|
||
MEM_VGA, 0x18000, 0x08000, MEM_VGA_SIZE,
|
||
720
|
||
},
|
||
|
||
//
|
||
// Mode index 1.
|
||
// Color text mode 3, 640x350, 8x14 char cell (EGA).
|
||
//
|
||
|
||
{
|
||
VIDEO_MODE_COLOR | VIDEO_MODE_BANKED, 4, 1, 80, 25, 640, 350, 1, 160, 0x10000, NoBanking,
|
||
#ifdef INT10_MODE_SET
|
||
0x3,
|
||
#else
|
||
VGA_TEXT_1, // pointer to the command strings
|
||
#endif
|
||
MEM_VGA, 0x18000, 0x08000, MEM_VGA_SIZE,
|
||
640
|
||
},
|
||
|
||
//
|
||
//
|
||
// Mode index 2
|
||
// Standard VGA Color graphics mode 0x12, 640x480 16 colors.
|
||
//
|
||
|
||
{
|
||
VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_BANKED, 4, 1, 80, 30,
|
||
640, 480, 1, 80, 0x10000, NoBanking,
|
||
#ifdef INT10_MODE_SET
|
||
0x12,
|
||
#else
|
||
VGA_640x480, // pointer to the command strings
|
||
#endif
|
||
MEM_VGA, 0x0000, MEM_VGA_SIZE, MEM_VGA_SIZE,
|
||
640
|
||
},
|
||
|
||
|
||
#ifdef INT10_MODE_SET
|
||
|
||
//
|
||
// 320x200 256 colors ModeX
|
||
//
|
||
|
||
{ VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_BANKED, 8, 1, 0, 0,
|
||
320, 200, 70, 80, 0x10000, NoBanking,
|
||
0x13,
|
||
MEM_VGA, 0x0000, MEM_VGA_SIZE, MEM_VGA_SIZE,
|
||
320
|
||
},
|
||
|
||
//
|
||
// 320x240 256 colors ModeX
|
||
//
|
||
|
||
{ VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_BANKED, 8, 1, 0, 0,
|
||
320, 240, 60, 80, 0x10000, NoBanking,
|
||
0x13,
|
||
MEM_VGA, 0x0000, MEM_VGA_SIZE, MEM_VGA_SIZE,
|
||
320
|
||
},
|
||
|
||
//
|
||
// 320x400 256 colors ModeX
|
||
//
|
||
|
||
{ VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_BANKED, 8, 1, 0, 0,
|
||
320, 400, 70, 80, 0x10000, NoBanking,
|
||
0x13,
|
||
MEM_VGA, 0x0000, MEM_VGA_SIZE,
|
||
320
|
||
},
|
||
|
||
//
|
||
// 320x480 256 colors ModeX
|
||
//
|
||
|
||
{ VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_BANKED, 8, 1, 0, 0,
|
||
320, 480, 60, 80, 0x10000, NoBanking,
|
||
0x13,
|
||
MEM_VGA, 0x0000, MEM_VGA_SIZE,
|
||
320
|
||
},
|
||
|
||
//
|
||
// 800x600 16 colors.
|
||
//
|
||
// NOTE: This must be the last mode in our static mode table.
|
||
//
|
||
|
||
{ VIDEO_MODE_COLOR | VIDEO_MODE_GRAPHICS | VIDEO_MODE_BANKED, 4, 1, 100, 37,
|
||
800, 600, 1, 100, 0x10000, NoBanking,
|
||
0x01024F02,
|
||
MEM_VGA, 0x0000, MEM_VGA_SIZE, MEM_VGA_SIZE,
|
||
800
|
||
},
|
||
|
||
#endif
|
||
|
||
};
|
||
|
||
ULONG NumVideoModes = sizeof(ModesVGA) / sizeof(VIDEOMODE);
|
||
|
||
//
|
||
//
|
||
// Data used to set the Graphics and Sequence Controllers to put the
|
||
// VGA into a planar state at A0000 for 64K, with plane 2 enabled for
|
||
// reads and writes, so that a font can be loaded, and to disable that mode.
|
||
//
|
||
|
||
// Settings to enable planar mode with plane 2 enabled.
|
||
//
|
||
|
||
USHORT EnableA000Data[] = {
|
||
OWM,
|
||
SEQ_ADDRESS_PORT,
|
||
1,
|
||
0x0100,
|
||
|
||
OWM,
|
||
GRAPH_ADDRESS_PORT,
|
||
3,
|
||
0x0204, // Read Map = plane 2
|
||
0x0005, // Graphics Mode = read mode 0, write mode 0
|
||
0x0406, // Graphics Miscellaneous register = A0000 for 64K, not odd/even,
|
||
// graphics mode
|
||
OWM,
|
||
SEQ_ADDRESS_PORT,
|
||
3,
|
||
0x0402, // Map Mask = write to plane 2 only
|
||
0x0404, // Memory Mode = not odd/even, not full memory, graphics mode
|
||
0x0300, // end sync reset
|
||
EOD
|
||
};
|
||
|
||
//
|
||
// Settings to disable the font-loading planar mode.
|
||
//
|
||
|
||
USHORT DisableA000Color[] = {
|
||
OWM,
|
||
SEQ_ADDRESS_PORT,
|
||
1,
|
||
0x0100,
|
||
|
||
OWM,
|
||
GRAPH_ADDRESS_PORT,
|
||
3,
|
||
0x0004, 0x1005, 0x0E06,
|
||
|
||
OWM,
|
||
SEQ_ADDRESS_PORT,
|
||
3,
|
||
0x0302, 0x0204, 0x0300, // end sync reset
|
||
EOD
|
||
|
||
};
|
||
|
||
|
||
#if defined(ALLOC_PRAGMA)
|
||
#pragma data_seg()
|
||
#endif
|