576 lines
14 KiB
C
576 lines
14 KiB
C
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/*++
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Copyright (c) 1999-2001 Microsoft Corporation. All Rights Reserved.
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Module Name:
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apic.c
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Abstract:
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This module contains global variables and functions used to program the local APIC.
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The local APIC resides on the processor die of newer Intel and AMD processors. It is
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used to control various interrupt sources both local and external to the processor.
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Author:
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Joseph Ballantyne
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Environment:
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Kernel Mode
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Revision History:
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--*/
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#include "common.h"
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#include "apic.h"
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#include "irq.h"
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#include "msr.h"
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#include "rtp.h"
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#include "rt.h"
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#include "x86.h"
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#include "rtexcept.h"
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#ifndef UNDER_NT
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#include <vmm.h>
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#endif
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#pragma LOCKED_DATA
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// These globals contain addresses pointing at various local APIC registers.
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// They must be in locked memory as they will be used to program the local APIC
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// while in interrupt service routines.
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CHAR *ApicBase=NULL;
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volatile ULONG *ApicPerfInterrupt=NULL;
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volatile ULONG *ApicTimerInterrupt=NULL;
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volatile ULONG *ApicNmiInterrupt=NULL;
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volatile ULONG *ApicIntrInterrupt=NULL;
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// WARNING!!! Do NOT change the ApicTimerVector or ApicErrorVector default
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// settings to a different define, without also updating HookWindowsInterrupts
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// in rt.c! Otherwise any local apic errors will jump to some unknown and
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// incorrect interrupt handler instead of our own - since we will not have
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// hooked the error vector IDT entry.
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// Also make sure you also update rtexcept.c appropriately as well if any
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// of the below variables are initialized with different defines.
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ULONG ApicTimerVector=MASKABLEIDTINDEX;
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ULONG ApicPerfVector=RTINTERRUPT;
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ULONG ApicErrorVector=APICERRORIDTINDEX;
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ULONG ApicSpuriousVector=APICSPURIOUSIDTINDEX;
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extern ID OriginalApicSpuriousVector;
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NTSTATUS
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HookInterrupt (
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ULONG index,
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ID *originalvector,
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VOID (* handler)(VOID)
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);
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#pragma PAGEABLE_DATA
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#pragma PAGEABLE_CODE
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#ifndef UNDER_NT
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#pragma warning ( disable : 4035 )
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#endif
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PCHAR
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MapPhysToLinear (
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VOID *physicaladdress,
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ULONG numbytes,
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ULONG flags
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)
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/*++
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Routine Description:
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This routine is a wrapper for OS functions that map physical memory to linear address
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space. On Win9x it wraps MapPhysToLinear, on WinNT it wraps MmMapIoSpace.
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Arguments:
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physicaladdress - Supplies the physical address to be mapped into linear address space.
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numbytes - Supplies the size of the block of physical memory to be mapped.
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flags - Supplies flags controlling the characteristics of the linear/virtual memory.
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Return Value:
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Since this routine is really just a wrapper for OS functions on
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Win9x and WinNT, the return value differs depending on the OS.
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On both platforms if the mapping is successful, the return value is the linear
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address of the mapped physical address.
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On Win9x if the mapping fails, the function returns (-1).
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On WinNT if the mapping fails, the function returns NULL.
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Platform independent callers MUST check for returns of EITHER (-1) or NULL
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when checking for failure.
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--*/
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{
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#ifdef UNDER_NT
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PHYSICAL_ADDRESS address;
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address.QuadPart=(ULONGLONG)physicaladdress;
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return MmMapIoSpace(address, numbytes, flags);
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#else
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__asm push flags
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__asm push numbytes
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__asm push physicaladdress
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VMMCall( _MapPhysToLinear );
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__asm add esp,12
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#endif
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}
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#ifndef UNDER_NT
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#pragma warning ( default : 4035 )
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#endif
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BOOL
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InitializeAPICBase (
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VOID
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)
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/*++
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Routine Description:
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If this routine has already run successfully, then it simply returns TRUE.
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If not, then it first reads the physical address that the local APIC
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is mapped to. Then it maps that physical address to virtual memory
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and saves the virtual memory location in the global ApicBase. If the
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mapping fails, then it returns FALSE, otherwise it loads globals that
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point to specific local APIC interrupt control registers and returns
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TRUE.
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WARNING: Currently this routine ASSUMES processor support of the
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Intel local APIC mapping MSR.
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Arguments:
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None.
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Return Value:
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TRUE if local APIC already mapped, or if it is mapped successfully during the call.
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FALSE if mapping the local APIC fails.
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--*/
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{
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// If local APIC already mapped, simply return TRUE.
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if (ApicBase!=NULL && ApicBase!=(CHAR *)(-1)) {
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return TRUE;
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}
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// Read the local APIC physical location.
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// NOTE: This next line assumes all machines this code runs on support the
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// local APIC mapping MSR that PII and newer Intel processors have.
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// Code that calls this function MUST properly screen for manufacturer,
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// processor family, and local apic support before calling this function.
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ApicBase=(CHAR *)(ReadIntelMSR(APICBASE)&~(0xfff));
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// Map the physical address to a virtual address.
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ApicBase=MapPhysToLinear(ApicBase, 4096, 0);
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// Return false if the mapping failed.
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if (ApicBase==(CHAR *)(-1) || ApicBase==NULL) {
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return FALSE;
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}
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// Mapping succeeded, so load global interrupt control register locations
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// and return TRUE.
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ApicPerfInterrupt=(ULONG *)(ApicBase+APICPERF);
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ApicTimerInterrupt=(ULONG *)(ApicBase+APICTIMER);
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ApicNmiInterrupt=(ULONG *)(ApicBase+APICNMI);
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ApicIntrInterrupt=(ULONG *)(ApicBase+APICINTR);
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return TRUE;
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}
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BOOL
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MachineHasAPIC (
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VOID
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)
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/*++
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Routine Description:
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Check the processor manufacturer, family, and the local APIC feature bit, and
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then call InitializeAPICBase on supported processors.
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Arguments:
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None.
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Return Value:
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FALSE for unsupported processor manufacturers and families and for processors
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without the local APIC feature bit set.
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If the manufacturer and processor family are supported and the processor sets
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the local APIC feature bit, then we call InitializeAPICBase and return the
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value returned by that function.
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--*/
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{
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if (CPUManufacturer==INTEL && CPUFamily>=6 && (CPUFeatures&0x20)) {
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return InitializeAPICBase();
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}
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if (CPUManufacturer==AMD && CPUFamily>=6 && (CPUFeatures&0x20)) {
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return InitializeAPICBase();
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}
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return FALSE;
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}
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#pragma LOCKED_CODE
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#pragma LOCKED_DATA
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#if 0
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__inline
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VOID
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GenerateLocalHardwareInterrupt (
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ULONG interrupt
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)
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/*++
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Routine Description:
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This routine can be used to generate what will appear to be a hardware interrupt.
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The local APIC is used to send the passed interrupt vector number to itself
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and will then handle the interrupt by invoking specified interrupt vector to
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handle the interrupt. I do NOT know whether this will work at all. It may or may not
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work with interrupt handlers that normally handle interrupts coming from an external
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IO APIC, and it may or may not work with interrupt handlers that normally handle
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interrupts coming through an external PIC. It seemed like an idea with interesting
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possibilities, so I wrote the code. It is NOT currently used. Note that for code
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already running in ring 0 on x86 processors, if you just want to run an arbitrary
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interrupt handler, it is much faster to just simulate the interrupt by running
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an __asm int x instruction.
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WARNING: This function does NOT currently wait until the interrupt is delivered
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before returning.
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Arguments:
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interrupt - Contains the interrupt vector number of the interrupt to be simulated.
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Return Value:
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None.
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--*/
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{
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// First write this machines local apic ID into the destination register of the ICR.
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// We must do this with interrupts disabled so that it is safe on NT multiproc
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// machines. Otherwise we could read the APIC ID for one processor and be switched
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// out and load it into a different processors register.
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SaveAndDisableMaskableInterrupts();
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WriteAPIC(APICICRHIGH,ReadAPIC(APICID));
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WriteAPIC(APICICRLOW,ASSERTIRQ|interrupt);
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RestoreMaskableInterrupts();
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}
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#endif
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BOOL
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TurnOnLocalApic (
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VOID
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)
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{
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if (!(CPUFeatures&0x20)) {
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return FALSE;
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}
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{
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ULONGLONG apicbaseaddress;
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// Make sure that APIC turned on by MSRs.
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apicbaseaddress=ReadIntelMSR(APICBASE);
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if (!(apicbaseaddress&0x800)) { // Apic is turned off.
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// First disable all interrupts.
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SaveAndDisableMaskableInterrupts();
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// Try turning it back on. Intel claims this doesn't work. It does.
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apicbaseaddress|=0x800;
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WriteIntelMSR(APICBASE, apicbaseaddress);
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// The following code should only be run in the case when the local APIC was
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// not turned on and we then turned it on.
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// Now check if the local APIC is turned on. If so, then set it up.
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if (ReadIntelMSR(APICBASE)&0x800) {
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// Local APIC is on.
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// Hook the APIC spurious interrupt vector if we have not hooked it before.
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if (*(PULONGLONG)&OriginalApicSpuriousVector==0 &&
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HookInterrupt(ApicSpuriousVector, &OriginalApicSpuriousVector, RtpLocalApicSpuriousHandler)!=STATUS_SUCCESS) {
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RestoreMaskableInterrupts();
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return FALSE;
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}
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// Now enable the APIC itself.
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// This also loads the spurious interrupt vector.
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WriteAPIC(APICSPURIOUS,(ReadAPIC(APICSPURIOUS)&0xfffffc00)|0x100|APICSPURIOUSIDTINDEX);
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// Now setup INTR.
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// Unmasked, ExtINT.
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WriteAPIC(APICINTR,(ReadAPIC(APICINTR)&0xfffe58ff)|EXTINT);
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// Now setup NMI.
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// Masked, NMI.
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// Leave external NMI enabled.
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WriteAPIC(APICNMI,(ReadAPIC(APICNMI)&0xfffe58ff)|NMI);
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// Now reenable interrupts.
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RestoreMaskableInterrupts();
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return TRUE;
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}
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else {
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// Local APIC could not be turned on with the MSRs!
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// This WILL happen on some mobile parts.
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// Now reenable interrupts.
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RestoreMaskableInterrupts();
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dprintf(("RealTime Executive could not enable local APIC. RT NOT RUNNING!"));
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return FALSE;
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}
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}
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else { // Local APIC is already turned on!
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// This will happen for HALs that use the local APIC. (mp, ACPI)
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// We should not touch the spurious, ExtINT, or NMI vectors in this case.
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// We do however read the settings out of the local APIC for the local timer
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// interrupt vector, and the performance counter interrupt vector. That
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// way we use the same vectors as the HAL initially programmed. (Except
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// that we do set the NMI flag in the performance counter interrupt, so
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// it actually uses interrupt vector 2.)
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ApicTimerVector=ReadAPIC(APICTIMER)&VECTORMASK;
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#ifdef MASKABLEINTERRUPT
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ApicPerfVector=ReadAPIC(APICPERF)&VECTORMASK;
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#else
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ApicPerfVector=NMI|(ReadAPIC(APICPERF)&VECTORMASK);
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#endif
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// We also read the error and spurious vector locations since we need
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// them when setting up our private IDTs.
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ApicErrorVector=ReadAPIC(APICERROR)&VECTORMASK;
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ApicSpuriousVector=ReadAPIC(APICSPURIOUS)&VECTORMASK;
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// Make sure the vectors we just read are valid. If not, then load them with
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// our defaults. These vectors should never be invalid if the local APIC
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// was turned on. The only way we will hit this case is if the BIOS turns
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// on the local APIC, but then a HAL without local apic support does not
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// turn OFF the local apic.
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if (!ApicTimerVector) {
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Trap();
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ApicTimerVector=MASKABLEIDTINDEX;
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}
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if (!ApicPerfVector) {
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Trap();
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ApicPerfVector=RTINTERRUPT;
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}
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if (!ApicErrorVector) {
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Trap();
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ApicErrorVector=APICERRORIDTINDEX;
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}
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if (!ApicSpuriousVector) {
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Trap();
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ApicSpuriousVector=APICSPURIOUSIDTINDEX;
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}
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return TRUE;
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}
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}
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}
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BOOL
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EnableAPIC (
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VOID
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)
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/*++
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Routine Description:
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This routine will enable the local APIC on processors it knows are supported.
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We check if the processor manufacturer and family are supported. If so we
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call TurnOnLocalApic to enable the local apic on the processor.
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Arguments:
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None.
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Return Value:
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FALSE if processor manufacturer and family are not explicitly supported.
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If the manufacturer and processor family are supported then we call
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TurnOnLocalApic and return the value returned by that function.
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--*/
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{
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// Is manufaturer supported?
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switch (CPUManufacturer) {
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case INTEL:
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// Check the processor family code for Intel.
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switch (CPUFamily) {
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case 6: // PII, PIII, Celeron
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case 0xf: // P4
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return TurnOnLocalApic();
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break;
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default:
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break;
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}
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break;
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case AMD:
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// Check the processor family code for AMD.
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switch (CPUFamily) {
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case 6: // Athlon, Duron
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return TurnOnLocalApic();
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break;
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default:
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break;
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}
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break;
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default:
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break;
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}
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return FALSE;
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}
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#pragma PAGEABLE_CODE
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#pragma PAGEABLE_DATA
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