292 lines
9.3 KiB
C
292 lines
9.3 KiB
C
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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ia64 psr
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Abstract:
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KD Extension Api
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Author:
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Thierry Fevrier (v-thief)
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Environment:
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User Mode.
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Revision History:
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--*/
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#include "precomp.h"
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#pragma hdrstop
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typedef struct _EM_PSR {
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unsigned __int64 reserved0:1; // 0 : reserved
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unsigned __int64 be:1; // 1 : Big-Endian
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unsigned __int64 up:1; // 2 : User Performance monitor enable
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unsigned __int64 ac:1; // 3 : Alignment Check
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unsigned __int64 mfl:1; // 4 : Lower (f2 .. f31) floating-point registers written
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unsigned __int64 mfh:1; // 5 : Upper (f32 .. f127) floating-point registers written
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unsigned __int64 reserved1:7; // 6-12 : reserved
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unsigned __int64 ic:1; // 13 : Interruption Collection
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unsigned __int64 i:1; // 14 : Interrupt Bit
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unsigned __int64 pk:1; // 15 : Protection Key enable
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unsigned __int64 reserved2:1; // 16 : reserved
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unsigned __int64 dt:1; // 17 : Data Address Translation
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unsigned __int64 dfl:1; // 18 : Disabled Floating-point Low register set
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unsigned __int64 dfh:1; // 19 : Disabled Floating-point High register set
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unsigned __int64 sp:1; // 20 : Secure Performance monitors
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unsigned __int64 pp:1; // 21 : Privileged Performance monitor enable
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unsigned __int64 di:1; // 22 : Disable Instruction set transition
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unsigned __int64 si:1; // 23 : Secure Interval timer
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unsigned __int64 db:1; // 24 : Debug Breakpoint fault
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unsigned __int64 lp:1; // 25 : Lower Privilege transfer trap
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unsigned __int64 tb:1; // 26 : Taken Branch trap
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unsigned __int64 rt:1; // 27 : Register stack translation
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unsigned __int64 reserved3:4; // 28-31 : reserved
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unsigned __int64 cpl:2; // 32;33 : Current Privilege Level
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unsigned __int64 is:1; // 34 : Instruction Set
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unsigned __int64 mc:1; // 35 : Machine Abort Mask
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unsigned __int64 it:1; // 36 : Instruction address Translation
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unsigned __int64 id:1; // 37 : Instruction Debug fault disable
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unsigned __int64 da:1; // 38 : Disable Data Access and Dirty-bit faults
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unsigned __int64 dd:1; // 39 : Data Debug fault disable
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unsigned __int64 ss:1; // 40 : Single Step enable
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unsigned __int64 ri:2; // 41;42 : Restart Instruction
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unsigned __int64 ed:1; // 43 : Exception Deferral
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unsigned __int64 bn:1; // 44 : register Bank
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unsigned __int64 ia:1; // 45 : Disable Instruction Access-bit faults
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unsigned __int64 reserved4:18; // 46-63 : reserved
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} EM_PSR, *PEM_PSR;
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typedef EM_PSR EM_IPSR;
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typedef EM_IPSR *PEM_IPSR;
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typedef unsigned __int64 EM_REG;
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typedef EM_REG *PEM_REG;
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#define EM_REG_BITS (sizeof(EM_REG) * 8)
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// IA64 only
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typedef enum _DISPLAY_MODE {
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DISPLAY_MIN = 0,
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DISPLAY_DEFAULT = DISPLAY_MIN,
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DISPLAY_MED = 1,
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DISPLAY_MAX = 2,
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DISPLAY_FULL = DISPLAY_MAX
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} DISPLAY_MODE;
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typedef struct _EM_REG_FIELD {
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const char *SubName;
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const char *Name;
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unsigned long Length;
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unsigned long Shift;
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} EM_REG_FIELD, *PEM_REG_FIELD;
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//
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// EmPsrFields: EM register fields for the Processor Status Register.
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//
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EM_REG_FIELD EmPsrFields[] = {
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{ "rv", "reserved0" , 0x1, 0 }, // 0
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{ "be", "Big-Endian" , 0x1, 1 }, // 1
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{ "up", "User Performance monitor enable", 0x1, 2 }, // 2
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{ "ac", "Alignment Check", 0x1, 3 }, // 3
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{ "mfl", "Lower floating-point registers written", 0x1, 4 }, // 4
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{ "mfh", "Upper floating-point registers written", 0x1, 5 }, // 5
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{ "rv", "reserved1", 0x7, 6 }, // 6-12
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{ "ic", "Interruption Collection", 0x1, 13 }, // 13
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{ "i", "Interrupt enable", 0x1, 14 }, // 14
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{ "pk", "Protection Key enable", 0x1, 15 }, // 15
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{ "rv", "reserved2", 0x1, 16 }, // 16
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{ "dt", "Data Address Translation enable", 0x1, 17 }, // 17
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{ "dfl", "Disabled Floating-point Low register set", 0x1, 18 }, // 18
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{ "dfh", "Disabled Floating-point High register set", 0x1, 19 }, // 19
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{ "sp", "Secure Performance monitors", 0x1, 20 }, // 20
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{ "pp", "Privileged Performance monitor enable", 0x1, 21 }, // 21
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{ "di", "Disable Instruction set transition", 0x1, 22 }, // 22
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{ "si", "Secure Interval timer", 0x1, 23 }, // 23
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{ "db", "Debug Breakpoint fault enable", 0x1, 24 }, // 24
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{ "lp", "Lower Privilege transfer trap enable", 0x1, 25 }, // 25
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{ "tb", "Taken Branch trap enable", 0x1, 26 }, // 26
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{ "rt", "Register stack translation enable", 0x1, 27 }, // 27
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{ "rv", "reserved3", 0x4, 28 }, // 28-31
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{ "cpl", "Current Privilege Level", 0x2, 32 }, // 32-33
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{ "is", "Instruction Set", 0x1, 34 }, // 34
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{ "mc", "Machine Abort Mask delivery disable", 0x1, 35 }, // 35
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{ "it", "Instruction address Translation enable", 0x1, 36 }, // 36
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{ "id", "Instruction Debug fault disable", 0x1, 37 }, // 37
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{ "da", "Disable Data Access and Dirty-bit faults", 0x1, 38 }, // 38
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{ "dd", "Data Debug fault disable", 0x1, 39 }, // 39
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{ "ss", "Single Step enable", 0x1, 40 }, // 40
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{ "ri", "Restart Instruction", 0x2, 41 }, // 41-42
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{ "ed", "Exception Deferral", 0x1, 43 }, // 43
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{ "bn", "register Bank", 0x1, 44 }, // 44
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{ "ia", "Disable Instruction Access-bit faults", 0x1, 45 }, // 45
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{ "rv", "reserved4", 0x12, 46 } // 46-63
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};
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VOID
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DisplayFullEmRegField(
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ULONG64 EmRegValue,
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EM_REG_FIELD EmRegFields[],
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ULONG Field
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)
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{
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dprintf( "\n %3.3s : %I64x : %-s",
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EmRegFields[Field].SubName,
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(EmRegValue >> EmRegFields[Field].Shift) & ((1 << EmRegFields[Field].Length) - 1),
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EmRegFields[Field].Name
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);
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return;
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} // DisplayFullEmRegField()
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VOID
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DisplayFullEmReg(
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IN ULONG64 Val,
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IN EM_REG_FIELD EmRegFields[],
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IN DISPLAY_MODE DisplayMode
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)
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{
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ULONG i, j;
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i = j = 0;
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if ( DisplayMode >= DISPLAY_MAX ) {
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while( j < EM_REG_BITS ) {
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DisplayFullEmRegField( Val, EmRegFields, i );
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j += EmRegFields[i].Length;
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i++;
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}
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}
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else {
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while( j < EM_REG_BITS ) {
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if ( !strstr(EmRegFields[i].Name, "reserved" ) &&
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!strstr(EmRegFields[i].Name, "ignored" ) ) {
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DisplayFullEmRegField( Val, EmRegFields, i );
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}
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j += EmRegFields[i].Length;
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i++;
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}
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}
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dprintf("\n");
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return;
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} // DisplayFullEmReg()
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VOID
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DisplayPsrIA64(
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IN const PCHAR Header,
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IN EM_PSR EmPsr,
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IN DISPLAY_MODE DisplayMode
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)
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{
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dprintf("%s", Header ? Header : "" );
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if ( DisplayMode >= DISPLAY_MED ) {
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DisplayFullEmReg( *((PULONG64) &EmPsr), EmPsrFields, DisplayMode );
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}
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else {
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dprintf(
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"ia bn ed ri ss dd da id it mc is cpl rt tb lp db\n\t\t "
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"%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x\n\t\t"
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"si di pp sp dfh dfl dt pk i ic | mfh mfl ac up be\n\t\t "
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"%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x | %1I64x %1I64x %1I64x %1I64x %1I64x\n",
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EmPsr.ia,
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EmPsr.bn,
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EmPsr.ed,
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EmPsr.ri,
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EmPsr.ss,
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EmPsr.dd,
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EmPsr.da,
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EmPsr.id,
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EmPsr.it,
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EmPsr.mc,
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EmPsr.is,
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EmPsr.cpl,
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EmPsr.rt,
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EmPsr.tb,
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EmPsr.lp,
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EmPsr.db,
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EmPsr.si,
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EmPsr.di,
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EmPsr.pp,
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EmPsr.sp,
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EmPsr.dfh,
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EmPsr.dfl,
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EmPsr.dt,
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EmPsr.pk,
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EmPsr.i,
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EmPsr.ic,
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EmPsr.mfh,
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EmPsr.mfl,
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EmPsr.ac,
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EmPsr.up,
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EmPsr.be
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);
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}
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return;
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} // DisplayPsrIA64()
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DECLARE_API( psr )
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/*++
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Routine Description:
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Dumps an IA64 Processor Status Word
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Arguments:
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args - Supplies the address in hex.
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Return Value:
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None
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--*/
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{
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ULONG64 psrValue;
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ULONG result;
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ULONG flags = 0;
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char *header;
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result = sscanf(args,"%X %lx", &psrValue, &flags);
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psrValue = GetExpression(args);
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if ((result != 1) && (result != 2)) {
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//
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// If user specified "@ipsr"...
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//
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char ipsrStr[16];
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result = sscanf(args, "%s %lx", ipsrStr, &flags);
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if ( ((result != 1) && (result != 2)) || strcmp(ipsrStr,"@ipsr") ) {
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dprintf("USAGE: !psr 0xValue [display_mode:0,1,2]\n");
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dprintf("USAGE: !psr @ipsr [display_mode:0,1,2]\n");
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return E_INVALIDARG;
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}
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psrValue = GetExpression("@ipsr");
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}
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header = (flags > DISPLAY_MIN) ? NULL : "\tpsr:\t";
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if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
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{
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dprintf("!psr not implemented for this architecture.\n");
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}
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else
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{
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DisplayPsrIA64( header, *((EM_PSR *) &psrValue), flags );
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}
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return S_OK;
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} // !psr
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