725 lines
20 KiB
C
725 lines
20 KiB
C
/*++
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Module Name:
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pci.h
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Abstract:
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This is the PCI bus specific header file used by device drivers.
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Author:
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Revision History:
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--*/
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#ifndef _PCI_
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#define _PCI_
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//
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// A PCI driver can read the complete 256 bytes of configuration
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// information for any PCI device by calling:
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//
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// ULONG
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// HalGetBusData (
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// IN BUS_DATA_TYPE PCIConfiguration,
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// IN ULONG PciBusNumber,
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// IN PCI_SLOT_NUMBER VirtualSlotNumber,
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// IN PPCI_COMMON_CONFIG &PCIDeviceConfig,
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// IN ULONG sizeof (PCIDeviceConfig)
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// );
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//
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// A return value of 0 means that the specified PCI bus does not exist.
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//
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// A return value of 2, with a VendorID of PCI_INVALID_VENDORID means
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// that the PCI bus does exist, but there is no device at the specified
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// VirtualSlotNumber (PCI Device/Function number).
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//
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//
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// begin_wdm begin_ntminiport begin_ntndis
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typedef struct _PCI_SLOT_NUMBER {
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union {
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struct {
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ULONG DeviceNumber:5;
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ULONG FunctionNumber:3;
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ULONG Reserved:24;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_SLOT_NUMBER, *PPCI_SLOT_NUMBER;
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#define PCI_TYPE0_ADDRESSES 6
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#define PCI_TYPE1_ADDRESSES 2
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#define PCI_TYPE2_ADDRESSES 5
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typedef struct _PCI_COMMON_CONFIG {
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USHORT VendorID; // (ro)
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USHORT DeviceID; // (ro)
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USHORT Command; // Device control
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USHORT Status;
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UCHAR RevisionID; // (ro)
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UCHAR ProgIf; // (ro)
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UCHAR SubClass; // (ro)
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UCHAR BaseClass; // (ro)
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UCHAR CacheLineSize; // (ro+)
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UCHAR LatencyTimer; // (ro+)
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UCHAR HeaderType; // (ro)
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UCHAR BIST; // Built in self test
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union {
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struct _PCI_HEADER_TYPE_0 {
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ULONG BaseAddresses[PCI_TYPE0_ADDRESSES];
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ULONG CIS;
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USHORT SubVendorID;
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USHORT SubSystemID;
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ULONG ROMBaseAddress;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved1[3];
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ULONG Reserved2;
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UCHAR InterruptLine; //
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UCHAR InterruptPin; // (ro)
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UCHAR MinimumGrant; // (ro)
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UCHAR MaximumLatency; // (ro)
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} type0;
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// end_wdm end_ntminiport end_ntndis
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//
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// PCI to PCI Bridge
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//
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struct _PCI_HEADER_TYPE_1 {
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ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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UCHAR IOBase;
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UCHAR IOLimit;
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USHORT SecondaryStatus;
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USHORT MemoryBase;
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USHORT MemoryLimit;
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USHORT PrefetchBase;
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USHORT PrefetchLimit;
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ULONG PrefetchBaseUpper32;
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ULONG PrefetchLimitUpper32;
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USHORT IOBaseUpper16;
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USHORT IOLimitUpper16;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved1[3];
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ULONG ROMBaseAddress;
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type1;
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//
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// PCI to CARDBUS Bridge
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//
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struct _PCI_HEADER_TYPE_2 {
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ULONG SocketRegistersBaseAddress;
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UCHAR CapabilitiesPtr;
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UCHAR Reserved;
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USHORT SecondaryStatus;
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UCHAR PrimaryBus;
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UCHAR SecondaryBus;
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UCHAR SubordinateBus;
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UCHAR SecondaryLatency;
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struct {
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ULONG Base;
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ULONG Limit;
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} Range[PCI_TYPE2_ADDRESSES-1];
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UCHAR InterruptLine;
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UCHAR InterruptPin;
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USHORT BridgeControl;
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} type2;
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// begin_wdm begin_ntminiport begin_ntndis
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} u;
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UCHAR DeviceSpecific[192];
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} PCI_COMMON_CONFIG, *PPCI_COMMON_CONFIG;
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#define PCI_COMMON_HDR_LENGTH (FIELD_OFFSET (PCI_COMMON_CONFIG, DeviceSpecific))
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#define PCI_MAX_DEVICES 32
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#define PCI_MAX_FUNCTION 8
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#define PCI_MAX_BRIDGE_NUMBER 0xFF
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#define PCI_INVALID_VENDORID 0xFFFF
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//
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// Bit encodings for PCI_COMMON_CONFIG.HeaderType
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//
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#define PCI_MULTIFUNCTION 0x80
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#define PCI_DEVICE_TYPE 0x00
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#define PCI_BRIDGE_TYPE 0x01
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#define PCI_CARDBUS_BRIDGE_TYPE 0x02
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#define PCI_CONFIGURATION_TYPE(PciData) \
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(((PPCI_COMMON_CONFIG)(PciData))->HeaderType & ~PCI_MULTIFUNCTION)
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#define PCI_MULTIFUNCTION_DEVICE(PciData) \
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((((PPCI_COMMON_CONFIG)(PciData))->HeaderType & PCI_MULTIFUNCTION) != 0)
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//
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// Bit encodings for PCI_COMMON_CONFIG.Command
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//
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#define PCI_ENABLE_IO_SPACE 0x0001
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#define PCI_ENABLE_MEMORY_SPACE 0x0002
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#define PCI_ENABLE_BUS_MASTER 0x0004
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#define PCI_ENABLE_SPECIAL_CYCLES 0x0008
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#define PCI_ENABLE_WRITE_AND_INVALIDATE 0x0010
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#define PCI_ENABLE_VGA_COMPATIBLE_PALETTE 0x0020
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#define PCI_ENABLE_PARITY 0x0040 // (ro+)
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#define PCI_ENABLE_WAIT_CYCLE 0x0080 // (ro+)
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#define PCI_ENABLE_SERR 0x0100 // (ro+)
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#define PCI_ENABLE_FAST_BACK_TO_BACK 0x0200 // (ro)
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//
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// Bit encodings for PCI_COMMON_CONFIG.Status
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//
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#define PCI_STATUS_CAPABILITIES_LIST 0x0010 // (ro)
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#define PCI_STATUS_66MHZ_CAPABLE 0x0020 // (ro)
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#define PCI_STATUS_UDF_SUPPORTED 0x0040 // (ro)
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#define PCI_STATUS_FAST_BACK_TO_BACK 0x0080 // (ro)
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#define PCI_STATUS_DATA_PARITY_DETECTED 0x0100
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#define PCI_STATUS_DEVSEL 0x0600 // 2 bits wide
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#define PCI_STATUS_SIGNALED_TARGET_ABORT 0x0800
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#define PCI_STATUS_RECEIVED_TARGET_ABORT 0x1000
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#define PCI_STATUS_RECEIVED_MASTER_ABORT 0x2000
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#define PCI_STATUS_SIGNALED_SYSTEM_ERROR 0x4000
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#define PCI_STATUS_DETECTED_PARITY_ERROR 0x8000
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//
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// The NT PCI Driver uses a WhichSpace parameter on its CONFIG_READ/WRITE
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// routines. The following values are defined-
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//
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#define PCI_WHICHSPACE_CONFIG 0x0
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#define PCI_WHICHSPACE_ROM 0x52696350
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// end_wdm
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//
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// PCI Capability IDs
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//
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#define PCI_CAPABILITY_ID_POWER_MANAGEMENT 0x01
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#define PCI_CAPABILITY_ID_AGP 0x02
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#define PCI_CAPABILITY_ID_MSI 0x05
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//
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// All PCI Capability structures have the following header.
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//
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// CapabilityID is used to identify the type of the structure (is
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// one of the PCI_CAPABILITY_ID values above.
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//
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// Next is the offset in PCI Configuration space (0x40 - 0xfc) of the
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// next capability structure in the list, or 0x00 if there are no more
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// entries.
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//
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typedef struct _PCI_CAPABILITIES_HEADER {
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UCHAR CapabilityID;
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UCHAR Next;
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} PCI_CAPABILITIES_HEADER, *PPCI_CAPABILITIES_HEADER;
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//
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// Power Management Capability
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//
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typedef struct _PCI_PMC {
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UCHAR Version:3;
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UCHAR PMEClock:1;
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UCHAR Rsvd1:1;
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UCHAR DeviceSpecificInitialization:1;
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UCHAR Rsvd2:2;
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struct _PM_SUPPORT {
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UCHAR Rsvd2:1;
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UCHAR D1:1;
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UCHAR D2:1;
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UCHAR PMED0:1;
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UCHAR PMED1:1;
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UCHAR PMED2:1;
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UCHAR PMED3Hot:1;
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UCHAR PMED3Cold:1;
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} Support;
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} PCI_PMC, *PPCI_PMC;
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typedef struct _PCI_PMCSR {
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USHORT PowerState:2;
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USHORT Rsvd1:6;
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USHORT PMEEnable:1;
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USHORT DataSelect:4;
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USHORT DataScale:2;
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USHORT PMEStatus:1;
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} PCI_PMCSR, *PPCI_PMCSR;
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typedef struct _PCI_PMCSR_BSE {
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UCHAR Rsvd1:6;
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UCHAR D3HotSupportsStopClock:1; // B2_B3#
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UCHAR BusPowerClockControlEnabled:1; // BPCC_EN
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} PCI_PMCSR_BSE, *PPCI_PMCSR_BSE;
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typedef struct _PCI_PM_CAPABILITY {
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PCI_CAPABILITIES_HEADER Header;
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//
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// Power Management Capabilities (Offset = 2)
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//
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union {
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PCI_PMC Capabilities;
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USHORT AsUSHORT;
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} PMC;
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//
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// Power Management Control/Status (Offset = 4)
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//
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union {
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PCI_PMCSR ControlStatus;
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USHORT AsUSHORT;
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} PMCSR;
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//
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// PMCSR PCI-PCI Bridge Support Extensions
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//
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union {
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PCI_PMCSR_BSE BridgeSupport;
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UCHAR AsUCHAR;
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} PMCSR_BSE;
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//
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// Optional read only 8 bit Data register. Contents controlled by
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// DataSelect and DataScale in ControlStatus.
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//
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UCHAR Data;
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} PCI_PM_CAPABILITY, *PPCI_PM_CAPABILITY;
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//
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// AGP Capability
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//
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typedef struct _PCI_AGP_CAPABILITY {
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PCI_CAPABILITIES_HEADER Header;
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USHORT Minor:4;
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USHORT Major:4;
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USHORT Rsvd1:8;
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struct _PCI_AGP_STATUS {
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ULONG Rate:3;
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ULONG Rsvd1:1;
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ULONG FastWrite:1;
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ULONG FourGB:1;
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ULONG Rsvd2:3;
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ULONG SideBandAddressing:1; // SBA
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ULONG Rsvd3:14;
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ULONG RequestQueueDepthMaximum:8; // RQ
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} AGPStatus;
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struct _PCI_AGP_COMMAND {
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ULONG Rate:3;
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ULONG Rsvd1:1;
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ULONG FastWriteEnable:1;
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ULONG FourGBEnable:1;
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ULONG Rsvd2:2;
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ULONG AGPEnable:1;
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ULONG SBAEnable:1;
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ULONG Rsvd3:14;
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ULONG RequestQueueDepth:8;
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} AGPCommand;
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} PCI_AGP_CAPABILITY, *PPCI_AGP_CAPABILITY;
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#define PCI_AGP_RATE_1X 0x1
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#define PCI_AGP_RATE_2X 0x2
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#define PCI_AGP_RATE_4X 0x4
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//
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// MSI (Message Signalled Interrupts) Capability
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//
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typedef struct _PCI_MSI_CAPABILITY {
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PCI_CAPABILITIES_HEADER Header;
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struct _PCI_MSI_MESSAGE_CONTROL {
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USHORT MSIEnable:1;
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USHORT MultipleMessageCapable:3;
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USHORT MultipleMessageEnable:3;
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USHORT CapableOf64Bits:1;
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USHORT Reserved:8;
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} MessageControl;
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union {
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struct _PCI_MSI_MESSAGE_ADDRESS {
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ULONG Reserved:2; // always zero, DWORD aligned address
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ULONG Address:30;
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} Register;
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ULONG Raw;
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} MessageAddress; // was ULONG_PTR
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//
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// The rest of the Capability structure differs depending on whether
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// 32bit or 64bit addressing is being used.
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//
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// (The CapableOf64Bits bit above determines this)
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//
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union {
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// For 64 bit devices
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struct _PCI_MSI_64BIT_DATA {
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ULONG MessageUpperAddress;
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USHORT MessageData;
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} Bit64;
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// For 32 bit devices
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struct _PCI_MSI_32BIT_DATA {
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USHORT MessageData;
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ULONG Unused;
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} Bit32;
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} Data;
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} PCI_MSI_CAPABILITY, *PPCI_PCI_CAPABILITY;
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// begin_wdm
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//
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// Base Class Code encodings for Base Class (from PCI spec rev 2.1).
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//
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#define PCI_CLASS_PRE_20 0x00
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#define PCI_CLASS_MASS_STORAGE_CTLR 0x01
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#define PCI_CLASS_NETWORK_CTLR 0x02
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#define PCI_CLASS_DISPLAY_CTLR 0x03
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#define PCI_CLASS_MULTIMEDIA_DEV 0x04
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#define PCI_CLASS_MEMORY_CTLR 0x05
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#define PCI_CLASS_BRIDGE_DEV 0x06
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#define PCI_CLASS_SIMPLE_COMMS_CTLR 0x07
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#define PCI_CLASS_BASE_SYSTEM_DEV 0x08
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#define PCI_CLASS_INPUT_DEV 0x09
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#define PCI_CLASS_DOCKING_STATION 0x0a
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#define PCI_CLASS_PROCESSOR 0x0b
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#define PCI_CLASS_SERIAL_BUS_CTLR 0x0c
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// 0d thru fe reserved
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#define PCI_CLASS_NOT_DEFINED 0xff
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//
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// Sub Class Code encodings (PCI rev 2.1).
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//
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// Class 00 - PCI_CLASS_PRE_20
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#define PCI_SUBCLASS_PRE_20_NON_VGA 0x00
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#define PCI_SUBCLASS_PRE_20_VGA 0x01
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// Class 01 - PCI_CLASS_MASS_STORAGE_CTLR
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#define PCI_SUBCLASS_MSC_SCSI_BUS_CTLR 0x00
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#define PCI_SUBCLASS_MSC_IDE_CTLR 0x01
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#define PCI_SUBCLASS_MSC_FLOPPY_CTLR 0x02
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#define PCI_SUBCLASS_MSC_IPI_CTLR 0x03
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#define PCI_SUBCLASS_MSC_RAID_CTLR 0x04
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#define PCI_SUBCLASS_MSC_OTHER 0x80
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// Class 02 - PCI_CLASS_NETWORK_CTLR
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#define PCI_SUBCLASS_NET_ETHERNET_CTLR 0x00
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#define PCI_SUBCLASS_NET_TOKEN_RING_CTLR 0x01
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#define PCI_SUBCLASS_NET_FDDI_CTLR 0x02
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#define PCI_SUBCLASS_NET_ATM_CTLR 0x03
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#define PCI_SUBCLASS_NET_OTHER 0x80
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// Class 03 - PCI_CLASS_DISPLAY_CTLR
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// N.B. Sub Class 00 could be VGA or 8514 depending on Interface byte
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#define PCI_SUBCLASS_VID_VGA_CTLR 0x00
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#define PCI_SUBCLASS_VID_XGA_CTLR 0x01
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#define PCI_SUBCLASS_VID_OTHER 0x80
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// Class 04 - PCI_CLASS_MULTIMEDIA_DEV
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#define PCI_SUBCLASS_MM_VIDEO_DEV 0x00
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#define PCI_SUBCLASS_MM_AUDIO_DEV 0x01
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#define PCI_SUBCLASS_MM_OTHER 0x80
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// Class 05 - PCI_CLASS_MEMORY_CTLR
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#define PCI_SUBCLASS_MEM_RAM 0x00
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#define PCI_SUBCLASS_MEM_FLASH 0x01
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#define PCI_SUBCLASS_MEM_OTHER 0x80
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// Class 06 - PCI_CLASS_BRIDGE_DEV
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#define PCI_SUBCLASS_BR_HOST 0x00
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#define PCI_SUBCLASS_BR_ISA 0x01
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#define PCI_SUBCLASS_BR_EISA 0x02
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#define PCI_SUBCLASS_BR_MCA 0x03
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#define PCI_SUBCLASS_BR_PCI_TO_PCI 0x04
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#define PCI_SUBCLASS_BR_PCMCIA 0x05
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#define PCI_SUBCLASS_BR_NUBUS 0x06
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#define PCI_SUBCLASS_BR_CARDBUS 0x07
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#define PCI_SUBCLASS_BR_OTHER 0x80
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// Class 07 - PCI_CLASS_SIMPLE_COMMS_CTLR
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// N.B. Sub Class 00 and 01 additional info in Interface byte
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#define PCI_SUBCLASS_COM_SERIAL 0x00
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#define PCI_SUBCLASS_COM_PARALLEL 0x01
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#define PCI_SUBCLASS_COM_OTHER 0x80
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// Class 08 - PCI_CLASS_BASE_SYSTEM_DEV
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// N.B. See Interface byte for additional info.
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#define PCI_SUBCLASS_SYS_INTERRUPT_CTLR 0x00
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#define PCI_SUBCLASS_SYS_DMA_CTLR 0x01
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#define PCI_SUBCLASS_SYS_SYSTEM_TIMER 0x02
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#define PCI_SUBCLASS_SYS_REAL_TIME_CLOCK 0x03
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#define PCI_SUBCLASS_SYS_OTHER 0x80
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// Class 09 - PCI_CLASS_INPUT_DEV
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#define PCI_SUBCLASS_INP_KEYBOARD 0x00
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#define PCI_SUBCLASS_INP_DIGITIZER 0x01
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#define PCI_SUBCLASS_INP_MOUSE 0x02
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#define PCI_SUBCLASS_INP_OTHER 0x80
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// Class 0a - PCI_CLASS_DOCKING_STATION
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#define PCI_SUBCLASS_DOC_GENERIC 0x00
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#define PCI_SUBCLASS_DOC_OTHER 0x80
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// Class 0b - PCI_CLASS_PROCESSOR
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#define PCI_SUBCLASS_PROC_386 0x00
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#define PCI_SUBCLASS_PROC_486 0x01
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#define PCI_SUBCLASS_PROC_PENTIUM 0x02
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#define PCI_SUBCLASS_PROC_ALPHA 0x10
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#define PCI_SUBCLASS_PROC_POWERPC 0x20
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#define PCI_SUBCLASS_PROC_COPROCESSOR 0x40
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// Class 0c - PCI_CLASS_SERIAL_BUS_CTLR
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#define PCI_SUBCLASS_SB_IEEE1394 0x00
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#define PCI_SUBCLASS_SB_ACCESS 0x01
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#define PCI_SUBCLASS_SB_SSA 0x02
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#define PCI_SUBCLASS_SB_USB 0x03
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#define PCI_SUBCLASS_SB_FIBRE_CHANNEL 0x04
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// end_ntndis
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type0.BaseAddresses
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//
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#define PCI_ADDRESS_IO_SPACE 0x00000001 // (ro)
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#define PCI_ADDRESS_MEMORY_TYPE_MASK 0x00000006 // (ro)
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#define PCI_ADDRESS_MEMORY_PREFETCHABLE 0x00000008 // (ro)
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#define PCI_ADDRESS_IO_ADDRESS_MASK 0xfffffffc
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#define PCI_ADDRESS_MEMORY_ADDRESS_MASK 0xfffffff0
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#define PCI_ADDRESS_ROM_ADDRESS_MASK 0xfffff800
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#define PCI_TYPE_32BIT 0
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#define PCI_TYPE_20BIT 2
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#define PCI_TYPE_64BIT 4
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type0.ROMBaseAddresses
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//
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#define PCI_ROMADDRESS_ENABLED 0x00000001
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//
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// Reference notes for PCI configuration fields:
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//
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// ro these field are read only. changes to these fields are ignored
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//
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// ro+ these field are intended to be read only and should be initialized
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// by the system to their proper values. However, driver may change
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// these settings.
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//
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// ---
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//
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// All resources comsumed by a PCI device start as unitialized
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// under NT. An uninitialized memory or I/O base address can be
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// determined by checking it's corrisponding enabled bit in the
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// PCI_COMMON_CONFIG.Command value. An InterruptLine is unitialized
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// if it contains the value of -1.
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//
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// end_wdm end_ntminiport
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// end_ntddk end_ntosp
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//
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// PCI_REGISTRY_INFO - this structure is passed into the HAL from
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// the firmware. It signifies how many PCI bus(es) are present and
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// what style of access the PCI bus(es) support.
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//
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typedef struct _PCI_REGISTRY_INFO {
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UCHAR MajorRevision;
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UCHAR MinorRevision;
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UCHAR NoBuses;
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UCHAR HardwareMechanism;
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} PCI_REGISTRY_INFO, *PPCI_REGISTRY_INFO;
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//
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// PCI definitions for IOBase & IOLimit
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// PCIBridgeIO2Base(a,b) - convert IOBase & IOBaseUpper16 to ULONG IOBase
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// PCIBridgeIO2Limit(a,b) - convert IOLimit & IOLimitUpper6 to ULONG IOLimit
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//
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#define PciBridgeIO2Base(a,b) \
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( ((a >> 4) << 12) + (((a & 0xf) == 1) ? (b << 16) : 0) )
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#define PciBridgeIO2Limit(a,b) (PciBridgeIO2Base(a,b) | 0xfff)
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#define PciBridgeMemory2Base(a) (ULONG) ((a & 0xfff0) << 16)
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#define PciBridgeMemory2Limit(a) (PciBridgeMemory2Base(a) | 0xfffff)
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type1/2.BridgeControl
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//
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#define PCI_ENABLE_BRIDGE_PARITY_ERROR 0x0001
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#define PCI_ENABLE_BRIDGE_SERR 0x0002
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#define PCI_ENABLE_BRIDGE_ISA 0x0004
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#define PCI_ENABLE_BRIDGE_VGA 0x0008
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#define PCI_ENABLE_BRIDGE_MASTER_ABORT_SERR 0x0020
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#define PCI_ASSERT_BRIDGE_RESET 0x0040
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type1.BridgeControl
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//
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#define PCI_ENABLE_BRIDGE_FAST_BACK_TO_BACK 0x0080
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//
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// Bit encodes for PCI_COMMON_CONFIG.u.type2.BridgeControl
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//
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#define PCI_ENABLE_CARDBUS_IRQ_ROUTING 0x0080
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#define PCI_ENABLE_CARDBUS_MEM0_PREFETCH 0x0100
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#define PCI_ENABLE_CARDBUS_MEM1_PREFETCH 0x0200
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#define PCI_ENABLE_CARDBUS_WRITE_POSTING 0x0400
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//
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// Definitions needed for Access to Hardware Type 1
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//
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#define PCI_TYPE1_ADDR_PORT (0xCF8)
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#define PCI_TYPE1_DATA_PORT 0xCFC
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typedef struct _PCI_TYPE1_CFG_BITS {
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union {
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struct {
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:7;
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ULONG Enable:1;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE1_CFG_BITS, *PPCI_TYPE1_CFG_BITS;
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//
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// Definitions needed for Access to Hardware Type 2
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//
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#define PCI_TYPE2_CSE_PORT ((PUCHAR) 0xCF8)
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#define PCI_TYPE2_FORWARD_PORT ((PUCHAR) 0xCFA)
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#define PCI_TYPE2_ADDRESS_BASE 0xC
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typedef struct _PCI_TYPE2_CSE_BITS {
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union {
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struct {
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UCHAR Enable:1;
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UCHAR FunctionNumber:3;
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UCHAR Key:4;
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} bits;
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UCHAR AsUCHAR;
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} u;
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} PCI_TYPE2_CSE_BITS, PPCI_TYPE2_CSE_BITS;
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typedef struct _PCI_TYPE2_ADDRESS_BITS {
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union {
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struct {
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USHORT RegisterNumber:8;
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USHORT Agent:4;
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USHORT AddressBase:4;
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} bits;
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USHORT AsUSHORT;
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} u;
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} PCI_TYPE2_ADDRESS_BITS, *PPCI_TYPE2_ADDRESS_BITS;
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//
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// Definitions for the config cycle format on the PCI bus.
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|
//
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typedef struct _PCI_TYPE0_CFG_CYCLE_BITS {
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union {
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struct {
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG Reserved2:21;
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} bits;
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ULONG AsULONG;
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} u;
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} PCI_TYPE0_CFG_CYCLE_BITS, *PPCI_TYPE0_CFG_CYCLE_BITS;
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typedef struct _PCI_TYPE1_CFG_CYCLE_BITS {
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union {
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struct {
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ULONG Reserved1:2;
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ULONG RegisterNumber:6;
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ULONG FunctionNumber:3;
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ULONG DeviceNumber:5;
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ULONG BusNumber:8;
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ULONG Reserved2:8;
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} bits;
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ULONG AsULONG;
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|
} u;
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} PCI_TYPE1_CFG_CYCLE_BITS, *PPCI_TYPE1_CFG_CYCLE_BITS;
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#endif
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