1080 lines
24 KiB
C
1080 lines
24 KiB
C
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/*++
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Copyright (c) 2000 Microsoft Corporation
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Module Name:
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initkr.c
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Abstract:
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This module contains the code to initialize the kernel data structures
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and to initialize the idle thread, its process, the processor control
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block, and the processor control region.
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Author:
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David N. Cutler (davec) 22-Apr-2000
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Environment:
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Kernel mode only.
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--*/
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#include "ki.h"
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//
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// Define default profile IRQL level.
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//
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KIRQL KiProfileIrql = PROFILE_LEVEL;
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//
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// Define the process and thread for the initial system process and startup
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// thread.
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//
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EPROCESS KiInitialProcess;
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ETHREAD KiInitialThread;
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//
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// Define macro to initialize an IDT entry.
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//
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// KiInitializeIdtEntry (
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// IN PKIDTENTRY64 Entry,
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// IN PVOID Address,
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// IN USHORT Level
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// )
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//
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// Arguments:
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//
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// Entry - Supplies a pointer to an IDT entry.
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//
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// Address - Supplies the address of the vector routine.
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//
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// Dpl - Descriptor privilege level.
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//
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// Ist - Interrupt stack index.
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//
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#define KiInitializeIdtEntry(Entry, Address, Level, Index) \
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(Entry)->OffsetLow = (USHORT)((ULONG64)(Address)); \
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(Entry)->Selector = KGDT64_R0_CODE; \
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(Entry)->IstIndex = Index; \
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(Entry)->Type = 0xe; \
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(Entry)->Dpl = (Level); \
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(Entry)->Present = 1; \
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(Entry)->OffsetMiddle = (USHORT)((ULONG64)(Address) >> 16); \
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(Entry)->OffsetHigh = (ULONG)((ULONG64)(Address) >> 32) \
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//
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// Define forward referenced prototypes.
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//
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ULONG
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KiFatalFilter (
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IN ULONG Code,
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IN PEXCEPTION_POINTERS Pointers
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);
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VOID
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KiSetCacheInformation (
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VOID
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);
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VOID
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KiSetCpuVendor (
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VOID
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);
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VOID
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KiSetFeatureBits (
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VOID
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);
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VOID
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KiSetProcessorType (
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VOID
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);
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#pragma alloc_text(INIT, KiFatalFilter)
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#pragma alloc_text(INIT, KiInitializeBootStructures)
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#pragma alloc_text(INIT, KiInitializeKernel)
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#pragma alloc_text(INIT, KiInitMachineDependent)
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#pragma alloc_text(INIT, KiSetCacheInformation)
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#pragma alloc_text(INIT, KiSetCpuVendor)
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#pragma alloc_text(INIT, KiSetFeatureBits)
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#pragma alloc_text(INIT, KiSetProcessorType)
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VOID
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KiInitializeKernel (
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IN PKPROCESS Process,
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IN PKTHREAD Thread,
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IN PVOID IdleStack,
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IN PKPRCB Prcb,
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IN CCHAR Number,
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PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This function gains control after the system has been booted, but before
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the system has been completely initialized. Its function is to initialize
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the kernel data structures, initialize the idle thread and process objects,
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complete the initialization of the processor control block (PRCB) and
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processor control region (PCR), call the executive initialization routine,
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then return to the system startup routine. This routine is also called to
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initialize the processor specific structures when a new processor is
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brought on line.
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Arguments:
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Process - Supplies a pointer to a control object of type process for
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the specified processor.
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Thread - Supplies a pointer to a dispatcher object of type thread for
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the specified processor.
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IdleStack - Supplies a pointer the base of the real kernel stack for
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idle thread on the specified processor.
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Prcb - Supplies a pointer to a processor control block for the specified
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processor.
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Number - Supplies the number of the processor that is being
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initialized.
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LoaderBlock - Supplies a pointer to the loader parameter block.
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Return Value:
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None.
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--*/
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{
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ULONG FeatureBits;
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LONG Index;
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ULONG64 DirectoryTableBase[2];
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KIRQL OldIrql;
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PKPCR Pcr = KeGetPcr();
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//
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// Set CPU vendor.
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//
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KiSetCpuVendor();
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//
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// Set processor type.
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//
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KiSetProcessorType();
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//
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// Set the processor feature bits.
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//
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KiSetFeatureBits();
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FeatureBits = Prcb->FeatureBits;
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//
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// If this is the boot processor, then enable global pages, set the page
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// attributes table, set machine check enable, set large page enable, and
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// enable debug extensions.
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//
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// N.B. This only happens on the boot processor and at a time when there
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// can be no coherency problem. On subsequent, processors this happens
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// during the transistion into 64-bit mode which is also at a time
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// that there can be no coherency problems.
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//
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if (Number == 0) {
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//
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// Flush the entire TB and enable global pages.
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//
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KeFlushCurrentTb();
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//
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// Set page attributes table and flush cache.
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//
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KiSetPageAttributesTable();
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WritebackInvalidate();
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//
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// Set machine check enable, large page enable, and debugger extensions.
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//
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WriteCR4(ReadCR4() | CR4_DE | CR4_MCE | CR4_PSE);
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//
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// Flush the entire TB.
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//
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KeFlushCurrentTb();
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}
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//
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// set processor cache size information.
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//
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KiSetCacheInformation();
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//
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// Initialize DPC listhead, spin lock, and queuing parameters.
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//
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InitializeListHead(&Prcb->DpcListHead);
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KeInitializeSpinLock(&Prcb->DpcLock);
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Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
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Prcb->MinimumDpcRate = KiMinimumDpcRate;
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Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
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//
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// Initialize power state information.
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//
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PoInitializePrcb(Prcb);
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//
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// initialize the per processor lock queue entry for implemented locks.
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//
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KiInitQueuedSpinLocks(Prcb, Number);
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//
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// If the initial processor is being initialized, then initialize the
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// per system data structures.
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//
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if (Number == 0) {
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//
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// Set default node until the node topology is available.
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//
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KeNodeBlock[0] = &KiNode0;
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#if defined(KE_MULTINODE)
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for (Index = 1; Index < MAXIMUM_CCNUMA_NODES; Index += 1) {
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KeNodeBlock[Index] = &KiNodeInit[Index];
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}
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#endif
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Prcb->ParentNode = KeNodeBlock[0];
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KeNodeBlock[0]->ProcessorMask = Prcb->SetMember;
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//
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// Set global architecture and feature information.
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//
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KeProcessorArchitecture = PROCESSOR_ARCHITECTURE_INTEL;
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KeProcessorLevel = (USHORT)Prcb->CpuType;
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KeProcessorRevision = Prcb->CpuStep;
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KeFeatureBits = FeatureBits;
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//
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// Lower IRQL to APC level.
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//
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KeLowerIrql(APC_LEVEL);
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//
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// Initialize kernel internal spinlocks
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//
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KeInitializeSpinLock(&KiFreezeExecutionLock);
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//
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// Performance architecture independent initialization.
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//
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KiInitSystem();
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//
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// Initialize idle thread process object and then set:
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//
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// 1. the process quantum.
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//
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DirectoryTableBase[0] = 0;
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DirectoryTableBase[1] = 0;
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KeInitializeProcess(Process,
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(KPRIORITY)0,
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(KAFFINITY)(-1),
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&DirectoryTableBase[0],
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FALSE);
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Process->ThreadQuantum = MAXCHAR;
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} else {
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//
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// If the CPU feature bits are not identical, then bugcheck.
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//
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// N.B. This will probably need to be relaxed at some point.
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//
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if (FeatureBits != KeFeatureBits) {
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KeBugCheckEx(MULTIPROCESSOR_CONFIGURATION_NOT_SUPPORTED,
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(ULONG64)FeatureBits,
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(ULONG64)KeFeatureBits,
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0,
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0);
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}
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//
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// Lower IRQL to DISPATCH level.
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//
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KeLowerIrql(DISPATCH_LEVEL);
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}
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//
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// Set global processor features.
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//
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SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE;
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SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] = TRUE;
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SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] = TRUE;
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SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] = TRUE;
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SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
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SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE;
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SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] = TRUE;
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//
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// Initialize idle thread object and then set:
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//
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// 1. the next processor number to the specified processor.
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// 2. the thread priority to the highest possible value.
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// 3. the state of the thread to running.
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// 4. the thread affinity to the specified processor.
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// 5. the specified member in the process active processors set.
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//
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KeInitializeThread(Thread,
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(PVOID)((ULONG64)IdleStack),
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NULL,
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NULL,
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NULL,
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NULL,
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NULL,
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Process);
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Thread->NextProcessor = Number;
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Thread->Priority = HIGH_PRIORITY;
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Thread->State = Running;
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Thread->Affinity = AFFINITY_MASK(Number);
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Thread->WaitIrql = DISPATCH_LEVEL;
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Process->ActiveProcessors |= AFFINITY_MASK(Number);
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//
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// Call the executive initialization routine.
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//
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try {
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ExpInitializeExecutive(Number, LoaderBlock);
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} except(KiFatalFilter(GetExceptionCode(), GetExceptionInformation())) {
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}
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//
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// If the initial processor is being initialized, then compute the timer
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// table reciprocal value, reset the PRCB values for the controllable DPC
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// behavior in order to reflect any registry overrides, and initialize the
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// global unwind history table.
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//
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if (Number == 0) {
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KiTimeIncrementReciprocal = KiComputeReciprocal((LONG)KeMaximumIncrement,
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&KiTimeIncrementShiftCount);
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Prcb->MaximumDpcQueueDepth = KiMaximumDpcQueueDepth;
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Prcb->MinimumDpcRate = KiMinimumDpcRate;
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Prcb->AdjustDpcThreshold = KiAdjustDpcThreshold;
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RtlInitializeHistoryTable();
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}
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//
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// Raise IRQL to dispatch level and eet the priority of the idle thread
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// to zero. This will have the effect of immediately causing the phase
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// one initialization thread to get scheduled for execution. The idle
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// thread priority is then set ot the lowest realtime priority.
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//
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KeRaiseIrql(DISPATCH_LEVEL, &OldIrql);
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KeSetPriorityThread(Thread, 0);
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Thread->Priority = LOW_REALTIME_PRIORITY;
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//
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// Raise IRQL to highest level.
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//
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KeRaiseIrql(HIGH_LEVEL, &OldIrql);
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//
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// If the current processor is a secondary processor and a thread has
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// not been selected for execution, then set the appropriate bit in the
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// idle summary.
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//
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#if !defined(NT_UP)
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if ((Number != 0) && (Prcb->NextThread == NULL)) {
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KiIdleSummary |= AFFINITY_MASK(Number);
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}
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#endif
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//
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// Signal that this processor has completed its initialization.
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//
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LoaderBlock->Prcb = (ULONG64)NULL;
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return;
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}
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VOID
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KiInitializeBootStructures (
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PLOADER_PARAMETER_BLOCK LoaderBlock
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)
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/*++
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Routine Description:
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This function initializes the boot structures for a processor. It is only
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called by the system start up code. Certain fields in the boot structures
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have already been initialized. In particular:
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The address and limit of the GDT and IDT in the PCR.
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The address of the system TSS in the PCR.
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The processor number in the PCR.
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The special registers in the PRCB.
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N.B. All uninitialized fields are zero.
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Arguments:
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LoaderBlock - Supplies a pointer to the loader block that has been
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initialized for this processor.
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Return Value:
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None.
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--*/
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{
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PKIDTENTRY64 IdtBase;
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ULONG Index;
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PKPCR Pcr = KeGetPcr();
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PKPRCB Prcb = KeGetCurrentPrcb();
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UCHAR Number;
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PKTHREAD Thread;
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PKTSS64 TssBase;
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//
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// Initialize the PCR major and minor version numbers.
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//
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Pcr->MajorVersion = PCR_MAJOR_VERSION;
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Pcr->MinorVersion = PCR_MINOR_VERSION;
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//
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// initialize the PRCB major and minor version numbers and build type.
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//
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Prcb->MajorVersion = PRCB_MAJOR_VERSION;
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Prcb->MinorVersion = PRCB_MINOR_VERSION;
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Prcb->BuildType = 0;
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#if DBG
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Prcb->BuildType |= PRCB_BUILD_DEBUG;
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#endif
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#if defined(NT_UP)
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Prcb->BuildType |= PRCB_BUILD_UNIPROCESSOR;
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#endif
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//
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// Initialize the PRCR processor number and the PCR and PRCB set member.
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//
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Number = Pcr->Number;
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Prcb->Number = Number;
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Prcb->SetMember = AFFINITY_MASK(Number);
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Prcb->NotSetMember = ~Prcb->SetMember;
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//
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// If this is processor zero, then initialize the address of the system
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// process and initial thread.
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//
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if (Number == 0) {
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LoaderBlock->Process = (ULONG64)&KiInitialProcess;
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LoaderBlock->Thread = (ULONG64)&KiInitialThread;
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}
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//
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// Initialize the PRCB scheduling thread address and the thread process
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// address.
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//
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Thread = (PVOID)LoaderBlock->Thread;
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Prcb->CurrentThread = Thread;
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Prcb->NextThread = NULL;
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Prcb->IdleThread = Thread;
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Thread->ApcState.Process = (PKPROCESS)LoaderBlock->Process;
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//
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// Initialize the processor block address.
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//
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KiProcessorBlock[Number] = Prcb;
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//
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// Initialize the PRCB address of the DPC stack.
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//
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Prcb->DpcStack = (PVOID)LoaderBlock->KernelStack;
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//
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// Initialize the PRCB symmetric multithreading member.
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//
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Prcb->MultiThreadProcessorSet = Prcb->SetMember;
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//
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// Initialize the IDT.
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//
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IdtBase = Pcr->IdtBase;
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KiInitializeIdtEntry(&IdtBase[0], &KiDivideErrorFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[1], &KiDebugTrapOrFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[2], &KiNmiInterrupt, 0, TSS_IST_PANIC);
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KiInitializeIdtEntry(&IdtBase[3], &KiBreakpointTrap, 3, 0);
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KiInitializeIdtEntry(&IdtBase[4], &KiOverflowTrap, 3, 0);
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KiInitializeIdtEntry(&IdtBase[5], &KiBoundFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[6], &KiInvalidOpcodeFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[7], &KiNpxNotAvailableFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[8], &KiDoubleFaultAbort, 0, TSS_IST_PANIC);
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KiInitializeIdtEntry(&IdtBase[9], &KiNpxSegmentOverrunAbort, 0, 0);
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KiInitializeIdtEntry(&IdtBase[10], &KiInvalidTssFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[11], &KiSegmentNotPresentFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[12], &KiStackFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[13], &KiGeneralProtectionFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[14], &KiPageFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[15], &KxUnexpectedInterrupt0[15], 0, 0);
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KiInitializeIdtEntry(&IdtBase[16], &KiFloatingErrorFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[17], &KiAlignmentFault, 0, 0);
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KiInitializeIdtEntry(&IdtBase[18], &KiMcheckAbort, 0, TSS_IST_MCA);
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KiInitializeIdtEntry(&IdtBase[19], &KiXmmException, 0, 0);
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KiInitializeIdtEntry(&IdtBase[20], &KxUnexpectedInterrupt0[20], 0, 0);
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KiInitializeIdtEntry(&IdtBase[21], &KxUnexpectedInterrupt0[21], 0, 0);
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KiInitializeIdtEntry(&IdtBase[22], &KxUnexpectedInterrupt0[22], 0, 0);
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KiInitializeIdtEntry(&IdtBase[23], &KxUnexpectedInterrupt0[23], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[24], &KxUnexpectedInterrupt0[24], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[25], &KxUnexpectedInterrupt0[25], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[26], &KxUnexpectedInterrupt0[26], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[27], &KxUnexpectedInterrupt0[27], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[28], &KxUnexpectedInterrupt0[28], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[29], &KxUnexpectedInterrupt0[29], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[30], &KxUnexpectedInterrupt0[30], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[31], &KiApcInterrupt, 0, 0);
|
|
|
|
KiInitializeIdtEntry(&IdtBase[32], &KxUnexpectedInterrupt0[32], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[33], &KxUnexpectedInterrupt0[33], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[34], &KxUnexpectedInterrupt0[34], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[35], &KxUnexpectedInterrupt0[35], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[36], &KxUnexpectedInterrupt0[36], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[37], &KxUnexpectedInterrupt0[37], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[38], &KxUnexpectedInterrupt0[38], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[39], &KxUnexpectedInterrupt0[39], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[40], &KxUnexpectedInterrupt0[40], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[41], &KxUnexpectedInterrupt0[41], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[42], &KxUnexpectedInterrupt0[42], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[43], &KxUnexpectedInterrupt0[43], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[44], &KxUnexpectedInterrupt0[44], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[45], &KiDebugServiceTrap, 3, 0);
|
|
KiInitializeIdtEntry(&IdtBase[46], &KxUnexpectedInterrupt0[46], 0, 0);
|
|
KiInitializeIdtEntry(&IdtBase[47], &KiDpcInterrupt, 0, 0);
|
|
|
|
//
|
|
// Initialize unexpected interrupt entries.
|
|
//
|
|
|
|
for (Index = PRIMARY_VECTOR_BASE; Index <= MAXIMUM_IDTVECTOR; Index += 1) {
|
|
KiInitializeIdtEntry(&IdtBase[Index],
|
|
&KxUnexpectedInterrupt0[Index],
|
|
0,
|
|
0);
|
|
}
|
|
|
|
//
|
|
// Initialize the system TSS I/O Map.
|
|
//
|
|
|
|
TssBase = Pcr->TssBase;
|
|
RtlFillMemory(&TssBase->IoMap[0], sizeof(KIO_ACCESS_MAP), -1);
|
|
TssBase->IoMapEnd = -1;
|
|
TssBase->IoMapBase = KiComputeIopmOffset(FALSE);
|
|
|
|
//
|
|
// Initialize the stack base and limit.
|
|
//
|
|
|
|
Pcr->NtTib.StackBase = (PVOID)(TssBase->Rsp0);
|
|
Pcr->NtTib.StackLimit = (PVOID)(TssBase->Rsp0 - KERNEL_STACK_SIZE);
|
|
|
|
//
|
|
// Initialize the system call MSRs.
|
|
//
|
|
// N.B. CSTAR must be written before LSTAR to work around a bug in the
|
|
// simulator.
|
|
//
|
|
|
|
WriteMSR(MSR_STAR,
|
|
((ULONG64)KGDT64_R0_CODE << 32) | (((ULONG64)KGDT64_R3_CMCODE | RPL_MASK) << 48));
|
|
|
|
WriteMSR(MSR_CSTAR, (ULONG64)&KiSystemCall32);
|
|
WriteMSR(MSR_LSTAR, (ULONG64)&KiSystemCall64);
|
|
WriteMSR(MSR_SYSCALL_MASK, EFLAGS_IF_MASK | EFLAGS_TF_MASK);
|
|
|
|
//
|
|
// Initialize the HAL for this processor.
|
|
//
|
|
|
|
HalInitializeProcessor(Number, LoaderBlock);
|
|
|
|
//
|
|
// Set the appropriate member in the active processors set.
|
|
//
|
|
|
|
KeActiveProcessors |= AFFINITY_MASK(Number);
|
|
|
|
//
|
|
// Set the number of processors based on the maximum of the current
|
|
// number of processors and the current processor number.
|
|
//
|
|
|
|
if ((Number + 1) > KeNumberProcessors) {
|
|
KeNumberProcessors = Number + 1;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
ULONG
|
|
KiFatalFilter (
|
|
IN ULONG Code,
|
|
IN PEXCEPTION_POINTERS Pointers
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function is executed if an unhandled exception occurs during
|
|
phase 0 initialization. Its function is to bug check the system
|
|
with all the context information still on the stack.
|
|
|
|
Arguments:
|
|
|
|
Code - Supplies the exception code.
|
|
|
|
Pointers - Supplies a pointer to the exception information.
|
|
|
|
Return Value:
|
|
|
|
None - There is no return from this routine even though it appears there
|
|
is.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
KeBugCheckEx(PHASE0_EXCEPTION,
|
|
Code,
|
|
(ULONG64)Pointers,
|
|
0,
|
|
0);
|
|
|
|
return EXCEPTION_EXECUTE_HANDLER;
|
|
}
|
|
|
|
BOOLEAN
|
|
KiInitMachineDependent (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function initializes machine dependent data structures and hardware.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
ULONG Size;
|
|
NTSTATUS Status;
|
|
BOOLEAN UseFrameBufferCaching;
|
|
|
|
//
|
|
// Query the HAL to determine if the write combining can be used for the
|
|
// frame buffer.
|
|
//
|
|
|
|
Status = HalQuerySystemInformation(HalFrameBufferCachingInformation,
|
|
sizeof(BOOLEAN),
|
|
&UseFrameBufferCaching,
|
|
&Size);
|
|
|
|
//
|
|
// If the status is successful and frame buffer caching is disabled,
|
|
// then don't enable write combining.
|
|
//
|
|
|
|
if (!NT_SUCCESS(Status) || (UseFrameBufferCaching != FALSE)) {
|
|
MmEnablePAT();
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
VOID
|
|
KiSetCacheInformation (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function sets the current processor cache information in the PCR.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
UCHAR Associativity;
|
|
ULONG CacheSize;
|
|
CPU_INFO CpuInfo;
|
|
ULONG LineSize;
|
|
PKPCR Pcr = KeGetPcr();
|
|
|
|
//
|
|
// Get the CPU L2 cache information.
|
|
//
|
|
|
|
KiCpuId(0x80000006, &CpuInfo);
|
|
|
|
//
|
|
// Get the L2 cache line size.
|
|
//
|
|
|
|
LineSize = CpuInfo.Ecx & 0xff;
|
|
|
|
//
|
|
// Get the L2 cache size.
|
|
//
|
|
|
|
CacheSize = (CpuInfo.Ecx >> 16) << 10;
|
|
|
|
//
|
|
// Compute the L2 cache associativity.
|
|
//
|
|
|
|
switch ((CpuInfo.Ecx >> 12) & 0xf) {
|
|
|
|
//
|
|
// Two way set associative.
|
|
//
|
|
|
|
case 2:
|
|
Associativity = 2;
|
|
break;
|
|
|
|
//
|
|
// Four way set associative.
|
|
//
|
|
|
|
case 4:
|
|
Associativity = 4;
|
|
break;
|
|
|
|
//
|
|
// Six way set associative.
|
|
//
|
|
|
|
case 6:
|
|
Associativity = 6;
|
|
break;
|
|
|
|
//
|
|
// Eight way set associative.
|
|
//
|
|
|
|
case 8:
|
|
Associativity = 8;
|
|
break;
|
|
|
|
//
|
|
// Fully associative.
|
|
//
|
|
|
|
case 255:
|
|
Associativity = 16;
|
|
break;
|
|
|
|
//
|
|
// Direct mapped.
|
|
//
|
|
|
|
default:
|
|
Associativity = 1;
|
|
break;
|
|
}
|
|
|
|
//
|
|
// Set L2 cache information.
|
|
//
|
|
|
|
Pcr->SecondLevelCacheAssociativity = Associativity;
|
|
Pcr->SecondLevelCacheSize = CacheSize;
|
|
|
|
//
|
|
// If the line size is greater then the current largest line size, then
|
|
// set the new largest line size.
|
|
//
|
|
|
|
if (LineSize > KeLargestCacheLine) {
|
|
KeLargestCacheLine = LineSize;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
KiSetCpuVendor (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Set the current processor cpu vendor information in the PRCB.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
PKPRCB Prcb = KeGetCurrentPrcb();
|
|
CPU_INFO CpuInfo;
|
|
ULONG Temp;
|
|
|
|
//
|
|
// Get the CPU vendor string.
|
|
//
|
|
|
|
KiCpuId(0, &CpuInfo);
|
|
|
|
//
|
|
// Copy vendor string to PRCB.
|
|
//
|
|
|
|
Temp = CpuInfo.Ecx;
|
|
CpuInfo.Ecx = CpuInfo.Edx;
|
|
CpuInfo.Edx = Temp;
|
|
RtlCopyMemory(Prcb->VendorString,
|
|
&CpuInfo.Ebx,
|
|
sizeof(Prcb->VendorString) - 1);
|
|
|
|
Prcb->VendorString[sizeof(Prcb->VendorString) - 1] = '\0';
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
KiSetFeatureBits (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Set the current processor feature bits in the PRCB.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
CPU_INFO CpuInfo;
|
|
ULONG FeatureBits;
|
|
PKPRCB Prcb = KeGetCurrentPrcb();
|
|
|
|
//
|
|
// Get CPU feature information.
|
|
//
|
|
|
|
KiCpuId(1, &CpuInfo);
|
|
|
|
//
|
|
// Set the initial APIC ID.
|
|
//
|
|
|
|
Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
|
|
|
|
//
|
|
// If the required fetures are not present, then bugcheck.
|
|
//
|
|
|
|
if ((CpuInfo.Edx & HF_REQUIRED) != HF_REQUIRED) {
|
|
KeBugCheckEx(UNSUPPORTED_PROCESSOR, CpuInfo.Edx, 0, 0, 0);
|
|
}
|
|
|
|
FeatureBits = KF_REQUIRED;
|
|
if (CpuInfo.Edx & 0x00200000) {
|
|
FeatureBits |= KF_DTS;
|
|
}
|
|
|
|
//
|
|
// Get extended CPU feature information.
|
|
//
|
|
|
|
KiCpuId(0x80000000, &CpuInfo);
|
|
|
|
//
|
|
// Check the extended feature bits.
|
|
//
|
|
|
|
if (CpuInfo.Edx & 0x80000000) {
|
|
FeatureBits |= KF_3DNOW;
|
|
}
|
|
|
|
Prcb->LogicalProcessorsPerPhysicalProcessor = 1;
|
|
Prcb->FeatureBits = FeatureBits;
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
KiSetProcessorType (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function sets the current processor family and stepping in the PRCB.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
CPU_INFO CpuInfo;
|
|
PKPRCB Prcb = KeGetCurrentPrcb();
|
|
|
|
//
|
|
// Get cpu feature information.
|
|
//
|
|
|
|
KiCpuId(1, &CpuInfo);
|
|
|
|
//
|
|
// Set processor family and stepping information.
|
|
//
|
|
|
|
Prcb->CpuID = TRUE;
|
|
Prcb->CpuType = (CCHAR)((CpuInfo.Eax >> 8) & 0xf);
|
|
Prcb->CpuStep = (USHORT)(((CpuInfo.Eax << 4) & 0xf00) | (CpuInfo.Eax & 0xf));
|
|
return;
|
|
}
|
|
|
|
VOID
|
|
KeOptimizeProcessorControlState (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This function performs no operation on AMD64.
|
|
|
|
Arguments:
|
|
|
|
None.
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
return;
|
|
}
|