212 lines
5.8 KiB
C
212 lines
5.8 KiB
C
/************************************************************************/
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/* */
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/* VDPDATA.H */
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/* */
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/* Copyright (c) 1993, ATI Technologies Incorporated. */
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/************************************************************************/
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/********************** PolyTron RCS Utilities
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$Revision: 1.1 $
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$Date: 20 Jul 1995 18:02:24 $
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$Author: mgrubac $
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$Log: S:/source/wnt/ms11/miniport/vcs/vdpdata.h $
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*
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* Rev 1.1 20 Jul 1995 18:02:24 mgrubac
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* Added support for VDIF files.
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*
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* Rev 1.0 31 Jan 1994 11:50:04 RWOLFF
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* Initial revision.
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Rev 1.1 05 Nov 1993 13:33:58 RWOLFF
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Fixed clock frequency table.
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Rev 1.0 16 Aug 1993 13:32:32 Robert_Wolff
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Initial revision.
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Rev 1.1 04 May 1993 16:51:10 RWOLFF
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Switched from floating point to long integers due to lack of floating point
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support in Windows NT kernel-mode code.
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Rev 1.0 30 Apr 1993 16:47:18 RWOLFF
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Initial revision.
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End of PolyTron RCS section *****************/
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#ifdef DOC
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VDPDATA.H - Definitions and structures used internally by VDPTOCRT.C.
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#endif
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/*
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* Sync polarities. INTERNAL_ERROR is an error code for functions
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* which have 0 as a legitimate return (e.g. GetPolarity). Functions
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* which do not have zero as a legitimate return value should follow
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* the "Zero = failure, Nonzero = success" convention.
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*/
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#define POSITIVE 0
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#define NEGATIVE 1
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#define INTERNAL_ERROR -1
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// GENERAL CONSTANTS
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#define NONINTERLACED 0
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#define INTERLACED 1
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/*
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* Constants used in pseudo-floating point calculations
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*/
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#define THOUSAND 1000L
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#define HALF_MILLION 500000L
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#define MILLION 1000000L
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/*
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* Data structure used for horz and vert information from the vddp file
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*/
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typedef struct _HALFDATA
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{
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long Resolution; // pixels
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unsigned long ScanFrequency; // horz - Hz, vert - mHz
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char Polarity; // positive or negative
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unsigned long SyncWidth, // horz - ns, vert - us
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FrontPorch, // horz - ns, vert - us
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BackPorch, // horz - ns, vert - us
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ActiveTime, // horz - ns, vert - us
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BlankTime; // horz - ns, vert - us
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} HALFDATA, *P_HALFDATA;
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/*
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* Data structure used for complete preadjusted timing data set
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*/
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typedef struct _TIMINGDATA
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{
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char ModeName[33]; // name of the video mode
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char Interlaced; // interlaced or non-interlaced mode
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HALFDATA HorzData; // horizontal data
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HALFDATA VertData; // vertical data
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} TIMINGDATA, *P_TIMINGDATA;
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/*
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* Data structure used to hold number of timings sections and pointers to
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* timings buffer for each limits section
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*/
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typedef struct _LIMITSDATA
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{
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unsigned long DotClock; // maximum pixel clock -- for all assoc. timings
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long TimingsCount; // number of timings section for this limits sec.
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P_TIMINGDATA TimingsPtr; // pointer to buffer holding timings data
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}LIMITSDATA, *P_LIMITSDATA;
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typedef struct {
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char video_mode[33];
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unsigned char h_total, h_disp, h_sync_strt, h_sync_wid;
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unsigned long v_total, v_disp, v_sync_strt;
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unsigned char v_sync_wid, disp_cntl, crt_pitch, clk_sel;
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unsigned long pixel_clk;
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// ***** the values below this comment were added for instvddp.exe *****
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unsigned char lock,fifo_depth,vga_refresh_rate_code;
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unsigned long control,hi_color_ctl,hi_color_vfifo;
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} crtT;
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#if 0
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typedef enum {
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clk_43MHz = 0,
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clk_49MHz = 1,
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clk_93MHz = 2,
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clk_36MHz = 3,
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clk_50MHz = 4,
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clk_57MHz = 5,
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clk_extrn1 = 6,
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clk_45MHz = 7,
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clk_30MHz = 8,
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clk_32MHz = 9,
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clk_110MHz = 10,
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clk_80MHz = 11,
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clk_40MHz = 12,
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clk_75MHz = 14,
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clk_65MHz = 15
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} clockT;
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#endif
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#if 1
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typedef enum {
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clk_100MHz = 0,
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clk_126MHz = 1,
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clk_93MHz = 2,
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clk_36MHz = 3,
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clk_50MHz = 4,
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clk_57MHz = 5,
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clk_extrn1 = 6,
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clk_45MHz = 7,
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clk_135MHz = 8,
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clk_32MHz = 9,
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clk_110MHz = 10,
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clk_80MHz = 11,
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clk_40MHz = 12,
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clk_75MHz = 14,
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clk_65MHz = 15
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} clockT;
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#endif
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typedef struct {
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long clock_selector;
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long clock_freq;
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} clk_infoT;
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#ifdef INCLUDE_VDPDATA
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#if 0
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/* These are the pixel clocks for the 18810 Clock Chip */
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clk_infoT clock_info[16] = {
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{ clk_43MHz , 42.95E+6 },
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{ clk_49MHz , 48.77E+6 },
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{ clk_93MHz , 92.40E+6 },
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{ clk_36MHz , 36.00E+6 },
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{ clk_50MHz , 50.35E+6 },
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{ clk_57MHz , 56.64E+6 },
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{ clk_extrn1 , 0.000000 },
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{ clk_45MHz , 44.90E+6 },
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{ clk_30MHz , 30.24E+6 },
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{ clk_32MHz , 32.00E+6 },
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{ clk_110MHz , 110.0E+6 },
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{ clk_80MHz , 80.00E+6 },
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{ clk_40MHz , 40.00E+6 },
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{ clk_75MHz , 75.00E+6 },
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{ clk_65MHz , 65.00E+6 },
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{ -1 , 0.000000 }
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};
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#endif
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#if 1
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/* These are the pixel clocks for the 18811-1 Clock Chip */
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clk_infoT clock_info[16] = {
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{ clk_100MHz , 100000000L },
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{ clk_126MHz , 126000000L },
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{ clk_93MHz , 92400000L },
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{ clk_36MHz , 36000000L },
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{ clk_50MHz , 50350000L },
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{ clk_57MHz , 56640000L },
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{ clk_extrn1 , 0L },
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{ clk_45MHz , 44900000L },
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{ clk_135MHz , 135000000L },
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{ clk_32MHz , 32000000L },
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{ clk_110MHz , 110000000L },
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{ clk_80MHz , 80000000L },
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{ clk_40MHz , 40000000L },
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{ clk_75MHz , 75000000L },
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{ clk_65MHz , 65000000L },
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{ -1 , 0L }
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};
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#endif
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#else
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extern clk_infoT clock_info[16];
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#endif
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