200 lines
4.9 KiB
C
200 lines
4.9 KiB
C
//
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// Register bit constants.
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//
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#define X86_CR4_DEBUG_EXTENSIONS 0x8
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#define X86_DR6_BREAK_03 0xf
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#define X86_DR6_SINGLE_STEP 0x4000
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#define X86_DR7_LOCAL_EXACT_ENABLE 0x100
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#define X86_DR7_LEN0_SHIFT 18
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#define X86_DR7_RW0_EXECUTE 0x00000
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#define X86_DR7_RW0_WRITE 0x10000
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#define X86_DR7_RW0_IO 0x20000
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#define X86_DR7_RW0_READ_WRITE 0x30000
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#define X86_DR7_L0_ENABLE 0x1
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#define X86_DR7_ALL_ENABLES 0xff
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// All control bits used by breaks 0-3.
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#define X86_DR7_CTRL_03_MASK ((ULONG)0xffff00ff)
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#define X86_IS_VM86(x) ((unsigned short)(((x) >> 17) & 1))
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#define X86_BIT_FLAGOF (1 << 11)
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#define X86_BIT_FLAGDF (1 << 10)
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#define X86_BIT_FLAGIF (1 << 9)
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#define X86_BIT_FLAGTF (1 << 8)
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#define X86_BIT_FLAGSF (1 << 7)
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#define X86_BIT_FLAGZF (1 << 6)
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#define X86_BIT_FLAGAF (1 << 4)
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#define X86_BIT_FLAGPF (1 << 2)
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#define X86_BIT_FLAGCF (1 << 0)
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#define X86_BIT_FLAGVIP (1 << 20)
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#define X86_BIT_FLAGVIF (1 << 19)
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#define X86_BIT_FLAGIOPL 3
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#define X86_SHIFT_FLAGIOPL 12
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//
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// MSRs and their bits.
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//
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#define X86_MSR_DEBUG_CTL 0x1d9
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#define X86_DEBUG_CTL_LAST_BRANCH_RECORD 0x0001
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#define X86_DEBUG_CTL_BRANCH_TRACE 0x0002
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#define X86_MSR_LAST_BRANCH_FROM_IP 0x1db
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#define X86_MSR_LAST_BRANCH_TO_IP 0x1dc
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#define X86_MSR_LAST_EXCEPTION_FROM_IP 0x1dd
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#define X86_MSR_LAST_EXCEPTION_TO_IP 0x1de
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//
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// Native register values. These register values are shared
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// between plain X86 and AMD64. In IA32 intregs have 32-bit values,
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// in AMD64 they have 64-bit values.
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// Logically they are the same register, though, and the shared
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// disassembler uses them.
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//
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// 32/64 bit.
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#define X86_NAX 1
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#define X86_NBX 2
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#define X86_NCX 3
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#define X86_NDX 4
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#define X86_NSI 5
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#define X86_NDI 6
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#define X86_NSP 7
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#define X86_NBP 8
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#define X86_NIP 9
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// 32 bit.
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#define X86_NFL 10
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// 16 bit. These must be a group of consecutive values.
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#define X86_NCS 11
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#define X86_NDS 12
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#define X86_NES 13
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#define X86_NFS 14
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#define X86_NGS 15
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#define X86_NSS 16
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#define X86_NSEG_FIRST X86_NCS
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#define X86_NSEG_LAST X86_NSS
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//
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// IA32 definitions.
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//
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#define X86_GS X86_NGS
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#define X86_FS X86_NFS
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#define X86_ES X86_NES
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#define X86_DS X86_NDS
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#define X86_EDI X86_NDI
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#define X86_ESI X86_NSI
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#define X86_EBX X86_NBX
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#define X86_EDX X86_NDX
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#define X86_ECX X86_NCX
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#define X86_EAX X86_NAX
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#define X86_EBP X86_NBP
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#define X86_EIP X86_NIP
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#define X86_CS X86_NCS
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#define X86_EFL X86_NFL
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#define X86_ESP X86_NSP
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#define X86_SS X86_NSS
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#define X86_CR0 17
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#define X86_CR2 18
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#define X86_CR3 19
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#define X86_CR4 20
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#define X86_DR0 21
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#define X86_DR1 22
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#define X86_DR2 23
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#define X86_DR3 24
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#define X86_DR6 25
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#define X86_DR7 26
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#define X86_GDTR 27
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#define X86_GDTL 28
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#define X86_IDTR 29
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#define X86_IDTL 30
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#define X86_TR 31
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#define X86_LDTR 32
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// SSE registers:
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#define X86_MXCSR 50
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#define X86_XMM0 51
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#define X86_XMM1 52
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#define X86_XMM2 53
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#define X86_XMM3 54
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#define X86_XMM4 55
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#define X86_XMM5 56
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#define X86_XMM6 57
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#define X86_XMM7 58
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#define X86_XMM_FIRST X86_XMM0
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#define X86_XMM_LAST X86_XMM7
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// Floating-point registers:
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#define X86_FPCW 60
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#define X86_FPSW 61
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#define X86_FPTW 62
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#define X86_ST0 70
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#define X86_ST1 71
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#define X86_ST2 72
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#define X86_ST3 73
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#define X86_ST4 74
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#define X86_ST5 75
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#define X86_ST6 76
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#define X86_ST7 77
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#define X86_ST_FIRST X86_ST0
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#define X86_ST_LAST X86_ST7
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// MMX registers:
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#define X86_MM0 80
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#define X86_MM1 81
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#define X86_MM2 82
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#define X86_MM3 83
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#define X86_MM4 84
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#define X86_MM5 85
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#define X86_MM6 86
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#define X86_MM7 87
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#define X86_MM_FIRST X86_MM0
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#define X86_MM_LAST X86_MM7
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#define X86_FLAGBASE 100
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#define X86_DI 100
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#define X86_SI 101
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#define X86_BX 102
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#define X86_DX 103
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#define X86_CX 104
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#define X86_AX 105
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#define X86_BP 106
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#define X86_IP 107
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#define X86_FL 108
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#define X86_SP 109
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#define X86_BL 110
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#define X86_DL 111
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#define X86_CL 112
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#define X86_AL 113
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#define X86_BH 114
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#define X86_DH 115
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#define X86_CH 116
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#define X86_AH 117
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#define X86_IOPL 118
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#define X86_OF 119
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#define X86_DF 120
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#define X86_IF 121
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#define X86_TF 122
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#define X86_SF 123
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#define X86_ZF 124
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#define X86_AF 125
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#define X86_PF 126
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#define X86_CF 127
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#define X86_VIP 128
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#define X86_VIF 129
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