583 lines
12 KiB
ArmAsm
583 lines
12 KiB
ArmAsm
//++
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//
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// Module name
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// miscs.s
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// Author
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// Allen Kay (allen.m.kay@intel.com) Jun-12-95
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// Description
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// Misc. assembly functions.
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//
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//---
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#include "ksia64.h"
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.file "miscs.s"
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.global PalProcPhysical
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.global PalPhysicalBase
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.global PalTrPs
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.global IoPortPhysicalBase
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.global IoPortTrPs
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.global BdPcr
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//
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// Setup CPU state to go from physical to virtual
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//
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LEAF_ENTRY(MempGoVirtual)
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rpT0 = t21
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rpT1 = t20
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rTrPs = t19
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rPPN = t18
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rPsr = t17
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mov ar.rsc = r0
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mov rPsr = psr
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;;
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rsm (1 << PSR_I)
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;;
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rsm (1 << PSR_IC)
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;;
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srlz.i
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;;
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movl t0 = FPSR_FOR_KERNEL
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;;
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mov ar.fpsr = t0 // initialize fpsr
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;;
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//
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// Initialize Region Registers
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//
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mov t1 = (START_GLOBAL_RID << RR_RID) | (PAGE_SHIFT << RR_PS) | RR_PS_VE
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movl t3 = KSEG0_BASE
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;;
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mov rr[t3] = t1
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//
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// Invalidate all protection key registers
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//
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mov t1 = zero
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;;
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Bl_PKRLoop:
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mov pkr[t1] = zero
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;;
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add t1 = 1, t1
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add t2 = 1, t2
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;;
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cmp.gtu pt0, pt1 = PKRNUM - 1, t1
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;;
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(pt0) br.cond.sptk.few.clr Bl_PKRLoop
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;;
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#if 0
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//
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// Setup the 1-to-1 translation for the loader
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//
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movl t0 = BL_16M
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;;
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movl t2 = ITIR_VALUE(0,PS_16M)
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mov cr.ifa = t0
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;;
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mov cr.itir = t2
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;;
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mov t3 = BL_LOADER_INDEX
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movl t2 = TR_VALUE(1,BL_16M,3,0,1,1,0,1)
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;;
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itr.d dtr[t3] = t2
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;;
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itr.i itr[t3] = t2
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#endif
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//
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//
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// Setup the first 16MB translation for the drivers.
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//
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movl t0 = KSEG0_BASE + BL_16M
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;;
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movl t2 = ITIR_VALUE(0,PS_16M)
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mov cr.ifa = t0
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;;
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mov cr.itir = t2
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;;
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mov t3 = DTR_DRIVER0_INDEX
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movl t2 = TR_VALUE(1,BL_16M,3,0,1,1,0,1)
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;;
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itr.d dtr[t3] = t2
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;;
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itr.i itr[t3] = t2
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//
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// Setup the second 16MB translation for the drivers.
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//
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movl t0 = KSEG0_BASE + BL_32M;
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;;
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movl t2 = ITIR_VALUE(0,PS_16M)
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mov cr.ifa = t0
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;;
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mov cr.itir = t2
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;;
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mov t3 = DTR_DRIVER1_INDEX
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movl t2 = TR_VALUE(1,BL_32M,3,0,1,1,0,1)
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;;
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itr.d dtr[t3] = t2
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;;
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itr.i itr[t3] = t2
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//
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// Setup 16MB translation for kernel/hal binary.
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//
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movl t0 = KSEG0_BASE + BL_48M;
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;;
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movl t2 = ITIR_VALUE(0,PS_16M)
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mov cr.ifa = t0
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;;
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mov cr.itir = t2
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;;
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mov t3 = DTR_KERNEL_INDEX
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movl t2 = TR_VALUE(1,BL_48M,3,0,1,1,0,1)
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;;
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itr.d dtr[t3] = t2
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;;
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itr.i itr[t3] = t2
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//
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// Setup 16MB translation for decompression buffer used by setupldr.
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//
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movl t0 = KSEG0_BASE + BL_64M;
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;;
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movl t2 = ITIR_VALUE(0,PS_16M)
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mov cr.ifa = t0
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;;
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mov cr.itir = t2
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;;
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mov t3 = BL_DECOMPRESS_INDEX
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movl t2 = TR_VALUE(1,BL_64M,3,0,1,1,0,1)
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;;
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itr.d dtr[t3] = t2
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;;
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itr.i itr[t3] = t2
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//
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//
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// Setup translation for PAL.
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//
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movl rpT0 = PalPhysicalBase // PAL base addr
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movl rpT1 = PalTrPs // PAL page size
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movl t1 = VIRTUAL_PAL_BASE
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;;
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ld8 t0 = [rpT0]
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ld8 rTrPs = [rpT1]
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mov cr.ifa = t1
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movl t4 = IITR_ATTRIBUTE_PPN_MASK // construct GR[r]
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movl t5 = TR_VALUE(1,0,3,0,1,1,0,1)
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;;
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shl t2 = rTrPs, ITIR_PS
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and t6 = t0, t4 // t6 is PPN in GR[r]
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;;
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mov cr.itir = t2
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;;
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mov t3 = DTR_HAL_INDEX // pre-assigned index
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or t2 = t5, t6 // t2 is now GR[r]
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;;
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itr.d dtr[t3] = t2
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//
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// Setup translation for I/O port space
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//
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movl rpT0 = IoPortPhysicalBase // IO Port base addr
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movl rpT1 = IoPortTrPs // IO Port page size
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movl t1 = VIRTUAL_IO_BASE
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;;
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ld8 t0 = [rpT0]
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ld8 rTrPs = [rpT1]
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mov cr.ifa = t1
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movl t4 = IITR_ATTRIBUTE_PPN_MASK // construct GR[r]
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movl t5 = TR_VALUE(1,0,3,0,1,1,4,1)
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;;
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shl t2 = rTrPs, ITIR_PS
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and t6 = t0, t4 // t6 is PPN in GR[r]
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;;
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mov cr.itir = t2
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;;
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mov t3 = DTR_IO_PORT_INDEX // pre-assigned index
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or t2 = t5, t6 // t2 is now GR[r]
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;;
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itr.d dtr[t3] = t2
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//
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// Setup translation for BdPcr
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//
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movl t0 = BdPcr
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movl rTrPs = PS_4M
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;;
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mov cr.ifa = t0
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movl t4 = IITR_ATTRIBUTE_PPN_MASK // construct GR[r]
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movl t5 = TR_VALUE(1,0,3,0,1,1,0,1)
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;;
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shl t2 = rTrPs, ITIR_PS
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and t6 = t0, t4 // t6 is PPN in GR[r]
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;;
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mov cr.itir = t2
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;;
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mov t3 = DTR_KIPCR_INDEX
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or t2 = t5, t6 // t2 is now GR[r]
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;;
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itr.d dtr[t3] = t2
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//
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// Turn on address translation, interrupt, psr.ed, protection key.
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//
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movl t1 = MASK_IA64(PSR_BN,1) | MASK_IA64(PSR_RT,1) | MASK_IA64(PSR_DT,1) | MASK_IA64(PSR_IC,1) | MASK_IA64(PSR_AC,1) | MASK_IA64(PSR_DB,1)
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;;
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or t1 = t1, rPsr
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;;
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mov cr.ipsr = t1
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//
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// Initialize DCR to defer all speculation faults
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//
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mov t0 = DCR_DEFER_ALL
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;;
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mov cr.dcr = t0
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//
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// Prepare to do RFI to return to the caller.
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//
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movl t0 = return_label
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;;
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mov cr.iip = t0
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;;
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mov cr.ifs = r0
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;;
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rfi
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;;
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return_label:
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mov v0 = zero
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;;
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LEAF_RETURN
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LEAF_EXIT(MempGoVirtual)
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//
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// Flip psr.it bit from virtual to physical addressing mode.
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//
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LEAF_ENTRY(FlipToPhysical)
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rPsr = t17
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rsm (1 << PSR_I)
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;;
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rsm (1 << PSR_IC)
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;;
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srlz.i
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;;
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mov rPsr = psr
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movl t1 = MASK_IA64(PSR_RT,1) | MASK_IA64(PSR_DT,1)
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movl t2 = MASK_IA64(PSR_BN,1) | MASK_IA64(PSR_IC,1)
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;;
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xor t1 = t1, rPsr
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;;
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or t1 = t1, t2
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;;
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mov cr.ipsr = t1
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//
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// Prepare to do RFI to return to the caller.
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//
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movl t0 = FlipToPhysicalReturn
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;;
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mov cr.iip = t0
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;;
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mov cr.ifs = r0
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;;
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rfi
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;;
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FlipToPhysicalReturn:
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mov v0 = zero
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;;
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LEAF_RETURN
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LEAF_EXIT(FlipToPhysical)
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//
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// Flip psr.it bit from physical to virtual addressing mode.
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//
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LEAF_ENTRY(FlipToVirtual)
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rPsr = t17
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rsm (1 << PSR_I)
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;;
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rsm (1 << PSR_IC)
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;;
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srlz.i
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;;
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mov rPsr = psr
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movl t1 = MASK_IA64(PSR_RT,1) | MASK_IA64(PSR_DT,1) | MASK_IA64(PSR_BN,1) | MASK_IA64(PSR_IC,1)
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;;
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or t1 = t1, rPsr
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;;
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mov cr.ipsr = t1
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//
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// Prepare to do RFI to return to the caller.
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//
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movl t0 = FlipToVirtualReturn
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;;
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mov cr.iip = t0
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;;
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mov cr.ifs = r0
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;;
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rfi
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;;
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FlipToVirtualReturn:
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mov v0 = zero
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;;
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LEAF_RETURN
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LEAF_EXIT(FlipToVirtual)
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//
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// Clean up TR mappings used only by NT loader.
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//
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LEAF_ENTRY(BlTrCleanUp)
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rpT0 = t22
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rPsr = t17
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//
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// purge BL_DECOMPRESS_INDEX
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//
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movl t0 = PS_16M << PS_SHIFT
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movl t1 = KSEG0_BASE + BL_64M
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;;
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ptr.d t1, t0
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;;
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#if 0
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//
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// purge BL_LOADER_INDEX
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//
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movl t0 = PS_16M << PS_SHIFT
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movl t1 = BL_16M
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;;
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ptr.i t1, t0
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;;
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ptr.d t1, t0
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#endif
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//
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// purge BdPcr translation.
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//
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movl t0 = BdPcr
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movl t1 = PS_4M << PS_SHIFT
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;;
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ptr.d t0, t1
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;;
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//
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// Turn on address translation, interrupt, psr.ed, protection key.
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//
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rsm (1 << PSR_I)
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;;
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rsm (1 << PSR_IC)
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;;
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srlz.i
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;;
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//
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// At this point, turn on psr.it so that we can pass control to
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// the kernel.
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//
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mov rPsr = psr
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movl t1 = MASK_IA64(PSR_BN,1) | MASK_IA64(PSR_IT,1) | MASK_IA64(PSR_RT,1) | MASK_IA64(PSR_DT,1) | MASK_IA64(PSR_IC,1) | MASK_IA64(PSR_AC,1) | MASK_IA64(PSR_DB,1)
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;;
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or t1 = t1, rPsr
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;;
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mov cr.ipsr = t1
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//
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// Prepare to do RFI to return to the caller.
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//
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movl t0 = BlTrCleanupReturn
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;;
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mov cr.iip = t0
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;;
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mov cr.ifs = r0
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;;
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rfi
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;;
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BlTrCleanupReturn:
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mov v0 = zero
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;;
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LEAF_RETURN
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LEAF_EXIT (BlTrCleanUp)
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//++
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//
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// VOID
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// BlpPalProc(
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// LONGLONG a0, /* PAL function ID */
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// LONGLONG a1, /* PAL argument */
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// LONGLONG a2, /* PAL argument */
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// LONGLONG a3 /* PAL argument */
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// );
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//
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// Routine Description
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// This routine sets up the correct registers for input into PAL depending on
|
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// if the call uses static or stacked registers, turns off interrupts, ensures
|
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// the correct bank registers are being used and calls into the PAL.
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//
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// Return Values:
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// r8->r11 contain the 4 64-bit return values for PAL, r8 is the status
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//--
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NESTED_ENTRY(BlpPalProc)
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NESTED_SETUP(4,3,4,0)
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PROLOGUE_END
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// For both the static and stacked register conventions, load r28 with FunctionID
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mov r28 = a0
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// If static register calling convention (1-255, 512-767), copy arguments to r29->r31
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// Otherwise, copy to out0->out3 so they are in r32->r35 in PAL_PROC
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mov t0 = a0
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;;
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shr t0 = t0, 8
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;;
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tbit.z pt0, pt1 = t0, 0
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;;
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//
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// Static proc: do br not call
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//
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(pt0) mov r29 = a1
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(pt0) mov r30 = a2
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(pt0) mov r31 = a3
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//
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// Stacked call
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//
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(pt1) mov out0 = a0
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(pt1) mov out1 = a1
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(pt1) mov out2 = a2
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(pt1) mov out3 = a3
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|
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// Load up the address of PAL_PROC and call it
|
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addl t1 = @gprel(PalProcPhysical), gp
|
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;;
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ld8 t0 = [t1]
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;;
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mov bt0 = t0
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|
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// Call into PAL_PROC
|
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|
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(pt0) addl t1 = @ltoff(PalReturn), gp
|
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;;
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(pt0) ld8 t0 = [t1]
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;;
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(pt0) mov brp = t0
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;;
|
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// Disable interrupts
|
||
|
||
DISABLE_INTERRUPTS(loc2)
|
||
;;
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||
srlz.d
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;;
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(pt0) br.sptk.many bt0
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;;
|
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(pt1) br.call.sptk brp = bt0
|
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;;
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||
PalReturn:
|
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// Restore the interrupt state
|
||
|
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RESTORE_INTERRUPTS(loc2)
|
||
;;
|
||
NESTED_RETURN
|
||
NESTED_EXIT(BlpPalProc)
|