512 lines
14 KiB
ArmAsm
512 lines
14 KiB
ArmAsm
// TITLE("Hibernation wake dispatcher")
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//++
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//
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// Copyright (c) 1999 Intel Corporation
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//
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// Module Name:
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//
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// wakes.s
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//
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// Abstract:
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//
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//
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// Author:
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//
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// Allen Kay (allen.m.kay@intel.com) 8 June, 1999
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//
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// Environment:
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//
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// Firmware, OS Loader. Position-independent.
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//
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// Revision History:
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//
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//--
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#include "ksia64.h"
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#include "paldef.h"
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.global HiberMapPage
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.global HiberRemapPage
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.global HiberWakeState
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.global HiberFirstRemap
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.global HiberLastRemap
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.global HiberImagePageSelf
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.global HiberBreakOnWake
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// VOID
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// WakeDispatcher(
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// VOID
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// )
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//
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// Routine description:
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//
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// This code performs the final stages of restarting the hibernation
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// image. Pages that were loaded in temporary buffer space because
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// the memory they belong in was in use by the firmware are copied
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// to their final destination; an IMB is issued after this to ensure
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// that the I-cache is coherent with any code that got copied; and
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// necessary context is loaded into registers and NT is reentered.
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//
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// Because this code is part of the loader image that may be overwritten
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// by this copy process, it must itself have been copied to a free
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// page before it is executed. Note that because there is presently
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// no mechanism for allocating multiple contiguous pages, this code cannot
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// exceed one page (8K).
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//
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// Arguments:
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//
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// None.
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//
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// Return Value:
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//
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// Never returns.
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LEAF_ENTRY(WakeDispatcherStartLocal)
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.prologue
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.regstk 1, 30, 2, 0
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alloc t4 = ar.pfs, 1, 30, 2, 0
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ARGPTR(a0)
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rMapPage = loc11
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rRemapPage = loc12
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rWakeState = loc13
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rPageCount = loc14
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rPageSelf = loc15
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rBreakOnWake = loc16
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src1 = loc17
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src2 = loc18
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tmp = loc19
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rKSEG0 = loc20
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rpT0 = loc21
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rpT1 = loc22
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rpT2 = loc23
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rpT3 = loc24
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//
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// Get variables into registers before copying any pages, as they may be
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// overwritten.
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//
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movl rpT0 = HiberMapPage // pointer to source pages
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movl rpT1 = HiberRemapPage // pointer to target pages
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movl rpT2 = HiberWakeState // pointer to KPROCESSOR_STATE for
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// restarting the hibernation image
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;;
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ld8 rMapPage = [rpT0] // load them
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ld8 rRemapPage = [rpT1]
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ld8 rWakeState = [rpT2]
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;;
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movl rpT0 = HiberFirstRemap // first page index
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movl rpT1 = HiberLastRemap // last page index
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movl rpT2 = HiberImagePageSelf // PFN where MemImage ends up
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movl rpT3 = HiberBreakOnWake // "break on wake" flag
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;;
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ld4 t0 = [rpT0] // load them
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ld4 t1 = [rpT1]
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ld8 rPageSelf = [rpT2]
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ld1 rBreakOnWake = [rpT3]
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;;
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sub rPageCount = t1, t0 // number of pages to copy
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add rMapPage = t0, rMapPage // first source page
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add rRemapPage = t0, rRemapPage // first target page
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;;
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cmp.eq pt1, pt0 = rPageCount, zero // nothing to copy
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;;
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(pt1) br.cond.spnt CopyDone
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//
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// Copy pages.
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//
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NextPage:
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add rPageCount = -1, rPageCount // count page copied
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movl rKSEG0 = KSEG0_BASE // physical -> KSEG0
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ld8.fill t0 = [rMapPage], 8 // source page number
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;;
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shl t0 = t0, PAGE_SHIFT // page -> physical address
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;;
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add t0 = rKSEG0, t0 // physical -> KSEG0
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ld8.fill t1 = [rRemapPage], 8 // destination address
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;;
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shl t1 = t1, PAGE_SHIFT // page -> physical address
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;;
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add t1 = rKSEG0, t1 // physical -> KSEG0
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movl t2 = 1024 // 8KB = 1024 quadwords
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;;
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NextQuadWord:
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add t2 = -1, t2 // count quadword
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ld8.fill t3 = [t0], 8 // load a quadword
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;;
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st8.spill [t1] = t3, 8 // store it
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;;
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cmp.eq pt0, pt1 = t2, zero
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;;
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(pt1) br.cond.spnt NextQuadWord
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cmp.eq pt0, pt1 = rPageCount, zero
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;;
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(pt1) br.cond.spnt NextPage
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//
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// All necessary pages have been copied. Check the break-on-wake flag,
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// and change the signature NT will see when it wakes up if it was set.
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//
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CopyDone:
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cmp.eq pt1, pt0 = rBreakOnWake, zero // no flag set, do nothing
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;;
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(pt1) br.cond.spnt SkipSigChange
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shl rPageSelf = rPageSelf, PAGE_SHIFT // convert to physical
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;;
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add rPageSelf = rKSEG0, rPageSelf // make superpage address
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movl t0 = 0x706b7262 // 'brkp'
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;;
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st4 [rPageSelf] = t0 // signature is first longword of MemImage
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//
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// Synchronize the I-cache, load essential NT context, and transfer control
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// to the restored system.
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//
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SkipSigChange:
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#if 0
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PublicFunction(PalProc)
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mov out0 = PAL_CACHE_FLUSH // call PAL cache flush routine
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mov out1 = 1 // flush I-cache only
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movl rpT0 = PalProc
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;;
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ld8 t0 = [rpT0]
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;;
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mov bt0 = t0
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;;
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br.call.spnt brp = bt0
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#endif
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//
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// Restore context. Only the integer registers are restored; this code runs
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// in the firmware environment, so floating point can't be used, and NT
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// PALcode abstractions such as the PSR don't exist. It is the responsibility
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// of NT's code that saves the hibernation context to put enough information
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// in the integer registers in the CONTEXT to be able to finish restoring
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// context to restart NT.
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//
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mov a0 = rWakeState // CONTEXT is the first thing
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// in the KPROCESSOR_STATE
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;;
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//
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// Restore all the registers.
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//
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add src1 = CxIntNats, a0
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add src2 = CxPreds, a0
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add tmp = CxIntGp, a0
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;;
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ld8.nt1 t17 = [src1], CxBrRp - CxIntNats
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ld8.nt1 t16 = [src2], CxBrS0 - CxPreds
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shr tmp = tmp, 3
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;;
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ld8.nt1 t0 = [src1], CxBrS1 - CxBrRp
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ld8.nt1 t1 = [src2], CxBrS2 - CxBrS0
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and tmp = 0x3f, tmp
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;;
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ld8.nt1 t2 = [src1], CxBrS3 - CxBrS1
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ld8.nt1 t3 = [src2], CxBrS4 - CxBrS2
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cmp4.ge pt1, pt0 = 1, tmp
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;;
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ld8.nt1 t4 = [src1], CxBrT0 - CxBrS3
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ld8.nt1 t5 = [src2], CxBrT1 - CxBrS4
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(pt1) sub loc5 = 1, tmp
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;;
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ld8.nt1 t6 = [src1], CxApUNAT - CxBrT0
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ld8.nt1 t7 = [src2], CxApLC - CxBrT1
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(pt0) add loc5 = -1, tmp
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;;
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ld8.nt1 loc0 = [src1], CxApEC - CxApUNAT
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ld8.nt1 t8 = [src2], CxApCCV - CxApLC
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(pt0) sub loc6 = 65, tmp
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;;
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ld8.nt1 t9 = [src1], CxApDCR - CxApEC
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ld8.nt1 t10 = [src2], CxRsPFS - CxApCCV
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(pt1) shr.u t17 = t17, loc5
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;;
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ld8.nt1 loc1 = [src1], CxRsBSP - CxApDCR
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ld8.nt1 t11 = [src2], CxRsRSC - CxRsPFS
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(pt0) shl loc7 = t17, loc5
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;;
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ld8.nt1 loc2 = [src1], CxStIIP - CxRsBSP
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ld8.nt1 loc3 = [src2], CxStIFS - CxRsRSC
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(pt0) shr.u loc8 = t17, loc6
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;;
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ld8.nt1 loc9 = [src1]
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ld8.nt1 loc10 = [src2]
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(pt0) or t17 = loc7, loc8
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;;
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mov ar.unat = t17
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add src1 = CxFltS0, a0
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shr t12 = loc2, 3
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;;
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add src2 = CxFltS1, a0
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and t12 = 0x3f, t12 // current rnat save index
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and t13 = 0x7f, loc10 // total frame size
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;;
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mov ar.ccv = t10
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add t14 = t13, t12
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mov ar.pfs = t11
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;;
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Rrc20:
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cmp4.gt pt1, pt0 = 63, t14
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;;
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(pt0) add t14 = -63, t14
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(pt0) add t13 = 1, t13
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;;
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nop.m 0
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(pt1) shl t13 = t13, 3
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(pt0) br.cond.spnt Rrc20
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;;
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add loc2 = loc2, t13
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nop.f 0
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mov pr = t16, -1
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ldf.fill.nt1 fs0 = [src1], CxFltS2 - CxFltS0
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ldf.fill.nt1 fs1 = [src2], CxFltS3 - CxFltS1
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mov brp = t0
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;;
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ldf.fill.nt1 fs2 = [src1], CxFltT0 - CxFltS2
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ldf.fill.nt1 fs3 = [src2], CxFltT1 - CxFltS3
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mov bs0 = t1
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;;
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ldf.fill.nt1 ft0 = [src1], CxFltT2 - CxFltT0
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ldf.fill.nt1 ft1 = [src2], CxFltT3 - CxFltT1
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mov bs1 = t2
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;;
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ldf.fill.nt1 ft2 = [src1], CxFltT4 - CxFltT2
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ldf.fill.nt1 ft3 = [src2], CxFltT5 - CxFltT3
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mov bs2 = t3
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;;
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ldf.fill.nt1 ft4 = [src1], CxFltT6 - CxFltT4
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ldf.fill.nt1 ft5 = [src2], CxFltT7 - CxFltT5
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mov bs3 = t4
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;;
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ldf.fill.nt1 ft6 = [src1], CxFltT8 - CxFltT6
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ldf.fill.nt1 ft7 = [src2], CxFltT9 - CxFltT7
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mov bs4 = t5
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;;
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ldf.fill.nt1 ft8 = [src1], CxFltS4 - CxFltT8
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ldf.fill.nt1 ft9 = [src2], CxFltS5 - CxFltT9
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mov bt0 = t6
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;;
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ldf.fill.nt1 fs4 = [src1], CxFltS6 - CxFltS4
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ldf.fill.nt1 fs5 = [src2], CxFltS7 - CxFltS5
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mov bt1 = t7
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;;
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ldf.fill.nt1 fs6 = [src1], CxFltS8 - CxFltS6
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ldf.fill.nt1 fs7 = [src2], CxFltS9 - CxFltS7
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mov ar.lc = t8
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;;
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ldf.fill.nt1 fs8 = [src1], CxFltS10 - CxFltS8
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ldf.fill.nt1 fs9 = [src2], CxFltS11 - CxFltS9
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mov ar.ec = t9
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;;
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ldf.fill.nt1 fs10 = [src1], CxFltS12 - CxFltS10
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ldf.fill.nt1 fs11 = [src2], CxFltS13 - CxFltS11
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nop.i 0
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;;
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ldf.fill.nt1 fs12 = [src1], CxFltS14 - CxFltS12
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ldf.fill.nt1 fs13 = [src2], CxFltS15 - CxFltS13
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add loc6 = CxIntGp, a0
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;;
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ldf.fill.nt1 fs14 = [src1], CxFltS16 - CxFltS14
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ldf.fill.nt1 fs15 = [src2], CxFltS17 - CxFltS15
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add loc7 = CxIntT0, a0
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;;
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ldf.fill.nt1 fs16 = [src1], CxFltS18 - CxFltS16
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ldf.fill.nt1 fs17 = [src2], CxFltS19 - CxFltS17
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add t19 = CxRsRNAT, a0
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;;
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ldf.fill.nt1 fs18 = [src1]
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ldf.fill.nt1 fs19 = [src2]
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add t7 = CxStFPSR, a0
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;;
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ld8.nt1 loc8 = [t7] // load fpsr from context
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ld8.nt1 loc5 = [t19] // load rnat from context
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nop.i 0
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ld8.fill.nt1 gp = [loc6], CxIntT1 - CxIntGp
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ld8.fill.nt1 t0 = [loc7], CxIntS0 - CxIntT0
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;;
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ld8.fill.nt1 t1 = [loc6], CxIntS1 - CxIntT1
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ld8.fill.nt1 s0 = [loc7], CxIntS2 - CxIntS0
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;;
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ld8.fill.nt1 s1 = [loc6], CxIntS3 - CxIntS1
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ld8.fill.nt1 s2 = [loc7], CxIntV0 - CxIntS2
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;;
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ld8.fill.nt1 s3 = [loc6], CxIntTeb - CxIntS3
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ld8.fill.nt1 v0 = [loc7], CxIntT2 - CxIntV0
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;;
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ld8.fill.nt1 teb = [loc6], CxIntT3 - CxIntTeb
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ld8.fill.nt1 t2 = [loc7], CxIntSp - CxIntT2
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;;
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ld8.fill.nt1 t3 = [loc6], CxIntT4 - CxIntT3
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ld8.fill.nt1 loc4 = [loc7], CxIntT5 - CxIntSp
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;;
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ld8.fill.nt1 t4 = [loc6], CxIntT6 - CxIntT4
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ld8.fill.nt1 t5 = [loc7], CxIntT7 - CxIntT5
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;;
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ld8.fill.nt1 t6 = [loc6], CxIntT8 - CxIntT6
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ld8.fill.nt1 t7 = [loc7], CxIntT9 - CxIntT7
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;;
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ld8.fill.nt1 t8 = [loc6], CxIntT10 - CxIntT8
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ld8.fill.nt1 t9 = [loc7], CxIntT11 - CxIntT9
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;;
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ld8.fill.nt1 t10 = [loc6], CxIntT12 - CxIntT10
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ld8.fill.nt1 t11 = [loc7], CxIntT13 - CxIntT11
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;;
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ld8.fill.nt1 t12 = [loc6], CxIntT14 - CxIntT12
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ld8.fill.nt1 t13 = [loc7], CxIntT15 - CxIntT13
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;;
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ld8.fill.nt1 t14 = [loc6], CxIntT16 - CxIntT14
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ld8.fill.nt1 t15 = [loc7], CxIntT17 - CxIntT15
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;;
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ld8.fill.nt1 t16 = [loc6], CxIntT18 - CxIntT16
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ld8.fill.nt1 t17 = [loc7], CxIntT19 - CxIntT17
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;;
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ld8.fill.nt1 t18 = [loc6], CxIntT20 - CxIntT18
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ld8.fill.nt1 t19 = [loc7], CxIntT21 - CxIntT19
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;;
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ld8.fill.nt1 t20 = [loc6], CxIntT22 - CxIntT20
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ld8.fill.nt1 t21 = [loc7]
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;;
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rsm 1 << PSR_I
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ld8.fill.nt1 t22 = [loc6]
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;;
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rsm 1 << PSR_IC
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movl t0 = 1 << IFS_V
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;;
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mov ar.fpsr = loc8 // set fpsr
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mov ar.unat = loc0
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;;
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srlz.d
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or loc10 = t0, loc10 // set ifs valid bit
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;;
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mov cr.iip = loc9
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mov cr.ifs = loc10
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bsw.0
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;;
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mov cr.dcr = loc1
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mov r17 = loc2 // put BSP in a shadow reg
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or r16 = 0x3, loc3 // put RSE in eager mode
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mov ar.rsc = r0 // put RSE in enforced lazy
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nop.m 0
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add r20 = CxStIPSR, a0
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;;
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ld8.nt1 r20 = [r20] // load IPSR
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mov r18 = loc4 // put SP in a shadow reg
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mov r19 = loc5 // put RNaTs in a shadow reg
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;;
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alloc t0 = 0, 0, 0, 0
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mov cr.ipsr = r20
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mov sp = r18
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;;
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loadrs
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;;
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mov ar.bspstore = r17
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nop.i 0
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;;
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mov ar.rnat = r19 // set rnat register
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mov ar.rsc = r16 // restore RSC
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bsw.1
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;;
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invala
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nop.i 0
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rfi
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;;
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//
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// This label is used to determine the size of the wake dispatcher code in the
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// process of copying it to a free page.
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//
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WakeDispatcherEndLocal::
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LEAF_EXIT(WakeDispatcherEndLocal)
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.sdata
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WakeDispatcherStart::
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data4 @secrel(WakeDispatcherStartLocal)
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WakeDispatcherEnd::
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data4 @secrel(WakeDispatcherEndLocal)
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