1402 lines
35 KiB
C
1402 lines
35 KiB
C
/*++
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Copyright (c) 1989 Microsoft Corporation
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Module Name:
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ixpcidat.c
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Abstract:
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Get/Set bus data routines for the PCI bus
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Author:
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Environment:
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Kernel mode
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Revision History:
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--*/
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#include "bootx86.h"
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#include "arc.h"
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#include "ixfwhal.h"
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#include "ntconfig.h"
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#include "pci.h"
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//extern WCHAR rgzMultiFunctionAdapter[];
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//extern WCHAR rgzConfigurationData[];
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//extern WCHAR rgzIdentifier[];
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//extern WCHAR rgzPCIIdentifier[];
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//
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// Hal specific PCI bus structures
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//
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typedef struct tagPCIPBUSDATA {
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union {
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struct {
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PULONG Address;
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ULONG Data;
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} Type1;
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struct {
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PUCHAR CSE;
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PUCHAR Forward;
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ULONG Base;
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} Type2;
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} Config;
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} PCIPBUSDATA, *PPCIPBUSDATA;
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#define PciBitIndex(Dev,Fnc) (Fnc*32 + Dev);
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#define PCI_CONFIG_TYPE(PciData) ((PciData)->HeaderType & ~PCI_MULTIFUNCTION)
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#define BUSHANDLER _BUSHANDLER
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#define PBUSHANDLER _PBUSHANDLER
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// thunk for NtLdr
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typedef struct {
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ULONG NoBuses;
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ULONG BusNumber;
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PVOID BusData;
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PCIPBUSDATA theBusData;
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} BUSHANDLER, *PBUSHANDLER;
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#define HalpPCIPin2Line(bus,rbus,slot,pcidata)
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#define HalpPCILine2Pin(bus,rbus,slot,pcidata,pcidata2)
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#define ExAllocatePool(a,l) FwAllocatePool(l)
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// thunk for NtLdr
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typedef ULONG (*FncConfigIO) (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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typedef VOID (*FncSync) (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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typedef VOID (*FncReleaseSync) (
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IN PBUSHANDLER BusHandler,
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IN KIRQL Irql
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);
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typedef struct {
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FncSync Synchronize;
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FncReleaseSync ReleaseSynchronzation;
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FncConfigIO ConfigRead[3];
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FncConfigIO ConfigWrite[3];
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} CONFIG_HANDLER, *PCONFIG_HANDLER;
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//
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// Prototypes
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//
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ULONG
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HalpGetPCIData (
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IN ULONG BusNumber,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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ULONG
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HalpSetPCIData (
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IN ULONG BusNumber,
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IN PCI_SLOT_NUMBER SlotNumber,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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extern ULONG
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HalpGetPCIInterruptVector (
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IN PBUSHANDLER BusHandler,
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IN PBUSHANDLER RootHandler,
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IN ULONG BusInterruptLevel,
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IN ULONG BusInterruptVector,
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OUT PKIRQL Irql,
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OUT PKAFFINITY Affinity
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);
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NTSTATUS
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HalpAdjustPCIResourceList (
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IN PBUSHANDLER BusHandler,
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IN PBUSHANDLER RootHandler,
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IN OUT PIO_RESOURCE_REQUIREMENTS_LIST *pResourceList
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);
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NTSTATUS
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HalpAssignPCISlotResources (
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IN ULONG BusNumber,
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IN ULONG SlotNumber,
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IN OUT PCM_RESOURCE_LIST *AllocatedResources
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);
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VOID
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HalpInitializePciBuses (
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VOID
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);
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//VOID
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//HalpPCIPin2Line (
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// IN PBUSHANDLER BusHandler,
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// IN PBUSHANDLER RootHandler,
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// IN PCI_SLOT_NUMBER Slot,
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// IN PPCI_COMMON_CONFIG PciData
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// );
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//
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//VOID
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//HalpPCILine2Pin (
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// IN PBUSHANDLER BusHandler,
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// IN PBUSHANDLER RootHandler,
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// IN PCI_SLOT_NUMBER SlotNumber,
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// IN PPCI_COMMON_CONFIG PciNewData,
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// IN PPCI_COMMON_CONFIG PciOldData
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// );
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BOOLEAN
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HalpValidPCISlot (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot
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);
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VOID
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HalpReadPCIConfig (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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VOID
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HalpWritePCIConfig (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PVOID Buffer,
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IN ULONG Offset,
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IN ULONG Length
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);
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PBUSHANDLER
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HalpGetPciBusHandler (
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IN ULONG BusNumber
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);
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//-------------------------------------------------
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VOID HalpPCISynchronizeType1 (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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VOID HalpPCIReleaseSynchronzationType1 (
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IN PBUSHANDLER BusHandler,
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IN KIRQL Irql
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);
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ULONG HalpPCIReadUlongType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUcharType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUshortType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUlongType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUcharType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUshortType1 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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VOID HalpPCISynchronizeType2 (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PKIRQL Irql,
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IN PVOID State
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);
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VOID HalpPCIReleaseSynchronzationType2 (
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IN PBUSHANDLER BusHandler,
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IN KIRQL Irql
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);
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ULONG HalpPCIReadUlongType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUcharType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIReadUshortType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUlongType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUcharType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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ULONG HalpPCIWriteUshortType2 (
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IN PPCIPBUSDATA BusData,
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IN PVOID State,
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IN PUCHAR Buffer,
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IN ULONG Offset
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);
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#define DISABLE_INTERRUPTS() //_asm { cli }
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#define ENABLE_INTERRUPTS() //_asm { sti }
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//
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// Globals
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//
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ULONG PCIMaxDevice;
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BUSHANDLER PCIBusHandler;
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CONFIG_HANDLER PCIConfigHandlers = {
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HalpPCISynchronizeType1,
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HalpPCIReleaseSynchronzationType1,
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{
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HalpPCIReadUlongType1, // 0
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HalpPCIReadUcharType1, // 1
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HalpPCIReadUshortType1 // 2
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},
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{
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HalpPCIWriteUlongType1, // 0
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HalpPCIWriteUcharType1, // 1
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HalpPCIWriteUshortType1 // 2
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}
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};
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CONFIG_HANDLER PCIConfigHandlersType2 = {
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HalpPCISynchronizeType2,
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HalpPCIReleaseSynchronzationType2,
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{
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HalpPCIReadUlongType2, // 0
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HalpPCIReadUcharType2, // 1
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HalpPCIReadUshortType2 // 2
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},
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{
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HalpPCIWriteUlongType2, // 0
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HalpPCIWriteUcharType2, // 1
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HalpPCIWriteUshortType2 // 2
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}
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};
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UCHAR PCIDeref[4][4] = { {0,1,2,2},{1,1,1,1},{2,1,2,2},{1,1,1,1} };
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VOID
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HalpPCIConfig (
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IN PBUSHANDLER BusHandler,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length,
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IN FncConfigIO *ConfigIO
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);
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VOID
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HalpInitializePciBus (
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VOID
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)
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{
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PPCI_REGISTRY_INFO PCIRegInfo;
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PPCIPBUSDATA BusData;
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PBUSHANDLER Bus;
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PCONFIGURATION_COMPONENT_DATA ConfigData;
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PCM_PARTIAL_RESOURCE_LIST Desc;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR PDesc;
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ULONG i;
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ULONG HwType;
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Bus = &PCIBusHandler;
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PCIBusHandler.BusData = &PCIBusHandler.theBusData;
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PCIRegInfo = NULL; // not found
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ConfigData = NULL; // start at begining
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do {
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ConfigData = KeFindConfigurationNextEntry (
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FwConfigurationTree,
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AdapterClass,
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MultiFunctionAdapter,
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NULL,
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&ConfigData
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);
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if (ConfigData == NULL) {
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// PCI info not found
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return ;
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}
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if (ConfigData->ComponentEntry.Identifier == NULL ||
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_stricmp (ConfigData->ComponentEntry.Identifier, "PCI") != 0) {
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continue;
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}
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PCIRegInfo = NULL;
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Desc = ConfigData->ConfigurationData;
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PDesc = Desc->PartialDescriptors;
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for (i = 0; i < Desc->Count; i++) {
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if (PDesc->Type == CmResourceTypeDeviceSpecific) {
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PCIRegInfo = (PPCI_REGISTRY_INFO) (PDesc+1);
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break;
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}
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PDesc++;
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}
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} while (!PCIRegInfo) ;
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//
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// PCIRegInfo describes the system's PCI support as indicated
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// by the BIOS.
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//
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HwType = PCIRegInfo->HardwareMechanism & 0xf;
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switch (HwType) {
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case 1:
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// this is the default case
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PCIMaxDevice = PCI_MAX_DEVICES;
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break;
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//
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// Type2 does not work MP, nor does the default type2
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// support more the 0xf device slots
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//
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case 2:
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RtlMoveMemory (&PCIConfigHandlers,
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&PCIConfigHandlersType2,
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sizeof (PCIConfigHandlersType2));
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PCIMaxDevice = 0x10;
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break;
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default:
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// unsupport type
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PCIRegInfo->NoBuses = 0;
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}
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PCIBusHandler.NoBuses = PCIRegInfo->NoBuses;
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if (PCIRegInfo->NoBuses) {
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BusData = (PPCIPBUSDATA) Bus->BusData;
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switch (HwType) {
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case 1:
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BusData->Config.Type1.Address = PCI_TYPE1_ADDR_PORT;
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BusData->Config.Type1.Data = PCI_TYPE1_DATA_PORT;
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break;
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case 2:
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BusData->Config.Type2.CSE = PCI_TYPE2_CSE_PORT;
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BusData->Config.Type2.Forward = PCI_TYPE2_FORWARD_PORT;
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BusData->Config.Type2.Base = PCI_TYPE2_ADDRESS_BASE;
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break;
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}
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}
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}
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PBUSHANDLER
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HalpGetPciBusHandler (
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IN ULONG BusNumber
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)
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{
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if (PCIBusHandler.BusData == NULL) {
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HalpInitializePciBus ();
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}
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if (BusNumber > PCIBusHandler.NoBuses) {
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return NULL;
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}
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PCIBusHandler.BusNumber = BusNumber;
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return &PCIBusHandler;
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}
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ULONG
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HalpGetPCIData (
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IN ULONG BusNumber,
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IN PCI_SLOT_NUMBER Slot,
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IN PUCHAR Buffer,
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IN ULONG Offset,
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IN ULONG Length
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)
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/*++
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Routine Description:
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The function returns the Pci bus data for a device.
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Arguments:
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BusNumber - Indicates which bus.
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VendorSpecificDevice - The VendorID (low Word) and DeviceID (High Word)
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Buffer - Supplies the space to store the data.
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Length - Supplies a count in bytes of the maximum amount to return.
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Return Value:
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Returns the amount of data stored into the buffer.
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If this PCI slot has never been set, then the configuration information
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returned is zeroed.
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--*/
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{
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PBUSHANDLER BusHandler;
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PPCI_COMMON_CONFIG PciData;
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UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
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PPCIPBUSDATA BusData;
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ULONG Len;
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BusHandler = HalpGetPciBusHandler (BusNumber);
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if (!BusHandler) {
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return 0;
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}
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if (Length > sizeof (PCI_COMMON_CONFIG)) {
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Length = sizeof (PCI_COMMON_CONFIG);
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}
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Len = 0;
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PciData = (PPCI_COMMON_CONFIG) iBuffer;
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if (Offset >= PCI_COMMON_HDR_LENGTH) {
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//
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// The user did not request any data from the common
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// header. Verify the PCI device exists, then continue
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// in the device specific area.
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//
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HalpReadPCIConfig (BusHandler, Slot, PciData, 0, sizeof(ULONG));
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
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return 0;
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}
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} else {
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//
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// Caller requested at least some data within the
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// common header. Read the whole header, effect the
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// fields we need to and then copy the user's requested
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// bytes from the header
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//
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//
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// Read this PCI devices slot data
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//
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Len = PCI_COMMON_HDR_LENGTH;
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HalpReadPCIConfig (BusHandler, Slot, PciData, 0, Len);
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
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Len = 2; // only return invalid id
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}
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//
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// Has this PCI device been configured?
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//
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BusData = (PPCIPBUSDATA) BusHandler->BusData;
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HalpPCIPin2Line (BusHandler, RootHandler, Slot, PciData);
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//
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// Copy whatever data overlaps into the callers buffer
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//
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if (Len < Offset) {
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// no data at caller's buffer
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return 0;
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}
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Len -= Offset;
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if (Len > Length) {
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Len = Length;
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}
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RtlMoveMemory(Buffer, iBuffer + Offset, Len);
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Offset += Len;
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Buffer += Len;
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Length -= Len;
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}
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if (Length) {
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if (Offset >= PCI_COMMON_HDR_LENGTH) {
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//
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// The remaining Buffer comes from the Device Specific
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// area - put on the kitten gloves and read from it.
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//
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// Specific read/writes to the PCI device specific area
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// are guarenteed:
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//
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// Not to read/write any byte outside the area specified
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// by the caller. (this may cause WORD or BYTE references
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// to the area in order to read the non-dword aligned
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// ends of the request)
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//
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// To use a WORD access if the requested length is exactly
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// a WORD long & WORD aligned.
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//
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// To use a BYTE access if the requested length is exactly
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// a BYTE long.
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//
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HalpReadPCIConfig (BusHandler, Slot, Buffer, Offset, Length);
|
|
Len += Length;
|
|
}
|
|
}
|
|
|
|
return Len;
|
|
}
|
|
|
|
ULONG
|
|
HalpSetPCIData (
|
|
IN ULONG BusNumber,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
The function returns the Pci bus data for a device.
|
|
|
|
Arguments:
|
|
|
|
|
|
VendorSpecificDevice - The VendorID (low Word) and DeviceID (High Word)
|
|
|
|
Buffer - Supplies the space to store the data.
|
|
|
|
Length - Supplies a count in bytes of the maximum amount to return.
|
|
|
|
Return Value:
|
|
|
|
Returns the amount of data stored into the buffer.
|
|
|
|
--*/
|
|
{
|
|
PBUSHANDLER BusHandler;
|
|
PPCI_COMMON_CONFIG PciData, PciData2;
|
|
UCHAR iBuffer[PCI_COMMON_HDR_LENGTH];
|
|
UCHAR iBuffer2[PCI_COMMON_HDR_LENGTH];
|
|
PPCIPBUSDATA BusData;
|
|
ULONG Len;
|
|
|
|
BusHandler = HalpGetPciBusHandler (BusNumber);
|
|
if (!BusHandler) {
|
|
return 0;
|
|
}
|
|
|
|
if (Length > sizeof (PCI_COMMON_CONFIG)) {
|
|
Length = sizeof (PCI_COMMON_CONFIG);
|
|
}
|
|
|
|
Len = 0;
|
|
PciData = (PPCI_COMMON_CONFIG) iBuffer;
|
|
PciData2 = (PPCI_COMMON_CONFIG) iBuffer2;
|
|
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH) {
|
|
//
|
|
// The user did not request any data from the common
|
|
// header. Verify the PCI device exists, then continue in
|
|
// the device specific area.
|
|
//
|
|
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, sizeof(ULONG));
|
|
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID) {
|
|
return 0;
|
|
}
|
|
|
|
} else {
|
|
|
|
//
|
|
// Caller requested to set at least some data within the
|
|
// common header.
|
|
//
|
|
|
|
Len = PCI_COMMON_HDR_LENGTH;
|
|
HalpReadPCIConfig (BusHandler, Slot, PciData, 0, Len);
|
|
if (PciData->VendorID == PCI_INVALID_VENDORID ||
|
|
PCI_CONFIG_TYPE (PciData) != 0) {
|
|
|
|
// no device, or header type unkown
|
|
return 0;
|
|
}
|
|
|
|
//
|
|
// Set this device as configured
|
|
//
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
//
|
|
// Copy COMMON_HDR values to buffer2, then overlay callers changes.
|
|
//
|
|
|
|
RtlMoveMemory (iBuffer2, iBuffer, Len);
|
|
|
|
Len -= Offset;
|
|
if (Len > Length) {
|
|
Len = Length;
|
|
}
|
|
|
|
RtlMoveMemory (iBuffer2+Offset, Buffer, Len);
|
|
|
|
// in case interrupt line or pin was editted
|
|
HalpPCILine2Pin (BusHandler, RootHandler, Slot, PciData2, PciData);
|
|
|
|
//
|
|
// Set new PCI configuration
|
|
//
|
|
|
|
HalpWritePCIConfig (BusHandler, Slot, iBuffer2+Offset, Offset, Len);
|
|
|
|
Offset += Len;
|
|
Buffer += Len;
|
|
Length -= Len;
|
|
}
|
|
|
|
if (Length) {
|
|
if (Offset >= PCI_COMMON_HDR_LENGTH) {
|
|
//
|
|
// The remaining Buffer comes from the Device Specific
|
|
// area - put on the kitten gloves and write it
|
|
//
|
|
// Specific read/writes to the PCI device specific area
|
|
// are guarenteed:
|
|
//
|
|
// Not to read/write any byte outside the area specified
|
|
// by the caller. (this may cause WORD or BYTE references
|
|
// to the area in order to read the non-dword aligned
|
|
// ends of the request)
|
|
//
|
|
// To use a WORD access if the requested length is exactly
|
|
// a WORD long & WORD aligned.
|
|
//
|
|
// To use a BYTE access if the requested length is exactly
|
|
// a BYTE long.
|
|
//
|
|
|
|
HalpWritePCIConfig (BusHandler, Slot, Buffer, Offset, Length);
|
|
Len += Length;
|
|
}
|
|
}
|
|
|
|
return Len;
|
|
}
|
|
|
|
VOID
|
|
HalpReadPCIConfig (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
{
|
|
if (!HalpValidPCISlot (BusHandler, Slot)) {
|
|
//
|
|
// Invalid SlotID return no data
|
|
//
|
|
|
|
RtlFillMemory (Buffer, Length, (UCHAR) -1);
|
|
return ;
|
|
}
|
|
|
|
HalpPCIConfig (BusHandler, Slot, (PUCHAR) Buffer, Offset, Length,
|
|
PCIConfigHandlers.ConfigRead);
|
|
}
|
|
|
|
VOID
|
|
HalpWritePCIConfig (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PVOID Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length
|
|
)
|
|
{
|
|
if (!HalpValidPCISlot (BusHandler, Slot)) {
|
|
//
|
|
// Invalid SlotID do nothing
|
|
//
|
|
return ;
|
|
}
|
|
|
|
HalpPCIConfig (BusHandler, Slot, (PUCHAR) Buffer, Offset, Length,
|
|
PCIConfigHandlers.ConfigWrite);
|
|
}
|
|
|
|
BOOLEAN
|
|
HalpValidPCISlot (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot
|
|
)
|
|
{
|
|
PCI_SLOT_NUMBER Slot2;
|
|
UCHAR HeaderType;
|
|
ULONG i;
|
|
|
|
if (Slot.u.bits.Reserved != 0) {
|
|
return FALSE;
|
|
}
|
|
|
|
if (Slot.u.bits.DeviceNumber >= PCIMaxDevice) {
|
|
return FALSE;
|
|
}
|
|
|
|
if (Slot.u.bits.FunctionNumber == 0) {
|
|
return TRUE;
|
|
}
|
|
|
|
//
|
|
// Non zero function numbers are only supported if the
|
|
// device has the PCI_MULTIFUNCTION bit set in it's header
|
|
//
|
|
|
|
i = Slot.u.bits.DeviceNumber;
|
|
|
|
//
|
|
// Read DeviceNumber, Function zero, to determine if the
|
|
// PCI supports multifunction devices
|
|
//
|
|
|
|
Slot2 = Slot;
|
|
Slot2.u.bits.FunctionNumber = 0;
|
|
|
|
HalpReadPCIConfig (
|
|
BusHandler,
|
|
Slot2,
|
|
&HeaderType,
|
|
FIELD_OFFSET (PCI_COMMON_CONFIG, HeaderType),
|
|
sizeof (UCHAR)
|
|
);
|
|
|
|
if (!(HeaderType & PCI_MULTIFUNCTION) || HeaderType == 0xFF) {
|
|
// this device doesn't exists or doesn't support MULTIFUNCTION types
|
|
return FALSE;
|
|
}
|
|
|
|
return TRUE;
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpPCIConfig (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset,
|
|
IN ULONG Length,
|
|
IN FncConfigIO *ConfigIO
|
|
)
|
|
{
|
|
KIRQL OldIrql;
|
|
ULONG i;
|
|
UCHAR State[20];
|
|
PPCIPBUSDATA BusData;
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
PCIConfigHandlers.Synchronize (BusHandler, Slot, &OldIrql, State);
|
|
|
|
while (Length) {
|
|
i = PCIDeref[Offset % sizeof(ULONG)][Length % sizeof(ULONG)];
|
|
i = ConfigIO[i] (BusData, State, Buffer, Offset);
|
|
|
|
Offset += i;
|
|
Buffer += i;
|
|
Length -= i;
|
|
}
|
|
|
|
PCIConfigHandlers.ReleaseSynchronzation (BusHandler, OldIrql);
|
|
}
|
|
|
|
VOID HalpPCISynchronizeType1 (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PKIRQL Irql,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1
|
|
)
|
|
{
|
|
//
|
|
// Initialize PciCfg1
|
|
//
|
|
|
|
PciCfg1->u.AsULONG = 0;
|
|
PciCfg1->u.bits.BusNumber = BusHandler->BusNumber;
|
|
PciCfg1->u.bits.DeviceNumber = Slot.u.bits.DeviceNumber;
|
|
PciCfg1->u.bits.FunctionNumber = Slot.u.bits.FunctionNumber;
|
|
PciCfg1->u.bits.Enable = TRUE;
|
|
|
|
//
|
|
// Synchronize with PCI type1 config space
|
|
//
|
|
|
|
//KeAcquireSpinLock (&HalpPCIConfigLock, Irql);
|
|
}
|
|
|
|
VOID HalpPCIReleaseSynchronzationType1 (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN KIRQL Irql
|
|
)
|
|
{
|
|
PCI_TYPE1_CFG_BITS PciCfg1;
|
|
PPCIPBUSDATA BusData;
|
|
|
|
//
|
|
// Disable PCI configuration space
|
|
//
|
|
|
|
PciCfg1.u.AsULONG = 0;
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1.u.AsULONG);
|
|
|
|
//
|
|
// Release spinlock
|
|
//
|
|
|
|
//KeReleaseSpinLock (&HalpPCIConfigLock, Irql);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIReadUcharType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1->u.AsULONG);
|
|
*Buffer = READ_PORT_UCHAR ((PUCHAR) (BusData->Config.Type1.Data + i));
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUshortType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1->u.AsULONG);
|
|
*((PUSHORT) Buffer) = READ_PORT_USHORT ((PUSHORT) (BusData->Config.Type1.Data + i));
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUlongType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1->u.AsULONG);
|
|
*((PULONG) Buffer) = READ_PORT_ULONG ((PULONG) BusData->Config.Type1.Data);
|
|
return sizeof (ULONG);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIWriteUcharType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1->u.AsULONG);
|
|
WRITE_PORT_UCHAR ((PUCHAR) (BusData->Config.Type1.Data + i), *Buffer);
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUshortType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
ULONG i;
|
|
|
|
i = Offset % sizeof(ULONG);
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1->u.AsULONG);
|
|
WRITE_PORT_USHORT ((PUSHORT) (BusData->Config.Type1.Data + i), *((PUSHORT) Buffer));
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUlongType1 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE1_CFG_BITS PciCfg1,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg1->u.bits.RegisterNumber = Offset / sizeof(ULONG);
|
|
WRITE_PORT_ULONG (BusData->Config.Type1.Address, PciCfg1->u.AsULONG);
|
|
WRITE_PORT_ULONG ((PULONG) BusData->Config.Type1.Data, *((PULONG) Buffer));
|
|
return sizeof (ULONG);
|
|
}
|
|
|
|
|
|
VOID HalpPCISynchronizeType2 (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN PCI_SLOT_NUMBER Slot,
|
|
IN PKIRQL Irql,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr
|
|
)
|
|
{
|
|
PCI_TYPE2_CSE_BITS PciCfg2Cse;
|
|
PPCIPBUSDATA BusData;
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
|
|
//
|
|
// Initialize Cfg2Addr
|
|
//
|
|
|
|
PciCfg2Addr->u.AsUSHORT = 0;
|
|
PciCfg2Addr->u.bits.Agent = (USHORT) Slot.u.bits.DeviceNumber;
|
|
PciCfg2Addr->u.bits.AddressBase = (USHORT) BusData->Config.Type2.Base;
|
|
|
|
//
|
|
// Synchronize with type2 config space - type2 config space
|
|
// remaps 4K of IO space, so we can not allow other I/Os to occur
|
|
// while using type2 config space, hence the disable_interrupts.
|
|
//
|
|
|
|
//KeAcquireSpinLock (&HalpPCIConfigLock, Irql);
|
|
//DISABLE_INTERRUPTS (); // is not MP safe
|
|
|
|
PciCfg2Cse.u.AsUCHAR = 0;
|
|
PciCfg2Cse.u.bits.Enable = TRUE;
|
|
PciCfg2Cse.u.bits.FunctionNumber = (UCHAR) Slot.u.bits.FunctionNumber;
|
|
PciCfg2Cse.u.bits.Key = 0xff;
|
|
|
|
//
|
|
// Select bus & enable type 2 configuration space
|
|
//
|
|
|
|
WRITE_PORT_UCHAR (BusData->Config.Type2.Forward, (UCHAR) BusHandler->BusNumber);
|
|
WRITE_PORT_UCHAR (BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
|
|
}
|
|
|
|
|
|
VOID HalpPCIReleaseSynchronzationType2 (
|
|
IN PBUSHANDLER BusHandler,
|
|
IN KIRQL Irql
|
|
)
|
|
{
|
|
PCI_TYPE2_CSE_BITS PciCfg2Cse;
|
|
PPCIPBUSDATA BusData;
|
|
|
|
//
|
|
// disable PCI configuration space
|
|
//
|
|
|
|
BusData = (PPCIPBUSDATA) BusHandler->BusData;
|
|
|
|
PciCfg2Cse.u.AsUCHAR = 0;
|
|
WRITE_PORT_UCHAR (BusData->Config.Type2.CSE, PciCfg2Cse.u.AsUCHAR);
|
|
|
|
//
|
|
// Restore interrupts, release spinlock
|
|
//
|
|
|
|
//ENABLE_INTERRUPTS ();
|
|
//KeReleaseSpinLock (&HalpPCIConfigLock, Irql);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIReadUcharType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg2Addr->u.bits.RegisterNumber = (USHORT) Offset;
|
|
*Buffer = READ_PORT_UCHAR ((PUCHAR) PciCfg2Addr->u.AsUSHORT);
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUshortType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg2Addr->u.bits.RegisterNumber = (USHORT) Offset;
|
|
*((PUSHORT) Buffer) = READ_PORT_USHORT ((PUSHORT) PciCfg2Addr->u.AsUSHORT);
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIReadUlongType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg2Addr->u.bits.RegisterNumber = (USHORT) Offset;
|
|
*((PULONG) Buffer) = READ_PORT_ULONG ((PULONG) PciCfg2Addr->u.AsUSHORT);
|
|
return sizeof(ULONG);
|
|
}
|
|
|
|
|
|
ULONG
|
|
HalpPCIWriteUcharType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg2Addr->u.bits.RegisterNumber = (USHORT) Offset;
|
|
WRITE_PORT_UCHAR ((PUCHAR) PciCfg2Addr->u.AsUSHORT, *Buffer);
|
|
return sizeof (UCHAR);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUshortType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg2Addr->u.bits.RegisterNumber = (USHORT) Offset;
|
|
WRITE_PORT_USHORT ((PUSHORT) PciCfg2Addr->u.AsUSHORT, *((PUSHORT) Buffer));
|
|
return sizeof (USHORT);
|
|
}
|
|
|
|
ULONG
|
|
HalpPCIWriteUlongType2 (
|
|
IN PPCIPBUSDATA BusData,
|
|
IN PPCI_TYPE2_ADDRESS_BITS PciCfg2Addr,
|
|
IN PUCHAR Buffer,
|
|
IN ULONG Offset
|
|
)
|
|
{
|
|
PciCfg2Addr->u.bits.RegisterNumber = (USHORT) Offset;
|
|
WRITE_PORT_ULONG ((PULONG) PciCfg2Addr->u.AsUSHORT, *((PULONG) Buffer));
|
|
return sizeof(ULONG);
|
|
}
|
|
|
|
NTSTATUS
|
|
HalpAssignPCISlotResources (
|
|
IN ULONG BusNumber,
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IN ULONG Slot,
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IN OUT PCM_RESOURCE_LIST *pAllocatedResources
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)
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/*++
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Routine Description:
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Reads the targeted device to determine it's required resources.
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Calls IoAssignResources to allocate them.
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Sets the targeted device with it's assigned resoruces
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and returns the assignments to the caller.
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Arguments:
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Return Value:
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STATUS_SUCCESS or error
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--*/
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{
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PBUSHANDLER BusHandler;
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UCHAR buffer[PCI_COMMON_HDR_LENGTH];
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UCHAR buffer2[PCI_COMMON_HDR_LENGTH];
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PPCI_COMMON_CONFIG PciData, PciData2;
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PCI_SLOT_NUMBER PciSlot;
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ULONG i, j, length, type;
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PHYSICAL_ADDRESS Address;
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PCM_PARTIAL_RESOURCE_DESCRIPTOR CmDescriptor;
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static PCM_RESOURCE_LIST CmResList;
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USHORT NewCommand;
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BusHandler = HalpGetPciBusHandler (BusNumber);
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if (!BusHandler) {
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return 0;
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}
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*pAllocatedResources = NULL;
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PciData = (PPCI_COMMON_CONFIG) buffer;
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PciData2 = (PPCI_COMMON_CONFIG) buffer2;
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PciSlot = *((PPCI_SLOT_NUMBER) &Slot);
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BusNumber = BusHandler->BusNumber;
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//
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// Read the PCI device's configuration
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//
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HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
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if (PciData->VendorID == PCI_INVALID_VENDORID) {
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return STATUS_NO_SUCH_DEVICE;
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}
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//
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// Make a copy of the device's current settings
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//
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RtlMoveMemory (buffer2, buffer, PCI_COMMON_HDR_LENGTH);
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//
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// Set resources to all bits on to see what type of resources
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// are required.
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//
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for (j=0; j < PCI_TYPE0_ADDRESSES; j++) {
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PciData->u.type0.BaseAddresses[j] = 0xFFFFFFFF;
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}
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PciData->u.type0.ROMBaseAddress = 0xFFFFFFFF;
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NewCommand = PciData->Command;
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PciData->Command &= ~(PCI_ENABLE_IO_SPACE | PCI_ENABLE_MEMORY_SPACE);
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PciData->u.type0.ROMBaseAddress &= ~PCI_ROMADDRESS_ENABLED;
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HalpWritePCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
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HalpReadPCIConfig (BusHandler, PciSlot, PciData, 0, PCI_COMMON_HDR_LENGTH);
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HalpPCIPin2Line (BusHandler, RootHandler, PciSlot, PciData);
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//
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// Restore the device's settings in case we don't complete
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//
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HalpWritePCIConfig (BusHandler, PciSlot, buffer2, 0, PCI_COMMON_HDR_LENGTH);
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//
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// Build a CmResource descriptor list for the device
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//
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if (!CmResList) {
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// NtLdr pool is only allocated and never freed. Allocate the
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// buffer once, and from then on just use the buffer over
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CmResList = ExAllocatePool (PagedPool,
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sizeof (CM_RESOURCE_LIST) +
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sizeof (CM_PARTIAL_RESOURCE_DESCRIPTOR) * (PCI_TYPE0_ADDRESSES + 2)
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);
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}
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if (!CmResList) {
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return STATUS_NO_MEMORY;
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}
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RtlZeroMemory (CmResList,
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sizeof (CM_RESOURCE_LIST) +
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sizeof (CM_PARTIAL_RESOURCE_DESCRIPTOR) * (PCI_TYPE0_ADDRESSES + 2)
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);
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*pAllocatedResources = CmResList;
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CmResList->List[0].InterfaceType = PCIBus;
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CmResList->List[0].BusNumber = BusNumber;
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CmDescriptor = CmResList->List[0].PartialResourceList.PartialDescriptors;
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if (PciData->u.type0.InterruptPin) {
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CmDescriptor->Type = CmResourceTypeInterrupt;
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CmDescriptor->ShareDisposition = CmResourceShareShared;
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CmDescriptor->Flags = CM_RESOURCE_INTERRUPT_LEVEL_SENSITIVE;
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// in the loader interrupts aren't actually enabled, so just
|
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// pass back the untranslated values
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CmDescriptor->u.Interrupt.Level = PciData->u.type0.InterruptLine;
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CmDescriptor->u.Interrupt.Vector = PciData->u.type0.InterruptLine;
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CmDescriptor->u.Interrupt.Affinity = 1;
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CmResList->List[0].PartialResourceList.Count++;
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CmDescriptor++;
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}
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// clear last address index + 1
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PciData->u.type0.BaseAddresses[PCI_TYPE0_ADDRESSES] = 0;
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if (PciData2->u.type0.ROMBaseAddress & PCI_ROMADDRESS_ENABLED) {
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// put rom address in last index+1
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PciData->u.type0.BaseAddresses[PCI_TYPE0_ADDRESSES] =
|
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PciData->u.type0.ROMBaseAddress & ~PCI_ADDRESS_IO_SPACE;
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|
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PciData2->u.type0.BaseAddresses[PCI_TYPE0_ADDRESSES] =
|
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PciData2->u.type0.ROMBaseAddress & ~PCI_ADDRESS_IO_SPACE;
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}
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for (j=0; j < PCI_TYPE0_ADDRESSES + 1; j++) {
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if (PciData->u.type0.BaseAddresses[j]) {
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i = PciData->u.type0.BaseAddresses[j];
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|
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//
|
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// Make sure the appropriate decode is turned on for this BAR.
|
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//
|
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if (i & PCI_ADDRESS_IO_SPACE) {
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NewCommand |= PCI_ENABLE_IO_SPACE;
|
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} else {
|
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NewCommand |= PCI_ENABLE_MEMORY_SPACE;
|
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}
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|
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// scan for first set bit, that's the length & alignment
|
|
length = 1 << (i & PCI_ADDRESS_IO_SPACE ? 2 : 4);
|
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Address.HighPart = 0;
|
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Address.LowPart = PciData2->u.type0.BaseAddresses[j] & ~(length-1);
|
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while (!(i & length) && length) {
|
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length <<= 1;
|
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}
|
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|
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// translate bus specific address
|
|
type = (i & PCI_ADDRESS_IO_SPACE) ? 0 : 1;
|
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if (!HalTranslateBusAddress (
|
|
PCIBus,
|
|
BusNumber,
|
|
Address,
|
|
&type,
|
|
&Address )) {
|
|
// translation failed, skip it
|
|
continue;
|
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}
|
|
|
|
// fill in CmDescriptor to return
|
|
if (type == 0) {
|
|
CmDescriptor->Type = CmResourceTypePort;
|
|
CmDescriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
CmDescriptor->Flags = CM_RESOURCE_PORT_IO;
|
|
CmDescriptor->u.Port.Length = length;
|
|
CmDescriptor->u.Port.Start = Address;
|
|
} else {
|
|
CmDescriptor->Type = CmResourceTypeMemory;
|
|
CmDescriptor->ShareDisposition = CmResourceShareDeviceExclusive;
|
|
CmDescriptor->Flags = CM_RESOURCE_MEMORY_READ_WRITE;
|
|
CmDescriptor->u.Memory.Length = length;
|
|
CmDescriptor->u.Memory.Start = Address;
|
|
|
|
if (j == PCI_TYPE0_ADDRESSES) {
|
|
// this is a ROM address
|
|
CmDescriptor->Flags = CM_RESOURCE_MEMORY_READ_ONLY;
|
|
}
|
|
}
|
|
|
|
CmResList->List[0].PartialResourceList.Count++;
|
|
CmDescriptor++;
|
|
|
|
if (i & PCI_TYPE_64BIT) {
|
|
// skip upper half of 64 bit address.
|
|
j++;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// If any decodes need to be turned on, do this now.
|
|
//
|
|
if (NewCommand != PciData2->Command) {
|
|
HalpWritePCIConfig(BusHandler,
|
|
PciSlot,
|
|
&NewCommand,
|
|
FIELD_OFFSET(PCI_COMMON_CONFIG, Command),
|
|
sizeof(NewCommand));
|
|
}
|
|
|
|
return STATUS_SUCCESS;
|
|
}
|