531 lines
20 KiB
NASM
531 lines
20 KiB
NASM
title "PC+MP configuration table processing"
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;++
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;
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;Copyright (c) 1991 Microsoft Corporation
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;Copyright (c) 1992 Intel Corporation
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;All rights reserved
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;
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;INTEL CORPORATION PROPRIETARY INFORMATION
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;
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;This software is supplied to Microsoft under the terms
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;of a license agreement with Intel Corporation and may not be
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;copied nor disclosed except in accordance with the terms
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;of that agreement.
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;
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;
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;Module Name:
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;
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; mpconfig.asm
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;
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;Abstract:
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;
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; Build the default PC+MP configuration tables defined in the PC+MP
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; specification. This file contains no code. It statically builds the
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; default PC+MP configurations in data. C code declaring structures to
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; use these tables must use the "pack(1)" pragma to ensure they are byte
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; aligned.
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;
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;
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;Author:
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;
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; Rajesh Shah (Intel) Oct 1993
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;
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;Revision History:
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;
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;--
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.386p
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include pcmp.inc
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include apic.inc
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;
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; Entry size in bytes for Bus entries, Io Apic entries, Io Apic interrupt
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; input entries and Local Apic interrupt input entries in the PC+MP table.
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;
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COMMON_ENTRY_SIZE equ 08H
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;
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; Default values for Processor entries in the PC+MP table.
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;
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DEFAULT_NUM_CPUS equ 02H
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PROC_ENTRY_SIZE equ 14H
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CPU_i486 equ 0421H
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CPU_FEATURES equ 01H ; On-chip FPU
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;
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; Default Apic Version values.
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;
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VERSION_82489DX equ 01H ; 8 bit APIC version register value.
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VERSION_INTEGRATED equ 11H ; 8 bit APIC version register value.
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;
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; Default values for Bus entries in the PC+MP table
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;
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BUS_ID_0 equ 0H
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BUS_INTI_POLARITY equ 0H
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BUS_INTI_LEVEL equ 0H
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; Macros to emit the 6 byte bus type string. The string is not
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; NULL terminated. If the Bus string consists of less than 6
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; characters, it is padded with space characters(ASCII 20h).
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BUS_TYPE_EISA macro
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db "EISA "
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endm
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BUS_TYPE_ISA macro
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db "ISA "
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endm
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BUS_TYPE_PCI macro
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db "PCI "
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endm
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BUS_TYPE_MCA macro
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db "MCA "
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endm
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;
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; Macros to build the different parts of the PC+MP table. See pcmp.inc
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; for the layout of the table and its entries.
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; Macro to build the HEADER part of the PC+MP table.
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; It takes a parameter (NumOfEntries) that specifies the total number of
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; data entries in the table. Processor entries are 20(decimal) bytes long,
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; all other entry types are 8 bytes long. All default configurations have
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; 2 processors. The table length is computed based on the NumOfEntries
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; parameter.
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;
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Header macro NumEntries
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dd PCMP_SIGNATURE ;; ASCII "PCMP"
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dw ( (DEFAULT_NUM_CPUS * PROC_ENTRY_SIZE) \
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+ ((NumEntries - DEFAULT_NUM_CPUS) * COMMON_ENTRY_SIZE)\
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+ HEADER_SIZE ) ;; Total table length
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db 1 ;; PC+MP spec. revision
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db 0 ;; Checksum
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db 8 dup (0) ;; OEM Id
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db 12 dup (0) ;; OEM Product Id
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dd 0 ;; OEM table pointer
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dw 0 ;; OEM table size
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dw NumOfEntries ;; Number of entries in DATA portion
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dd LU_BASE_ADDRESS ;; Default Loacal Apic address
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dd 0 ;; Reserved (Not Used)
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endm ;;Header
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;
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; Macro to build Processor entries of the PC+MP table
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;
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; Parameter ApicVersion specifes the Apic version (82489DX or integrated)
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; Parameter IsBsp is used in the CPU Flags field, and specifies if this
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; processor is the BSP processor
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;
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Processor macro LocalApicId, ApicVersion, IsBspCpu
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db ENTRY_PROCESSOR ;; Processor entry type
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db LocalApicId ;; ID of Loacal Apic unit.
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db ApicVersion ;; Must agree with IO Apic Version
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db CPU_ENABLED OR IsBspCpu ;; CpuFlags
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dd CPU_i486 ;; Default CPU type
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dd CPU_FEATURES ;; Default CPU features
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db 8 dup (0) ;; Reserved
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endm ;Processor
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;
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; Macro to build Bus entries of the PC+MP table
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;
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Bus macro BusId, BusString
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db ENTRY_BUS ;; Bus entry type
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db BusId ;; ID of this bus
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BusString ;; This parameter is a macro that
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;; emits the 6 byte bus type string.
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endm ;Bus
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;
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; Macro to build Io Apic entries of the PC+MP table
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; Parameter IoApicVersion specifes the Apic version (82489DX or integrated)
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; All default configurations have a single IO Apic.
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;
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IoApic macro IoApicVersion
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db ENTRY_IOAPIC ;; IO APIC entry type
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db IOUNIT_APIC_ID ;; Default Io Apic ID
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db IoApicVersion ;; Must agree with Local APIC ver.
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db IO_APIC_ENABLED ;; enable the IO APIC by default,
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dd IO_BASE_ADDRESS ;; Default physical address of 1st
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;; IO APIC.
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endm ;IoApic
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;
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; Macro to build Io Apic interrupt input entries of the PC+MP table
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; Since all default configurations have a single IO Apic, all the IO Apic
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; interrput input entries are built for the default IO Apic. For all default
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; configurations, the interrupt source bus is assumed to have a bus ID 0.
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;
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IoApicInti macro IntType,SourceBusIrq,ApicInti
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db ENTRY_INTI ;; IO Apic interrupt input entry type
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db IntType ;; NMI,SMI,ExtINT or INTR
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dw BUS_INTI_POLARITY OR BUS_INTI_LEVEL ;; Default polarity and level
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db BUS_ID_0 ;; Bus Id on which interrupt arrives
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db SourceBusIrq ;; Bus relative IRQ at which
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;; interrupt arrives
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db IOUNIT_APIC_ID ;; Apic Id of destination IO Apic
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db ApicInti ;; Io Apic Interrupt input pin
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;; number this interrupt goes to
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endm ;IoApicInti
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;
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; Macro to build Io Apic interrupt input entries of the PC+MP table
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; Since all default configurations have a single IO Apic, all the IO Apic
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; interrput input entries are built for the default IO Apic. For all default
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; configurations, the interrupt source bus is assumed to have a bus ID 0.
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;
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ApicInti macro IntType,SourceBusId,SourceBusIrq,AInti
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db ENTRY_INTI ;; IO Apic interrupt input entry type
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db IntType ;; NMI,SMI,ExtINT or INTR
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dw BUS_INTI_POLARITY OR BUS_INTI_LEVEL ;; Default polarity and level
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db SourceBusId ;; Bus Id on which interrupt arrives
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db SourceBusIrq ;; Bus relative IRQ at which
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;; interrupt arrives
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db IOUNIT_APIC_ID ;; Apic Id of destination IO Apic
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db AInti ;; Io Apic Interrupt input pin
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;; number this interrupt goes to
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endm ;ApicInti
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;
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; Macro to build Local Apic interruptinput entries of the PC+MP table
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;
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Linti macro IntType,SourceBusId,SourceBusIrq,LocalApicId,ApicInti
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db ENTRY_LINTI ;; Local Apic Interrupt Input
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db IntType ;; NMI,SMI,ExtINT or INTR.
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dw BUS_INTI_POLARITY OR BUS_INTI_LEVEL ;; Polarity and level
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db SourceBusId ;; Bus Id on which interrupt arrives
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db SourceBusIrq ;; Bus relative IRQ at which
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;; interrupt arrives
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db LocalApicId ;; Apic Id of destination Local Apic
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db ApicInti ;; Local Apic Interrupt input pin
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;; number this interrupt goes to
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endm ;Linti
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PAGELK SEGMENT DWORD PUBLIC 'CODE'
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; The PC+MP table consists of a fixed size HEADER and a variable
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; number of DATA entries. The order of the DATA entries is as
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; follows:
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;
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; 1) Processor entries (20 decimal bytes long). The Boot Strap
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; Processor (BSP) entry must be the first entry.
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; 2) Bus entries (8 bytes long).
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; 3) IO Apic entries (8 bytes long).
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; 4) IO Apic interrupt input entries (8 bytes long).
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; 5) Local Apic interrupt input entries (8 bytes long).
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;
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; All interrupting devices are connected to Bus ID 0 in the
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; default configurations.
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;
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; Any C code using these tables must use the pack(1) pragma.
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;
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; PC+MP default configuration 1: ISA bus, 82489DX Apic.
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;
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public _PcMpDefaultConfig1
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_PcMpDefaultConfig1 label byte
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; Create table HEADER.
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Header 14h
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; Create processor entries
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Processor 0, VERSION_82489DX, BSP_CPU
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Processor 1, VERSION_82489DX, 0
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; Create bus entries
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Bus 0, BUS_TYPE_ISA
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; Create IO Apic entries.
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IoApic VERSION_82489DX
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; Create IO Apic interrupt input entries.
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IoApicInti INT_TYPE_INTR,1,1 ; IO APIC IRQ 1, INTIN 1
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IoApicInti INT_TYPE_INTR,0,2 ; IO APIC IRQ 0, INTIN 2
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IoApicInti INT_TYPE_INTR,3,3 ; IO APIC IRQ 3, INTIN 3
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IoApicInti INT_TYPE_INTR,4,4 ; IO APIC IRQ 4, INTIN 4
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IoApicInti INT_TYPE_INTR,5,5 ; IO APIC IRQ 5, INTIN 5
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IoApicInti INT_TYPE_INTR,6,6 ; IO APIC IRQ 6, INTIN 6
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IoApicInti INT_TYPE_INTR,7,7 ; IO APIC IRQ 7, INTIN 7
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IoApicInti INT_TYPE_INTR,8,8 ; IO APIC IRQ 8, INTIN 8
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IoApicInti INT_TYPE_INTR,9,9 ; IO APIC IRQ 9, INTIN 9
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IoApicInti INT_TYPE_INTR,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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IoApicInti INT_TYPE_INTR,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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IoApicInti INT_TYPE_INTR,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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IoApicInti INT_TYPE_INTR,0dH,0dH ; IO APIC IRQ 13, INTIN 13
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IoApicInti INT_TYPE_INTR,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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IoApicInti INT_TYPE_INTR,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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; Create Local Apic interrupt input entries.
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Linti INT_TYPE_NMI,0,2,0,1 ; IRQ 2,LocalApicId 0,Linti 1
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;
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; PC+MP default configuration 2: EISA bus, 82489DX Apic.
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;
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public _PcMpDefaultConfig2
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_PcMpDefaultConfig2 label byte
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; Create table HEADER.
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Header 14h
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; Create processor entries
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Processor 0H, VERSION_82489DX, BSP_CPU
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Processor 01H, VERSION_82489DX, 0
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; Create bus entries
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Bus 0, BUS_TYPE_EISA
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; Create IO Apic entries.
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IoApic VERSION_82489DX
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; Create IO Apic interrupt input entries.
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; In configuration 2, the 8259 PIC fields the timer and DMA interrupts.
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; The PIC is connected to interrupt input pin 0 of the IO Apic, so this
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; IO Apic interrupt pin can get 2 different interrupts.
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IoApicInti INT_TYPE_EXTINT,0,0 ; IO APIC IRQ 0, INTIN 0
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IoApicInti INT_TYPE_EXTINT,0dh,0 ; IO APIC IRQ 13, INTIN 0
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IoApicInti INT_TYPE_INTR,1,1 ; IO APIC IRQ 1, INTIN 1
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; In this configuration, NMI comes through IO Apic interrupt
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; input pin 2. In all other configurations, NMI comes through
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; the Local Apic interrupt input LINTIN1
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IoApicInti INT_TYPE_NMI,2,2 ; IO APIC IRQ 2, INTIN 2
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IoApicInti INT_TYPE_INTR,3,3 ; IO APIC IRQ 3, INTIN 3
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IoApicInti INT_TYPE_INTR,4,4 ; IO APIC IRQ 4, INTIN 4
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IoApicInti INT_TYPE_INTR,5,5 ; IO APIC IRQ 5, INTIN 5
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IoApicInti INT_TYPE_INTR,6,6 ; IO APIC IRQ 6, INTIN 6
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IoApicInti INT_TYPE_INTR,7,7 ; IO APIC IRQ 7, INTIN 7
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IoApicInti INT_TYPE_INTR,8,8 ; IO APIC IRQ 8, INTIN 8
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IoApicInti INT_TYPE_INTR,9,9 ; IO APIC IRQ 9, INTIN 9
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IoApicInti INT_TYPE_INTR,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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IoApicInti INT_TYPE_INTR,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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IoApicInti INT_TYPE_INTR,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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IoApicInti INT_TYPE_INTR,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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IoApicInti INT_TYPE_INTR,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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;
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; PC+MP default configuration 3: EISA bus, 82489DX Apic, timer(Inti2)
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;
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public _PcMpDefaultConfig3
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_PcMpDefaultConfig3 label byte
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; Create table HEADER.
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Header 14h
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; Create processor entries
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Processor 0H, VERSION_82489DX, BSP_CPU
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Processor 01H, VERSION_82489DX, 0
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; Create bus entries
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Bus 0, BUS_TYPE_EISA
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; Create IO Apic entries.
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IoApic VERSION_82489DX
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; Create IO Apic interrupt input entries.
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IoApicInti INT_TYPE_INTR,1,1 ; IO APIC IRQ 1, INTIN 1
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IoApicInti INT_TYPE_INTR,0,2 ; IO APIC IRQ 0, INTIN 2
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IoApicInti INT_TYPE_INTR,3,3 ; IO APIC IRQ 3, INTIN 3
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IoApicInti INT_TYPE_INTR,4,4 ; IO APIC IRQ 4, INTIN 4
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IoApicInti INT_TYPE_INTR,5,5 ; IO APIC IRQ 5, INTIN 5
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IoApicInti INT_TYPE_INTR,6,6 ; IO APIC IRQ 6, INTIN 6
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IoApicInti INT_TYPE_INTR,7,7 ; IO APIC IRQ 7, INTIN 7
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IoApicInti INT_TYPE_INTR,8,8 ; IO APIC IRQ 8, INTIN 8
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IoApicInti INT_TYPE_INTR,9,9 ; IO APIC IRQ 9, INTIN 9
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IoApicInti INT_TYPE_INTR,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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IoApicInti INT_TYPE_INTR,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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IoApicInti INT_TYPE_INTR,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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IoApicInti INT_TYPE_INTR,0dH,0dH ; IO APIC IRQ 13, INTIN 13
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IoApicInti INT_TYPE_INTR,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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IoApicInti INT_TYPE_INTR,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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; Create Local Apic interrupt input entries.
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Linti INT_TYPE_NMI,0,2,0,1 ; IRQ 2,LocalApicId 0,Linti 1
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;
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; PC+MP default configuration 4: MCA bus, 82489DX Apic.
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;
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public _PcMpDefaultConfig4
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_PcMpDefaultConfig4 label byte
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; Create table HEADER.
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Header 14h
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; Create processor entries
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Processor 0H, VERSION_82489DX, BSP_CPU
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Processor 01H, VERSION_82489DX, 0
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; Create bus entries
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Bus 0, BUS_TYPE_MCA
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; Create IO Apic entries.
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IoApic VERSION_82489DX
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; Create IO Apic interrupt input entries.
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IoApicInti INT_TYPE_INTR,1,1 ; IO APIC IRQ 1, INTIN 1
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IoApicInti INT_TYPE_INTR,0,2 ; IO APIC IRQ 0, INTIN 2
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IoApicInti INT_TYPE_INTR,3,3 ; IO APIC IRQ 3, INTIN 3
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IoApicInti INT_TYPE_INTR,4,4 ; IO APIC IRQ 4, INTIN 4
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IoApicInti INT_TYPE_INTR,5,5 ; IO APIC IRQ 5, INTIN 5
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IoApicInti INT_TYPE_INTR,6,6 ; IO APIC IRQ 6, INTIN 6
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IoApicInti INT_TYPE_INTR,7,7 ; IO APIC IRQ 7, INTIN 7
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IoApicInti INT_TYPE_INTR,8,8 ; IO APIC IRQ 8, INTIN 8
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IoApicInti INT_TYPE_INTR,9,9 ; IO APIC IRQ 9, INTIN 9
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IoApicInti INT_TYPE_INTR,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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IoApicInti INT_TYPE_INTR,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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IoApicInti INT_TYPE_INTR,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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IoApicInti INT_TYPE_INTR,0dH,0dH ; IO APIC IRQ 13, INTIN 13
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IoApicInti INT_TYPE_INTR,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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IoApicInti INT_TYPE_INTR,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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; Create Local Apic interrupt input entries.
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Linti INT_TYPE_NMI,0,2,0,1 ; IRQ 2,LocalApicId 0,Linti 1
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;
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; PC+MP default configuration 5: ISA & PCI bus, Integrated Local Apic
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;
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public _PcMpDefaultConfig5
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_PcMpDefaultConfig5 label byte
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; Create table HEADER.
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Header 15h
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; Create processor entries
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Processor 0H, VERSION_INTEGRATED, BSP_CPU
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Processor 01H, VERSION_INTEGRATED, 0
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; Create bus entries
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Bus 1, BUS_TYPE_ISA
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Bus 0, BUS_TYPE_PCI
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; Create IO Apic entries.
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IoApic VERSION_INTEGRATED
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; Create IO Apic interrupt input entries.
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ApicInti INT_TYPE_INTR,1,1,1 ; IO APIC IRQ 1, INTIN 1
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ApicInti INT_TYPE_INTR,1,0,2 ; IO APIC IRQ 0, INTIN 2
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ApicInti INT_TYPE_INTR,1,3,3 ; IO APIC IRQ 3, INTIN 3
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ApicInti INT_TYPE_INTR,1,4,4 ; IO APIC IRQ 4, INTIN 4
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ApicInti INT_TYPE_INTR,1,5,5 ; IO APIC IRQ 5, INTIN 5
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ApicInti INT_TYPE_INTR,1,6,6 ; IO APIC IRQ 6, INTIN 6
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ApicInti INT_TYPE_INTR,1,7,7 ; IO APIC IRQ 7, INTIN 7
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ApicInti INT_TYPE_INTR,1,8,8 ; IO APIC IRQ 8, INTIN 8
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ApicInti INT_TYPE_INTR,1,9,9 ; IO APIC IRQ 9, INTIN 9
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ApicInti INT_TYPE_INTR,1,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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ApicInti INT_TYPE_INTR,1,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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ApicInti INT_TYPE_INTR,1,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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ApicInti INT_TYPE_INTR,1,0dH,0dH ; IO APIC IRQ 13, INTIN 13
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ApicInti INT_TYPE_INTR,1,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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ApicInti INT_TYPE_INTR,1,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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; Create Local Apic interrupt input entries.
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Linti INT_TYPE_NMI,1,2,0,1 ; IRQ 2,LocalApicId 0,Linti 1
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;
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; PC+MP default configuration 6 EISA & PCI bus, Integrated Local Apic
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;
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public _PcMpDefaultConfig6
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_PcMpDefaultConfig6 label byte
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; Create table HEADER.
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Header 15h
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; Create processor entries
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Processor 0H, VERSION_INTEGRATED, BSP_CPU
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Processor 1H, VERSION_INTEGRATED, 0
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; Create bus entries
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Bus 1, BUS_TYPE_EISA
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Bus 0, BUS_TYPE_PCI
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; Create IO Apic entries.
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IoApic VERSION_INTEGRATED
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; Create IO Apic interrupt input entries.
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ApicInti INT_TYPE_INTR,1,1,1 ; IO APIC IRQ 1, INTIN 1
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ApicInti INT_TYPE_INTR,1,0,2 ; IO APIC IRQ 0, INTIN 2
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ApicInti INT_TYPE_INTR,1,3,3 ; IO APIC IRQ 3, INTIN 3
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ApicInti INT_TYPE_INTR,1,4,4 ; IO APIC IRQ 4, INTIN 4
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ApicInti INT_TYPE_INTR,1,5,5 ; IO APIC IRQ 5, INTIN 5
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ApicInti INT_TYPE_INTR,1,6,6 ; IO APIC IRQ 6, INTIN 6
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ApicInti INT_TYPE_INTR,1,7,7 ; IO APIC IRQ 7, INTIN 7
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ApicInti INT_TYPE_INTR,1,8,8 ; IO APIC IRQ 8, INTIN 8
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ApicInti INT_TYPE_INTR,1,9,9 ; IO APIC IRQ 9, INTIN 9
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ApicInti INT_TYPE_INTR,1,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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ApicInti INT_TYPE_INTR,1,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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ApicInti INT_TYPE_INTR,1,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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ApicInti INT_TYPE_INTR,1,0dH,0dH ; IO APIC IRQ 13, INTIN 13
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ApicInti INT_TYPE_INTR,1,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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ApicInti INT_TYPE_INTR,1,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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; Create Local Apic interrupt input entries.
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Linti INT_TYPE_NMI,1,2,0,1 ; IRQ 2,LocalApicId 0,Linti 1
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;
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; PC+MP default configuration 7: MCA & PCI bus, Integrated Local Apic
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;
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public _PcMpDefaultConfig7
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_PcMpDefaultConfig7 label byte
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; Create table HEADER.
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Header 15h
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; Create processor entries
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Processor 0H, VERSION_INTEGRATED, BSP_CPU
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Processor 01H, VERSION_INTEGRATED, 0
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; Create bus entries
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Bus 1, BUS_TYPE_MCA
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Bus 0, BUS_TYPE_PCI
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; Create IO Apic entries.
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IoApic VERSION_INTEGRATED
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; Create IO Apic interrupt input entries.
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ApicInti INT_TYPE_INTR,1,1,1 ; IO APIC IRQ 1, INTIN 1
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ApicInti INT_TYPE_INTR,1,0,2 ; IO APIC IRQ 0, INTIN 2
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ApicInti INT_TYPE_INTR,1,3,3 ; IO APIC IRQ 3, INTIN 3
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ApicInti INT_TYPE_INTR,1,4,4 ; IO APIC IRQ 4, INTIN 4
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ApicInti INT_TYPE_INTR,1,5,5 ; IO APIC IRQ 5, INTIN 5
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ApicInti INT_TYPE_INTR,1,6,6 ; IO APIC IRQ 6, INTIN 6
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ApicInti INT_TYPE_INTR,1,7,7 ; IO APIC IRQ 7, INTIN 7
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ApicInti INT_TYPE_INTR,1,8,8 ; IO APIC IRQ 8, INTIN 8
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ApicInti INT_TYPE_INTR,1,9,9 ; IO APIC IRQ 9, INTIN 9
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ApicInti INT_TYPE_INTR,1,0ah,0ah ; IO APIC IRQ 10, INTIN 10
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ApicInti INT_TYPE_INTR,1,0bh,0bh ; IO APIC IRQ 11, INTIN 11
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ApicInti INT_TYPE_INTR,1,0ch,0ch ; IO APIC IRQ 12, INTIN 12
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ApicInti INT_TYPE_INTR,1,0dH,0dH ; IO APIC IRQ 13, INTIN 13
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ApicInti INT_TYPE_INTR,1,0eH,0eH ; IO APIC IRQ 14, INTIN 14
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ApicInti INT_TYPE_INTR,1,0fH,0fH ; IO APIC IRQ 15, INTIN 15
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; Create Local Apic interrupt input entries.
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Linti INT_TYPE_NMI,1,2,0,1 ; IRQ 2,LocalApicId 0,Linti 1
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;
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; Pointers to the default configuration tables
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;
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public _PcMpDefaultTablePtrs
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; Array of pointers to the default configurations.
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_PcMpDefaultTablePtrs label byte
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dd offset _PcMpDefaultConfig1 ; Pointer to Default Config 1
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dd offset _PcMpDefaultConfig2 ; Pointer to Default Config 2
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dd offset _PcMpDefaultConfig3 ; Pointer to Default Config 3
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dd offset _PcMpDefaultConfig4 ; Pointer to Default Config 4
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dd offset _PcMpDefaultConfig5 ; Pointer to Default Config 5
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dd offset _PcMpDefaultConfig6 ; Pointer to Default Config 6
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dd offset _PcMpDefaultConfig7 ; Pointer to Default Config 7
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PAGELK ENDS
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end
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