1134 lines
30 KiB
NASM
1134 lines
30 KiB
NASM
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title "Interprocessor Interrupt"
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;++
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;
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;Copyright (c) 1991 Microsoft Corporation
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;Copyright (c) 1992 Intel Corporation
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;All rights reserved
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;
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;INTEL CORPORATION PROPRIETARY INFORMATION
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;
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;This software is supplied to Microsoft under the terms
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;of a license agreement with Intel Corporation and may not be
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;copied nor disclosed except in accordance with the terms
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;of that agreement.
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;
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;
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;Module Name:
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;
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; mpipi.asm
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;
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;Abstract:
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;
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; PC+MP IPI code.
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; Provides the HAL support for Interprocessor Interrupts and Processor
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; initialization for PC+MP Systems
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;
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;Author:
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;
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; Ken Reneris (kenr) 13-Jan-1992
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;
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;Revision History:
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;
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; Ron Mosgrove (Intel) Aug 1993
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; Modified for PC+MP Systems
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;--
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.486p
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.xlist
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;
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; Normal includes
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;
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include hal386.inc
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include i386\kimacro.inc
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include mac386.inc
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include apic.inc
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include callconv.inc ; calling convention macros
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include ntapic.inc
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EXTRNP Kei386EoiHelper,0,IMPORT
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EXTRNP _HalBeginSystemInterrupt,3
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EXTRNP _HalEndSystemInterrupt,2
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EXTRNP _KiIpiServiceRoutine,2,IMPORT
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EXTRNP _HalDisplayString,1
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EXTRNP HalpAcquireHighLevelLock,1,,FASTCALL
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EXTRNP HalpReleaseHighLevelLock,2,,FASTCALL
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ifdef ACPI_HAL
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EXTRNP _DetectAcpiMP,2
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else
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EXTRNP _DetectMPS,1
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endif
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EXTRNP _HalpRegisterKdSupportFunctions,1
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EXTRNP _HalpInitializeLocalUnit,0
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EXTRNP _HalpResetThisProcessor,0
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if DBG OR DEBUGGING
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EXTRNP _DbgBreakPoint,0,IMPORT
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endif
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extrn _HalpDefaultInterruptAffinity:DWORD
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extrn _HalpActiveProcessors:DWORD
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extrn _HalpGlobal8259Mask:WORD
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extrn _HalpStaticIntAffinity:BYTE
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extrn _HalpPICINTToVector:BYTE
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extrn _rgzBadHal:BYTE
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extrn _HalpMaxProcsPerCluster:BYTE
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extrn _HalpIntDestMap:BYTE
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I386_80387_BUSY_PORT equ 0f0h
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SEND_IPI macro IpiCommand
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; Assumption:
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; TargetProcessors KAFFINITY value is in eax at entry
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; IpiCommand is a constant(i.e. an immediate value not in a register)
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local HsiGetProcessor, HsiGetNextProcInCluster, HsiDone, HsiSendIpi
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local HsiUseClusterMode, HsiExit
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cmp _HalpMaxProcsPerCluster, 0
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jne HsiUseClusterMode
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; Fewer than 8 processors. Use APIC flat logical mode to send IPI.
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shl eax, DESTINATION_SHIFT
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pushfd
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cli
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STALL_WHILE_APIC_BUSY
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mov dword ptr APIC[LU_INT_CMD_HIGH], eax
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APICFIX edx
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mov dword ptr APIC[LU_INT_CMD_LOW], IpiCommand
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STALL_WHILE_APIC_BUSY
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popfd
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jmp HsiExit
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; Use APIC cluster mode to send IPI
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HsiUseClusterMode:
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pushad
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pushfd
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mov ch, 0ffh
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HsiGetProcessor:
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test eax, eax
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jz HsiDone
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@@:
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inc ch
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shr eax, 1
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jnc @b
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; Found a processor. Get its hardware processor bitmask
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xor ebx, ebx ; Avoid partial stall on PentiumPro
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mov bl, ch
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add ebx, offset _HalpIntDestMap
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movzx edx, byte ptr[ebx]
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; Search for other target processors with the same cluster ID
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mov edi, eax
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mov cl, 0ffh
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HsiGetNextProcInCluster:
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test edi, edi
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jz HsiSendIpi
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@@:
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inc cl
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shr edi, 1
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jnc @b
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xor ebx, ebx
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mov bl, cl
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add bl, ch
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add ebx, offset _HalpIntDestMap
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inc ebx ; Both cl and ch indices are zero based
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movzx esi, byte ptr[ebx]
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mov ebx, esi
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; Compare cluster ID of new processor with current processor
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; Note that 0 is a valid cluster ID
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shr bl, 4
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mov bh, dl
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shr bh, 4
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cmp bl, bh
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jne HsiGetNextProcInCluster
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; Found another target processor with the same cluster ID. Or it in.
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or edx, esi
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; Remove this new processor from the set of remaining processors
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mov esi, 1
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shl esi, cl
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not esi
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and eax, esi
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jmp HsiGetNextProcInCluster
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HsiSendIpi:
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; (edx) = Target Processor bitmask
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shl edx, DESTINATION_SHIFT
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cli
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STALL_WHILE_APIC_BUSY
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mov dword ptr APIC[LU_INT_CMD_HIGH], edx
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APICFIX edx
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mov dword ptr APIC[LU_INT_CMD_LOW], IpiCommand
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STALL_WHILE_APIC_BUSY
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jmp HsiGetProcessor
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HsiDone:
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popfd
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popad
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HsiExit:
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endm ;; SEND_IPI
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_DATA SEGMENT DWORD PUBLIC 'DATA'
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ALIGN dword
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public _HalpProcessorPCR
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_HalpProcessorPCR dd MAXIMUM_PROCESSORS dup (?) ; PCR pointer for each processor
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;
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; The following symbols are used by the Local Apic Error handler.
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;
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LogApicErrors equ 1
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if LogApicErrors
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public _HalpLocalApicErrorLock
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public _HalpLocalApicErrorCount
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public _HalpApicErrorLog
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APIC_ERROR_LOG_SIZE equ 128 ; Must be 2^n see usage below
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ALIGN dword
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_HalpApicErrorLog dw APIC_ERROR_LOG_SIZE dup(0)
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_HalpLocalApicErrorLock dd 0
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_HalpLocalApicErrorCount dd 0
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;
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; Bit:
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;
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; 0 - Send checksum error
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; 1 - Recieve checksum error
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; 2 - Send accept error
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; 3 - Receive accept error
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; 4 - reserved
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; 5 - Send illegal vector
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; 6 - Receive illegal vector
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; 7 - illegal register address
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; 8-31 - reserved
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;
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endif ; LogApicErrors
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public HalpBroadcastLock, HalpBroadcastTargets
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public HalpBroadcastFunction, HalpBroadcastContext
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HalpBroadcastLock dd 0
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HalpBroadcastFunction dd 0
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HalpBroadcastContext dd 0
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HalpBroadcastTargets dd 0
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_DATA ends
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_TEXT SEGMENT DWORD PUBLIC 'DATA'
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ALIGN dword
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;
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; The _PicExtintIntiHandlers and the _PicNopIntiHandlers tables are
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; used by the enable and disable system interrupt routines to determine
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; the EXTINT interrupt handler to install.
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;
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public _PicExtintIntiHandlers
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_PicExtintIntiHandlers label dword
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dd PicInterruptHandlerInti0 ; Inti 0 - PIC 1
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dd PicInterruptHandlerInti1 ; Inti 1 - PIC 1
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dd PicInterruptHandlerInti2 ; Inti 2 - PIC 1
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dd PicInterruptHandlerInti3 ; Inti 3 - PIC 1
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dd PicInterruptHandlerInti4 ; Inti 4 - PIC 1
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dd PicInterruptHandlerInti5 ; Inti 5 - PIC 1
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dd PicInterruptHandlerInti6 ; Inti 6 - PIC 1
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dd PicInterruptHandlerInti7 ; Inti 7 - PIC 1
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dd PicInterruptHandlerInti8 ; Inti 8 - PIC 2
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dd PicInterruptHandlerInti9 ; Inti 9 - PIC 2
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dd PicInterruptHandlerIntiA ; Inti 10 - PIC 2
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dd PicInterruptHandlerIntiB ; Inti 11 - PIC 2
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dd PicInterruptHandlerIntiC ; Inti 12 - PIC 2
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dd PicInterruptHandlerIntiD ; Inti 13 - PIC 2
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dd PicInterruptHandlerIntiE ; Inti 14 - PIC 2
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dd PicInterruptHandlerIntiF ; Inti 15 - PIC 2
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public _PicNopIntiHandlers
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_PicNopIntiHandlers label dword
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dd PicNopHandlerInti0 ; Inti 0 - PIC 1
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dd PicNopHandlerInti1 ; Inti 1 - PIC 1
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dd PicNopHandlerInti2 ; Inti 2 - PIC 1
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dd PicNopHandlerInti3 ; Inti 3 - PIC 1
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dd PicNopHandlerInti4 ; Inti 4 - PIC 1
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dd PicNopHandlerInti5 ; Inti 5 - PIC 1
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dd PicNopHandlerInti6 ; Inti 6 - PIC 1
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dd PicNopHandlerInti7 ; Inti 7 - PIC 1
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dd CommonPic2NopHandler ; Inti 8 - PIC 2
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dd CommonPic2NopHandler ; Inti 9 - PIC 2
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dd CommonPic2NopHandler ; Inti 10 - PIC 2
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dd CommonPic2NopHandler ; Inti 11 - PIC 2
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dd CommonPic2NopHandler ; Inti 12 - PIC 2
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dd PicNopHandlerIntiD ; Inti 13 - PIC 2
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dd CommonPic2NopHandler ; Inti 14 - PIC 2
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dd CommonPic2NopHandler ; Inti 15 - PIC 2
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_TEXT ends
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page ,132
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subttl "Post InterProcessor Interrupt"
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_TEXT SEGMENT DWORD PUBLIC 'CODE'
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;
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; VOID
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; HalInitializeProcessor(
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; ULONG Number
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; PVOID LoaderBlock
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; );
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;
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;Routine Description:
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;
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; Initialize hal pcr values for current processor (if any)
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; (called shortly after processor reaches kernel, before
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; HalInitSystem if P0)
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;
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; IPI's and KeReadir/LowerIrq's must be available once this function
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; returns. (IPI's are only used once two or more processors are
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; available)
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;
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; . Enable IPI interrupt (makes sense for P1, P2, ...).
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; . Save Processor Number in PCR.
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; . if (P0)
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; . determine if the system is a PC+MP,
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; . if not a PC+MP System Halt;
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; . Enable IPI's on CPU.
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;
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;Arguments:
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;
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; Number - Logical processor number of calling processor
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalInitializeProcessor ,2
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mov PCR[PcIDR], 0FFFFFFFFH ; mark all INTs as disabled
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movzx eax, byte ptr [esp+4]
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mov PCR[PcHal.PcrNumber], al ; Save processor # in PCR
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mov ecx, PCR[PcSelfPcr] ; Flat address of this PCR
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mov _HalpProcessorPCR[eax*4], ecx ; Save it away
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mov dword ptr PCR[PcStallScaleFactor], INITIAL_STALL_COUNT
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;
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; set bit in affinity mask for this active processor
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;
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lock bts _HalpActiveProcessors, eax
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;
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; set interrupt affinity to either be most-significant processor or
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; a set of all processors
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;
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mov edx, eax
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mov eax, _HalpDefaultInterruptAffinity
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hip10: cmp _HalpStaticIntAffinity, 1 ; Signle or all?
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sbb ecx, ecx ; set mask 0 or -1
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and ecx, eax ; include existing set or not
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bts ecx, edx ; include self
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cmp ecx, eax ; new mask a better choice?
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jc short hip20 ; no, done
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lock cmpxchg _HalpDefaultInterruptAffinity, ecx ; set new mask
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jnz short hip10 ; if it didn't take, do it again
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hip20:
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;
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; Most of the following code is only needed on P0
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;
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or edx, edx
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jnz PnInitCode ; Not P0 skip a lot
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; Run on P0 only
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;
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; Determine if the system we are on is an PC+MP
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;
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; DetectMPS has a parameter we don't currently use. It's a boolean
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; which is set to TRUE if the system we're on is a MP system. Remember,
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; we could have a UP PC+MP system.
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;
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; The DetectMPS routine also allocates Virtual Addresses for all of
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; the APIC's in the system (it needs to access the devices anyway so ...)
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;
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sub esp, 4
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ifdef ACPI_HAL
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mov eax, esp
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stdCall _DetectAcpiMP <eax, [esp + 12]> ; Are we running on an ACPI MP
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else
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stdCall _DetectMPS <esp> ; Are we running on an PC+MP
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endif
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add esp,4
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cmp eax, 0 ; Yes (nonZero) or
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je NotPcMp ; No (Zero)
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; stdCall _HalDisplayString, <offset HalSignonString>
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;
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; This next call has nothing to do with processor init.
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; But this is the only function in the HAL that gets
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; called before KdInit.
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;
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stdCall _HalpRegisterKdSupportFunctions <[esp + 8]>
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mov ax, 0FFFFH ; mask all PIC interrupts
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mov _HalpGlobal8259Mask, ax ; save the mask
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SET_8259_MASK
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;
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; Other P0 initialization would go here
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;
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jmp CommonInitCode
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PnInitCode:
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;
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; Pn initialization goes here
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;
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CommonInitCode:
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stdCall _HalInitApicInterruptHandlers
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;
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; initialize the APIC local unit for this Processor
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;
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stdCall _HalpInitializeLocalUnit
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stdRET _HalInitializeProcessor
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NotPcMp:
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stdCall _HalDisplayString, <offset _rgzBadHal>
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hlt
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stdENDP _HalInitializeProcessor
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D_INT032 EQU 8E00h ; access word for 386 ring 0 interrupt gate
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;++
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;
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; VOID
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; HalInitApicInterruptHandlers(
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; );
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;
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;Routine Description:
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;
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; This routine installs the interrupt vector in the IDT for the APIC
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; spurious interrupt.
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;
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;Arguments:
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;
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; None.
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;
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;Return Value:
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;
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; None.
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;
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;--
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cPublicProc _HalInitApicInterruptHandlers ,0
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enter 8,0 ; setup ebp, reserve 8 bytes of stack
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sidt fword ptr [ebp-8] ; get IDT address
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mov edx, [ebp-6] ; (edx)->IDT
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mov ecx, PIC1_SPURIOUS_VECTOR ; Spurious Vector
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mov eax, offset FLAT:PicSpuriousService37
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mov word ptr [edx+8*ecx], ax ; Lower half of handler addr
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mov word ptr [edx+8*ecx+2], KGDT_R0_CODE ; set up selector
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mov word ptr [edx+8*ecx+4], D_INT032 ; 386 interrupt gate
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shr eax, 16 ; (ax)=higher half of handler addr
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mov word ptr [edx+8*ecx+6], ax
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mov ecx, APIC_SPURIOUS_VECTOR ; Apic Spurious Vector
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mov eax, offset FLAT:_HalpApicSpuriousService
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mov word ptr [edx+8*ecx], ax ; Lower half of handler addr
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mov word ptr [edx+8*ecx+2], KGDT_R0_CODE ; set up selector
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mov word ptr [edx+8*ecx+4], D_INT032 ; 386 interrupt gate
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shr eax, 16 ; (ax)=higher half of handler addr
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mov word ptr [edx+8*ecx+6], ax
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leave
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stdRET _HalInitApicInterruptHandlers
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stdENDP _HalInitApicInterruptHandlers
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cPublicProc PicSpuriousService37 ,0
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iretd
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stdENDP PicSpuriousService37
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;++
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;
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; VOID
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; HalpApicRebootService(
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; );
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;
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;Routine Description:
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;
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; This is the ISR that handles Reboot events
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;
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;--
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ENTER_DR_ASSIST HReboot_a, HReboot_t
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cPublicProc _HalpApicRebootService ,0
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ENTER_INTERRUPT_FORCE_STATE HReboot_a, HReboot_t ; (ebp) -> Trap frame
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mov eax, APIC_REBOOT_VECTOR
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mov ecx, dword ptr APIC[LU_TPR] ; get the old TPR
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push ecx ; save it
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mov dword ptr APIC[LU_TPR], eax ; set the TPR
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APICFIX edx
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;
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; EOI the local APIC, warm reset does not reset the 82489 APIC
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; so if we don't EOI here we'll never see an interrupt after
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; the reboot.
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;
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mov dword ptr APIC[LU_EOI], 0 ; send EOI to APIC local unit
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stdCall _HalpResetThisProcessor
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;
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; We should never get here, but just in case someone is stepping
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; through this
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;
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pop eax
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mov dword ptr APIC[LU_TPR], eax ; reset the TPR
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APICFIX edx
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;
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; Do interrupt exit processing without EOI
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;
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SPURIOUS_INTERRUPT_EXIT
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stdENDP _HalpApicRebootService
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;++
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;
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; VOID
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; HalpGenericCallService(
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; );
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;
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; Routine Description:
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; This is the ISR that handles the GenericCall interrupt
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;
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;--
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ENTER_DR_ASSIST HGeneric_a, HGeneric_t
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cPublicProc _HalpBroadcastCallService ,0
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ENTER_INTERRUPT HGeneric_a, HGeneric_t ; (ebp) -> Trap frame
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;
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; (esp) - base of trap frame
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;
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; dismiss interrupt and raise Irql
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;
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push APIC_GENERIC_VECTOR
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sub esp, 4 ; allocate space to save OldIrql
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stdCall _HalBeginSystemInterrupt, <CLOCK2_LEVEL-1,APIC_GENERIC_VECTOR,esp>
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|
|
|
call _HalpPollForBroadcast
|
|
|
|
INTERRUPT_EXIT ; lower irql to old value, iret
|
|
|
|
stdENDP _HalpBroadcastCallService
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpGenericCall(
|
|
; IN VOID (*WorkerFunction)(VOID),
|
|
; IN ULONG Context,
|
|
; IN KAFFINITY TargetProcessors
|
|
; );
|
|
;
|
|
; Routine Description:
|
|
; Causes the WorkerFunction to be called on the specified target
|
|
; processors. The WorkerFunction is called at CLOCK2_LEVEL-1
|
|
; (Must be below IPI_LEVEL in order to prevent system deadlocks).
|
|
;
|
|
; Enviroment:
|
|
; Must be called with interrupts enabled.
|
|
; Must be called with IRQL = CLOCK2_LEVEL-1
|
|
;--
|
|
|
|
cPublicProc _HalpGenericCall,3
|
|
cPublicFpo 3, 0
|
|
|
|
GENERIC_IPI equ (DELIVER_FIXED OR LOGICAL_DESTINATION OR ICR_USE_DEST_FIELD OR APIC_GENERIC_VECTOR)
|
|
|
|
@@: call _HalpPollForBroadcast
|
|
test HalpBroadcastLock, 1 ; Is broadcast busy?
|
|
jnz short @b ; Yes, wait
|
|
|
|
lock bts HalpBroadcastLock, 0 ; Try to get lock
|
|
jc short @b ; didn't get it, loop
|
|
|
|
hgc30: mov ecx, [esp+4]
|
|
mov edx, [esp+8]
|
|
mov eax, [esp+12]
|
|
mov HalpBroadcastFunction, ecx
|
|
mov HalpBroadcastContext, edx
|
|
mov HalpBroadcastTargets, eax
|
|
|
|
or eax, eax ; (eax) = Targets
|
|
jz gc90
|
|
|
|
SEND_IPI GENERIC_IPI
|
|
|
|
;
|
|
; Wait for all processors to call broadcast function
|
|
;
|
|
|
|
@@: call _HalpPollForBroadcast
|
|
cmp HalpBroadcastTargets, 0
|
|
jnz short @b
|
|
|
|
gc90: mov HalpBroadcastLock, 0 ; Release BroadcastLock
|
|
stdRET _HalpGenericCall
|
|
|
|
stdENDP _HalpGenericCall
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; _HalpPollForBroadcast (
|
|
; VOID
|
|
; );
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; IRQL = CLOCK2_LEVEL-1
|
|
;--
|
|
cPublicProc _HalpPollForBroadcast, 0
|
|
cPublicFpo 0, 0
|
|
mov eax, PCR[PcSetMember]
|
|
test HalpBroadcastTargets, eax
|
|
jz short pb90
|
|
|
|
mov ecx, HalpBroadcastFunction ; Pickup broadcast function
|
|
push HalpBroadcastContext
|
|
|
|
not eax ; Remove our bit from destionations
|
|
lock and HalpBroadcastTargets, eax
|
|
|
|
call ecx
|
|
|
|
pb90: stdRET _HalpPollForBroadcast
|
|
|
|
stdENDP _HalpPollForBroadcast
|
|
|
|
;++
|
|
;
|
|
; ULONG
|
|
; FASTCALL
|
|
; HalpWaitForPending (
|
|
; ULONG Count (ecx)
|
|
; PULONG LuICR (edx)
|
|
; );
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; Waits for DELIVERY_PENDING to clear and returns remaining iteration count
|
|
;--
|
|
cPublicFastCall HalpWaitForPending, 2
|
|
cPublicFpo 0, 0
|
|
|
|
wfp10: test dword ptr [edx], DELIVERY_PENDING
|
|
jz short wfp20
|
|
|
|
dec ecx
|
|
jnz short wfp10
|
|
|
|
wfp20: mov eax, ecx
|
|
fstRet HalpWaitForPending
|
|
|
|
fstENDP HalpWaitForPending
|
|
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpLocalApicErrorService(
|
|
; );
|
|
;
|
|
;Routine Description:
|
|
;
|
|
; This routine fields Local APIC error Events
|
|
;
|
|
;--
|
|
|
|
ENTER_DR_ASSIST HApicErr_a, HApicErr_t
|
|
|
|
cPublicProc _HalpLocalApicErrorService ,0
|
|
|
|
;
|
|
; Save machine state in trap frame
|
|
;
|
|
|
|
ENTER_INTERRUPT HApicErr_a, HApicErr_t ; (ebp) -> Trap frame
|
|
|
|
if LogApicErrors
|
|
|
|
lea ecx, _HalpLocalApicErrorLock
|
|
fstCall HalpAcquireHighLevelLock
|
|
push eax
|
|
|
|
mov eax, _HalpLocalApicErrorCount
|
|
inc _HalpLocalApicErrorCount
|
|
|
|
lea ecx, _HalpApicErrorLog
|
|
|
|
and eax, APIC_ERROR_LOG_SIZE-1
|
|
shl eax, 1
|
|
add ecx, eax
|
|
|
|
endif ; LogApicErrors
|
|
|
|
mov dword ptr APIC[LU_EOI], 0 ; local unit EOI
|
|
APICFIX eax
|
|
|
|
;
|
|
; The Apic EDS (Rev 4.0) says you have to write before you read
|
|
; this doesn't work. The write clears the status bits.
|
|
; But P6 works as according to the EDS!
|
|
;
|
|
|
|
mov eax, PCR[PcPrcb]
|
|
cmp byte ptr [eax].PbCpuType, 6
|
|
jc short lae10
|
|
mov dword ptr APIC[LU_ERROR_STATUS], 0
|
|
|
|
lae10:
|
|
mov eax, dword ptr APIC[LU_ERROR_STATUS] ; read error status
|
|
|
|
|
|
; Find out what kind of error it is and update the appropriate count.
|
|
|
|
if LogApicErrors
|
|
; out 80h, al
|
|
mov byte ptr [ecx], al
|
|
inc ecx
|
|
mov al, byte ptr PCR[PcHal.PcrNumber]
|
|
mov byte ptr [ecx], al
|
|
|
|
lea ecx, _HalpLocalApicErrorLock
|
|
pop edx
|
|
fstCall HalpReleaseHighLevelLock
|
|
|
|
endif ; LogApicErrors
|
|
|
|
SPURIOUS_INTERRUPT_EXIT ; exit interrupt without eoi
|
|
stdENDP _HalpLocalApicErrorService
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalRequestIpi(
|
|
; IN ULONG Mask
|
|
; );
|
|
;
|
|
;Routine Description:
|
|
;
|
|
; Requests an interprocessor interrupt
|
|
;
|
|
;Arguments:
|
|
;
|
|
; Mask - Supplies a mask of the processors to be interrupted
|
|
;
|
|
;Return Value:
|
|
;
|
|
; None.
|
|
;
|
|
;--
|
|
APIC_IPI equ (DELIVER_FIXED OR LOGICAL_DESTINATION OR ICR_USE_DEST_FIELD OR APIC_IPI_VECTOR)
|
|
|
|
cPublicProc _HalRequestIpi ,1
|
|
cPublicFpo 1, 0
|
|
|
|
mov eax, [esp+4] ; (eax) = Processor bitmask
|
|
|
|
SEND_IPI APIC_IPI
|
|
|
|
stdRET _HalRequestIpi
|
|
|
|
stdENDP _HalRequestIpi
|
|
|
|
page ,132
|
|
subttl "PC+MP IPI Interrupt Handler"
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpIpiHandler (
|
|
; );
|
|
;
|
|
; Routine Description:
|
|
;
|
|
; This routine is entered as the result of an interrupt generated by inter
|
|
; processor communication.
|
|
;
|
|
; Arguments:
|
|
;
|
|
; None.
|
|
;
|
|
; Return Value:
|
|
;
|
|
; None.
|
|
;
|
|
;--
|
|
|
|
ENTER_DR_ASSIST Hipi_a, Hipi_t
|
|
|
|
cPublicProc _HalpIpiHandler ,0
|
|
|
|
;
|
|
; Save machine state in trap frame
|
|
;
|
|
|
|
ENTER_INTERRUPT Hipi_a, Hipi_t ; (ebp) -> Trap frame
|
|
|
|
;
|
|
; Save previous IRQL
|
|
;
|
|
push APIC_IPI_VECTOR ; Vector
|
|
sub esp, 4 ; space for OldIrql
|
|
;
|
|
; We now dismiss the interprocessor interrupt and call its handler
|
|
;
|
|
|
|
stdCall _HalBeginSystemInterrupt,<IPI_LEVEL,APIC_IPI_VECTOR,esp>
|
|
|
|
stdCall _KiIpiServiceRoutine, <ebp,0>
|
|
|
|
;
|
|
; Do interrupt exit processing
|
|
;
|
|
|
|
INTERRUPT_EXIT ; will return to caller
|
|
|
|
stdENDP _HalpIpiHandler
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; HalpApicSpuriousService(
|
|
; );
|
|
;
|
|
;Routine Description:
|
|
;
|
|
; A place for spurious interrupts to end up.
|
|
;
|
|
;--
|
|
cPublicProc _HalpApicSpuriousService,0
|
|
iretd
|
|
stdENDP _HalpApicSpuriousService
|
|
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; _PicInterruptHandlerIntiXX(
|
|
; );
|
|
;
|
|
;Routine Description:
|
|
;
|
|
; These handlers receive interrupts from the PIC and reissues them via
|
|
; a vector at the proper priority level. This is used to provide a symetric
|
|
; interrupt distribution on a non symetric system.
|
|
;
|
|
; The PIC interrupts will normally only be received (in the PC+MP Hal) via an
|
|
; interrupt input from on either the IO Unit or the Local unit which has been
|
|
; programed as EXTINT. EXTINT interrupts are received outside of the APIC
|
|
; priority structure (the PIC provides the vector). We use the APIC ICR to
|
|
; generate interrupts to the proper handler at the proper priority.
|
|
;
|
|
; The EXTINT interrupts are directed to a single processor, currently P0.
|
|
; There is no good reason why they can't be directed to another processor.
|
|
;
|
|
; Since one processor must absorb the overhead of redistributing PIC interrupts
|
|
; the interrupt handling on a system using EXTINT interrupts is not symetric.
|
|
;
|
|
;--
|
|
|
|
ENTER_DR_ASSIST Hcpic_a, Hcpic_t
|
|
|
|
cPublicProc PicHandler ,0
|
|
|
|
PicInterruptHandlerInti0:
|
|
push 0
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti1:
|
|
push 1
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti2:
|
|
push 2
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti3:
|
|
push 3
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti4:
|
|
push 4
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti5:
|
|
push 5
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti6:
|
|
push 6
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti7:
|
|
;
|
|
; Check to see if this is a spurious interrupt
|
|
;
|
|
push eax
|
|
mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
|
|
out PIC1_PORT0, al
|
|
IODelay ; delay
|
|
in al, PIC1_PORT0 ; (al) = content of PIC 1 ISR
|
|
test al, 10000000B ; Is In-Service register set?
|
|
pop eax
|
|
jz short pic7_spurious ;
|
|
|
|
push 7
|
|
jmp short CommonPicHandler
|
|
|
|
picf_spurious:
|
|
mov al, OCW2_SPECIFIC_EOI OR SlavePicInti ; specific eoi to master for pic2 eoi
|
|
out PIC1_PORT0, al
|
|
pop eax
|
|
pic7_spurious:
|
|
iretd ; ignore PIC
|
|
|
|
PicInterruptHandlerInti8:
|
|
push 8
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerInti9:
|
|
push 9
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerIntiA:
|
|
push 10
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerIntiB:
|
|
push 11
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerIntiC:
|
|
push 12
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerIntiD:
|
|
push 13
|
|
push eax
|
|
xor eax, eax
|
|
out I386_80387_BUSY_PORT, al
|
|
pop eax
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerIntiE:
|
|
push 14
|
|
jmp short CommonPicHandler
|
|
|
|
PicInterruptHandlerIntiF:
|
|
push eax
|
|
mov al, OCW3_READ_ISR ; tell 8259 we want to read ISR
|
|
out PIC2_PORT0, al
|
|
IODelay ; delay
|
|
in al, PIC2_PORT0 ; (al) = content of PIC 1 ISR
|
|
test al, 10000000B ; Is In-Service register set?
|
|
jz short picf_spurious ; Go eoi PIC1 & Ignore PIC2
|
|
|
|
pop eax
|
|
push 15
|
|
jmp short CommonPicHandler
|
|
|
|
CommonPicHandler:
|
|
ENTER_INTERRUPT Hcpic_a, Hcpic_t,PassDwordParm ; (ebp) -> Trap frame
|
|
|
|
;
|
|
; Need to determine if we have a level interrupt and if so don't EOI it
|
|
; It should be EOI'd by end system interrupt
|
|
;
|
|
|
|
cmp bl, 8 ; Pic or Slave Pic
|
|
jae short cph20
|
|
|
|
mov al, bl
|
|
or al, OCW2_SPECIFIC_EOI ; specific eoi
|
|
out PIC1_PORT0, al ; dismiss the interrupt
|
|
jmp short cph30
|
|
|
|
cph20:
|
|
mov al, OCW2_NON_SPECIFIC_EOI ; send non specific eoi to slave
|
|
out PIC2_PORT0, al
|
|
mov al, OCW2_SPECIFIC_EOI OR SlavePicInti ; specific eoi to master for pic2 eoi
|
|
out PIC1_PORT0, al ; send irq2 specific eoi to master
|
|
|
|
cph30:
|
|
mov al, _HalpPICINTToVector[ebx] ; Get vector for PIC interrupt
|
|
or al, al ; Is vector known?
|
|
jz short cph90 ; No, don't dispatch it
|
|
|
|
;
|
|
; Now gain exclusive access to the ICR
|
|
;
|
|
|
|
STALL_WHILE_APIC_BUSY
|
|
|
|
cmp bl, 8
|
|
je short HandleClockInti
|
|
|
|
;
|
|
; Write the IPI Command to the Memory Mapped Register
|
|
;
|
|
|
|
mov dword ptr APIC[LU_INT_CMD_HIGH], DESTINATION_ALL_CPUS
|
|
APICFIX edx
|
|
mov dword ptr APIC[LU_INT_CMD_LOW], eax
|
|
jmp short cph90
|
|
|
|
|
|
HandleClockInti:
|
|
;
|
|
; Write the IPI Command to the Memory Mapped Register
|
|
;
|
|
|
|
mov dword ptr APIC[LU_INT_CMD_LOW], (DELIVER_FIXED OR ICR_SELF OR APIC_CLOCK_VECTOR)
|
|
|
|
|
|
cph90: APICFIX edx
|
|
SPURIOUS_INTERRUPT_EXIT ; exit interrupt without eoi
|
|
|
|
stdENDP PicHandler
|
|
|
|
|
|
;++
|
|
;
|
|
; VOID
|
|
; _PicXXNopHandler(
|
|
; );
|
|
;
|
|
;Routine Description:
|
|
;
|
|
; These handlers are designed to be installed on a system to field any PIC
|
|
; interrupts when there are not supposed to be any delivered.
|
|
;
|
|
; In the Debug case this routine increments an error count EOI's the PIC and
|
|
; returns. Normally the increment is not performed.
|
|
;--
|
|
|
|
|
|
|
|
cPublicProc PicNopHandler ,0
|
|
|
|
PicNopHandlerInti0:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 0
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti1:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 1
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti2:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 2
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti3:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 3
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti4:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 4
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti5:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 5
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti6:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 6
|
|
jmp short CommonPic1NopHandler
|
|
|
|
PicNopHandlerInti7:
|
|
push eax ; Save Scratch Registers
|
|
mov al, 7
|
|
|
|
CommonPic1NopHandler:
|
|
;
|
|
; Need to determine if we have a level interrupt and if so don't EOI it
|
|
; It should be EOI'd by end system interrupt
|
|
;
|
|
|
|
or al, OCW2_SPECIFIC_EOI ; specific eoi
|
|
out PIC1_PORT0, al ; dismiss the interrupt
|
|
pop eax ; Restore Scratch registers
|
|
iretd
|
|
|
|
PicNopHandlerIntiD:
|
|
push eax
|
|
xor eax, eax
|
|
out I386_80387_BUSY_PORT, al
|
|
pop eax
|
|
|
|
CommonPic2NopHandler:
|
|
push eax
|
|
|
|
;
|
|
; Need to determine if we have a level interrupt and if so don't EOI it
|
|
; It should be EOI'd by end system interrupt
|
|
;
|
|
|
|
mov al, OCW2_NON_SPECIFIC_EOI ; send non specific eoi to slave
|
|
out PIC2_PORT0, al
|
|
mov al, OCW2_SPECIFIC_EOI OR SlavePicInti ; specific eoi to master for pic2 eoi
|
|
out PIC1_PORT0, al ; send irq2 specific eoi to master
|
|
pop eax
|
|
iretd
|
|
|
|
stdENDP PicNopHandler
|
|
|
|
|
|
_TEXT ENDS
|
|
|
|
END
|