1279 lines
30 KiB
C
1279 lines
30 KiB
C
/*++
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Module Name:
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ixmca.c
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Abstract:
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HAL component of the Machine Check Architecture.
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All exported MCA functionality is present in this file.
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Author:
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Srikanth Kambhatla (Intel)
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Revision History:
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Anil Aggarwal (Intel)
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Changes incorporated as per design review with Microsoft
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--*/
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#include <bugcodes.h>
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#include <halp.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <nthal.h>
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//
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// Structure to keep track of MCA features available on installed hardware
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//
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typedef struct _MCA_INFO {
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FAST_MUTEX Mutex;
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UCHAR NumBanks; // Number of Banks present
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ULONGLONG Bank0Config; // Bank0 configuration setup by BIOS.
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// This will be used as mask when
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// setting up bank 0
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MCA_DRIVER_INFO DriverInfo; // Info about registered driver
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KDPC Dpc; // DPC object for MCA
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} MCA_INFO, *PMCA_INFO;
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//
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// Default MCA Bank configuration
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//
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#define MCA_DEFAULT_BANK_CONF 0xFFFFFFFFFFFFFFFF
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//
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// MCA architecture related defines
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//
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#define MCA_NUM_REGS 4
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#define MCE_VALID 0x01
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#define MCA_VECTOR 18
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//
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// MSR register addresses for MCA
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//
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#define MCG_CAP 0x179
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#define MCG_STATUS 0x17a
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#define MCG_CTL 0x17b
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#define MCG_EAX 0x180
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#define MCG_EBX 0x181
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#define MCG_ECX 0x182
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#define MCG_EDX 0x183
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#define MCG_ESI 0x184
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#define MCG_EDI 0x185
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#define MCG_EBP 0x186
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#define MCG_ESP 0x187
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#define MCG_EFLAGS 0x188
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#define MCG_EIP 0x189
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#define MC0_CTL 0x400
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#define MC0_STATUS 0x401
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#define MC0_ADDR 0x402
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#define MC0_MISC 0x403
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#define PENTIUM_MC_ADDR 0x0
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#define PENTIUM_MC_TYPE 0x1
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//
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// Bit Masks for MCG_CAP
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//
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#define MCA_CNT_MASK 0xFF
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#define MCG_CTL_PRESENT 0x100
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#define MCG_EXT_PRESENT 0x200
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typedef struct _MCG_CAPABILITY {
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union {
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struct {
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ULONG McaCnt:8;
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ULONG McaCntlPresent:1;
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ULONG McaExtPresent:1;
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ULONG Reserved_1: 6;
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ULONG McaExtCnt: 8;
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ULONG Reserved_2: 8;
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ULONG Reserved_3;
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} hw;
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ULONGLONG QuadPart;
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} u;
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} MCG_CAPABILITY, *PMCG_CAPABILITY;
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//
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// V2 defines up through Eip
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//
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#define MCG_EFLAGS_OFFSET (MCG_EFLAGS-MCG_EAX+1)
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//
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// Writing all 1's to MCG_CTL register enables logging.
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//
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#define MCA_MCGCTL_ENABLE_LOGGING 0xffffffffffffffff
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//
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// Bit interpretation of MCG_STATUS register
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//
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#define MCG_MC_INPROGRESS 0x4
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#define MCG_EIP_VALID 0x2
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#define MCG_RESTART_EIP_VALID 0x1
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//
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// For the function that reads the error reporting bank log, the type of error we
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// are interested in
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//
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#define MCA_GET_ANY_ERROR 0x1
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#define MCA_GET_NONRESTARTABLE_ERROR 0x2
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//
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// Defines for the size of TSS and the initial stack to operate on
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//
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#define MINIMUM_TSS_SIZE 0x68
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//
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// Global Varibles
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//
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MCA_INFO HalpMcaInfo;
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BOOLEAN HalpMcaInterfaceLocked;
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extern KAFFINITY HalpActiveProcessors;
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#if !defined(_WIN64) || defined(PICACPI)
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extern UCHAR HalpClockMcaQueueDpc;
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#endif
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extern UCHAR MsgMCEPending[];
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extern WCHAR rgzSessionManager[];
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extern WCHAR rgzEnableMCE[];
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extern WCHAR rgzEnableMCA[];
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//
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// External prototypes
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//
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VOID
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HalpMcaCurrentProcessorSetTSS (
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IN PULONG pTSS
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);
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#if !defined(_AMD64_)
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VOID
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HalpSetCr4MCEBit (
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VOID
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);
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#endif // _AMD64_
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//
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// Internal prototypes
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//
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VOID
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HalpMcaInit (
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VOID
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);
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NTSTATUS
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HalpMcaReadProcessorException (
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IN OUT PMCA_EXCEPTION Exception,
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IN BOOLEAN NonRestartableOnly
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);
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VOID
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HalpMcaQueueDpc(
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VOID
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);
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VOID
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HalpMcaGetConfiguration (
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OUT PULONG MCEEnabled,
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OUT PULONG MCAEnabled
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);
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VOID
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HalpMcaLockInterface(
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VOID
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);
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VOID
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HalpMcaUnlockInterface(
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VOID
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);
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NTSTATUS
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HalpMcaReadRegisterInterface(
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IN UCHAR BankNumber,
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IN OUT PMCA_EXCEPTION Exception
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);
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#ifdef ALLOC_PRAGMA
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#pragma alloc_text(INIT, HalpMcaInit)
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#pragma alloc_text(PAGELK, HalpMcaCurrentProcessorSetConfig)
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#pragma alloc_text(INIT, HalpMcaGetConfiguration)
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#pragma alloc_text(PAGE, HalpGetMcaLog)
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#pragma alloc_text(PAGE, HalpMcaRegisterDriver)
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#pragma alloc_text(PAGE, HalpMcaLockInterface)
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#pragma alloc_text(PAGE, HalpMcaUnlockInterface)
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#endif
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//
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// Register names for registers starting at MCG_EAX
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//
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char *RegNames[] = {
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"eax", "ebx", "ecx", "edx", "esi", "edi", "ebp", "esp", "eflags", "eip"
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};
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#define REGNAMECNT (sizeof(RegNames)/sizeof(RegNames[0]))
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VOID
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HalpMcaLockInterface(
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VOID
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)
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{
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ExAcquireFastMutex(&HalpMcaInfo.Mutex);
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#if DBG
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ASSERT(HalpMcaInterfaceLocked == FALSE);
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HalpMcaInterfaceLocked = TRUE;
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#endif
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}
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VOID
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HalpMcaUnlockInterface(
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VOID
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)
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{
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ExReleaseFastMutex(&HalpMcaInfo.Mutex);
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#if DBG
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ASSERT(HalpMcaInterfaceLocked == TRUE);
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HalpMcaInterfaceLocked = FALSE;
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#endif
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}
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//
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// All the initialization code for MCA goes here
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//
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VOID
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HalpMcaInit (
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VOID
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)
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/*++
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Routine Description:
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This routine is called to do all the initialization work
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Arguments:
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None
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Return Value:
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STATUS_SUCCESS if successful
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error status otherwise
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--*/
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{
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ULONGLONG MsrCapability;
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KIRQL OldIrql;
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KAFFINITY ActiveProcessors, CurrentAffinity;
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ULONGLONG MsrMceType;
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ULONG MCEEnabled;
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ULONG MCAEnabled;
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PULONG pTSS;
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//
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// This lock synchronises access to the log area when we call the
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// logger on multiple processors.
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//
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// Note: This must be initialized regardless of whether or not
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// this processor supports MCA.
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//
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ExInitializeFastMutex (&HalpMcaInfo.Mutex);
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//
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// If this processor does not support MCA, nothing more to do.
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//
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if ( (!(HalpFeatureBits & HAL_MCE_PRESENT)) &&
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(!(HalpFeatureBits & HAL_MCA_PRESENT)) ) {
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return; // nothing to do
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}
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HalpMcaGetConfiguration(&MCEEnabled, &MCAEnabled);
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if ( (HalpFeatureBits & HAL_MCE_PRESENT) &&
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(!(HalpFeatureBits & HAL_MCA_PRESENT)) ) {
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if (MCEEnabled == FALSE) {
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// User has not enabled MCE capability.
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HalpFeatureBits &= ~(HAL_MCE_PRESENT | HAL_MCA_PRESENT);
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return;
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}
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#if DBG
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DbgPrint("MCE feature is enabled via registry\n");
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#endif // DBG
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MsrMceType = RDMSR(PENTIUM_MC_TYPE);
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if (((PLARGE_INTEGER)(&MsrMceType))->LowPart & MCE_VALID) {
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//
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// On an AST PREMMIA MX machine we seem to have a Machine
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// Check Pending always.
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//
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HalDisplayString(MsgMCEPending);
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HalpFeatureBits &= ~(HAL_MCE_PRESENT | HAL_MCA_PRESENT);
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return;
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}
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}
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//
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// If MCA is available, find out the number of banks available and
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// also get the platform specific bank 0 configuration
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//
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if ( HalpFeatureBits & HAL_MCA_PRESENT ) {
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if (MCAEnabled == FALSE) {
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//
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// User has disabled MCA capability.
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//
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#if DBG
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DbgPrint("MCA feature is disabled via registry\n");
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#endif // DBG
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HalpFeatureBits &= ~(HAL_MCE_PRESENT | HAL_MCA_PRESENT);
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return;
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}
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MsrCapability = RDMSR(MCG_CAP);
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HalpMcaInfo.NumBanks = (UCHAR)(MsrCapability & MCA_CNT_MASK);
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//
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// Find out the Bank 0 configuration setup by BIOS. This will be used
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// as a mask when writing to Bank 0
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//
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HalpMcaInfo.Bank0Config = RDMSR(MC0_CTL);
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}
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ASSERT(HalpFeatureBits & HAL_MCE_PRESENT);
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//
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// Initialize on each processor
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//
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#if !defined(_AMD64_)
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ActiveProcessors = HalpActiveProcessors;
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for (CurrentAffinity = 1; ActiveProcessors; CurrentAffinity <<= 1) {
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if (ActiveProcessors & CurrentAffinity) {
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ActiveProcessors &= ~CurrentAffinity;
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KeSetSystemAffinityThread (CurrentAffinity);
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//
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// Initialize MCA support on this processor
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//
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//
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// Allocate memory for this processor's TSS and it's own
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// private stack
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//
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pTSS = (PULONG)ExAllocatePoolWithTag(NonPagedPool,
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MINIMUM_TSS_SIZE,
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HAL_POOL_TAG
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);
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if (!pTSS) {
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//
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// This allocation is critical.
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//
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KeBugCheckEx(HAL_MEMORY_ALLOCATION,
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MINIMUM_TSS_SIZE,
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2,
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(ULONG_PTR)__FILE__,
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__LINE__
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);
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}
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RtlZeroMemory(pTSS, MINIMUM_TSS_SIZE);
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OldIrql = KfRaiseIrql(HIGH_LEVEL);
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HalpMcaCurrentProcessorSetTSS(pTSS);
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HalpMcaCurrentProcessorSetConfig();
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KeLowerIrql(OldIrql);
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}
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}
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#endif // _AMD64_
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//
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// Restore threads affinity
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//
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KeRevertToUserAffinityThread();
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}
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VOID
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HalpMcaCurrentProcessorSetConfig (
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VOID
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)
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/*++
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Routine Description:
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This routine sets/modifies the configuration of the machine check
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architecture on the current processor. Input is specification of
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the control register MCi_CTL for each bank of the MCA architecture.
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which controls the generation of machine check exceptions for errors
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logged to that bank.
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If MCA is not available on this processor, check if MCE is available.
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If so, enable MCE in CR4
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Arguments:
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Context: Array of values of MCi_CTL for each bank of MCA.
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If NULL, use MCA_DEFAULT_BANK_CONF values for each bank
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Return Value:
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None
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--*/
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{
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ULONGLONG MciCtl;
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ULONGLONG McgCap;
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ULONGLONG McgCtl;
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ULONG BankNum;
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if (HalpFeatureBits & HAL_MCA_PRESENT) {
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//
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// MCA is available. Initialize MCG_CTL register if present
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// Writing all 1's enable MCE or MCA Error Exceptions
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//
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McgCap = RDMSR(MCG_CAP);
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if (McgCap & MCG_CTL_PRESENT) {
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McgCtl = MCA_MCGCTL_ENABLE_LOGGING;
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WRMSR(MCG_CTL, McgCtl);
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}
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//
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// Enable all MCA errors
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//
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for ( BankNum = 0; BankNum < HalpMcaInfo.NumBanks; BankNum++ ) {
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//
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// Use MCA_DEFAULT_BANK_CONF for each bank
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//
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MciCtl = MCA_DEFAULT_BANK_CONF;
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//
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// If this is bank 0, use HalpMcaInfo.Bank0Config as a mask
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//
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if (BankNum == 0) {
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MciCtl &= HalpMcaInfo.Bank0Config;
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}
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WRMSR(MC0_CTL + (BankNum * MCA_NUM_REGS), MciCtl);
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}
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}
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//
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// Enable MCE bit in CR4
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//
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#if defined(_AMD64_)
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{
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ULONG64 cr4;
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cr4 = ReadCR4();
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cr4 |= CR4_MCE;
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WriteCR4(cr4);
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}
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#else
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HalpSetCr4MCEBit();
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#endif
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}
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NTSTATUS
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HalpMcaRegisterDriver(
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IN PMCA_DRIVER_INFO DriverInfo
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)
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/*++
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Routine Description:
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This routine is called by the driver (via HalSetSystemInformation)
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to register its presence. Only one driver can be registered at a time.
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Arguments:
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DriverInfo: Contains info about the callback routine and the DriverObject
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Return Value:
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Unless a MCA driver is already registered OR one of the two callback
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routines are NULL, this routine returns Success.
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--*/
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{
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KIRQL OldIrql;
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PVOID UnlockHandle;
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NTSTATUS Status;
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PAGED_CODE();
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Status = STATUS_UNSUCCESSFUL;
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if ((HalpFeatureBits & HAL_MCE_PRESENT) && DriverInfo->DpcCallback) {
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HalpMcaLockInterface();
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//
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// Register driver
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//
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if (!HalpMcaInfo.DriverInfo.DpcCallback) {
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// Initialize the DPC object
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KeInitializeDpc(
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&HalpMcaInfo.Dpc,
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DriverInfo->DpcCallback,
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DriverInfo->DeviceContext
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);
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// register driver
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HalpMcaInfo.DriverInfo.ExceptionCallback = DriverInfo->ExceptionCallback;
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HalpMcaInfo.DriverInfo.DpcCallback = DriverInfo->DpcCallback;
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HalpMcaInfo.DriverInfo.DeviceContext = DriverInfo->DeviceContext;
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Status = STATUS_SUCCESS;
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}
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HalpMcaUnlockInterface();
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} else if (!DriverInfo->DpcCallback) {
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HalpMcaLockInterface();
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// Only deregistering myself is permitted
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if (HalpMcaInfo.DriverInfo.DeviceContext == DriverInfo->DeviceContext) {
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HalpMcaInfo.DriverInfo.ExceptionCallback = NULL;
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HalpMcaInfo.DriverInfo.DpcCallback = NULL;
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HalpMcaInfo.DriverInfo.DeviceContext = NULL;
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Status = STATUS_SUCCESS;
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}
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HalpMcaUnlockInterface();
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}
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return Status;
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}
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|
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#define MAX_MCA_NONFATAL_RETRIES 5
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#define MCA_NONFATAL_ERORRS_BEFORE_WBINVD 3
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|
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NTSTATUS
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HalpGetMcaLog (
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IN OUT PMCA_EXCEPTION Exception,
|
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IN ULONG BufferSize,
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OUT PULONG Length
|
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)
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|
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/*++
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Routine Description:
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This is the entry point for driver to read the bank logs
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Called by HaliQuerySystemInformation()
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Arguments:
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Exception: Buffer into which the error is reported
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BufferSize: Size of the passed buffer
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Length: of the result
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Return Value:
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Success or failure
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--*/
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|
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{
|
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KAFFINITY ActiveProcessors, CurrentAffinity;
|
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NTSTATUS Status;
|
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ULONG p1, p2;
|
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ULONGLONG p3;
|
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static ULONG McaStatusCount = 0;
|
|
static ULONG SavedBank = 0;
|
|
static ULONGLONG SavedMcaStatus = 0;
|
|
static KAFFINITY SavedAffinity = 0;
|
|
|
|
|
|
PAGED_CODE();
|
|
|
|
if (! (HalpFeatureBits & HAL_MCA_PRESENT)) {
|
|
return(STATUS_NO_SUCH_DEVICE);
|
|
}
|
|
|
|
switch (BufferSize) {
|
|
|
|
case MCA_EXCEPTION_V1_SIZE:
|
|
Exception->VersionNumber = 1;
|
|
break;
|
|
|
|
case MCA_EXCEPTION_V2_SIZE:
|
|
ASSERT(Exception->VersionNumber == 2);
|
|
break;
|
|
|
|
default:
|
|
return(STATUS_INVALID_PARAMETER);
|
|
}
|
|
|
|
|
|
ActiveProcessors = HalpActiveProcessors;
|
|
Status = STATUS_NOT_FOUND;
|
|
|
|
HalpMcaLockInterface();
|
|
|
|
*Length = 0;
|
|
for (CurrentAffinity = 1; ActiveProcessors; CurrentAffinity <<= 1) {
|
|
|
|
if (ActiveProcessors & CurrentAffinity) {
|
|
|
|
ActiveProcessors &= ~CurrentAffinity;
|
|
KeSetSystemAffinityThread (CurrentAffinity);
|
|
|
|
//
|
|
// Check this processor for an exception
|
|
//
|
|
|
|
Status = HalpMcaReadProcessorException (Exception, FALSE);
|
|
|
|
//
|
|
// Avoiding going into an infinite loop reporting a non-fatal
|
|
// single bit MCA error. This can be the result of the same
|
|
// error being generated repeatly by the hardware.
|
|
//
|
|
|
|
if (Status == STATUS_SUCCESS) {
|
|
|
|
//
|
|
// Check to see if the same processor is reporting the
|
|
// same MCA status.
|
|
//
|
|
|
|
if ((CurrentAffinity == SavedAffinity) &&
|
|
(SavedBank == Exception->u.Mca.BankNumber) &&
|
|
(SavedMcaStatus == Exception->u.Mca.Status.QuadPart)) {
|
|
|
|
//
|
|
// Check to see if the same error is generated more than
|
|
// n times. Currently n==5. If so, bugcheck the system.
|
|
//
|
|
|
|
if (McaStatusCount >= MAX_MCA_NONFATAL_RETRIES) {
|
|
|
|
if (Exception->VersionNumber == 1) {
|
|
|
|
//
|
|
// Parameters for bugcheck
|
|
//
|
|
|
|
p1 = ((PLARGE_INTEGER)(&Exception->u.Mce.Type))->LowPart;
|
|
p2 = 0;
|
|
p3 = Exception->u.Mce.Address;
|
|
|
|
} else {
|
|
|
|
//
|
|
// Parameters for bugcheck
|
|
//
|
|
|
|
p1 = Exception->u.Mca.BankNumber;
|
|
p2 = Exception->u.Mca.Address.Address;
|
|
p3 = Exception->u.Mca.Status.QuadPart;
|
|
}
|
|
|
|
//
|
|
// We need a new bugcheck code for this case.
|
|
//
|
|
|
|
KeBugCheckEx (
|
|
MACHINE_CHECK_EXCEPTION,
|
|
p1,
|
|
p2,
|
|
((PLARGE_INTEGER)(&p3))->HighPart,
|
|
((PLARGE_INTEGER)(&p3))->LowPart
|
|
);
|
|
|
|
} else {
|
|
|
|
//
|
|
// This error is seen more than 1 once. If it has
|
|
// occurred more than
|
|
// MCA_NONFATAL_ERORRS_BEFORE_WBINVD times, write
|
|
// back and Invalid cache to see if the error can be
|
|
// cleared.
|
|
//
|
|
|
|
McaStatusCount++;
|
|
if (McaStatusCount >=
|
|
MCA_NONFATAL_ERORRS_BEFORE_WBINVD) {
|
|
#if defined(_AMD64_)
|
|
WritebackInvalidate();
|
|
#else
|
|
_asm {
|
|
wbinvd
|
|
}
|
|
#endif
|
|
}
|
|
}
|
|
|
|
} else {
|
|
|
|
//
|
|
// First time we have seen this error, save the Status,
|
|
// affinity and clear the count.
|
|
//
|
|
|
|
SavedMcaStatus = Exception->u.Mca.Status.QuadPart;
|
|
SavedBank = Exception->u.Mca.BankNumber;
|
|
McaStatusCount = 0;
|
|
SavedAffinity = CurrentAffinity;
|
|
}
|
|
|
|
} else {
|
|
|
|
//
|
|
// Either we did not get an error or it will be fatal.
|
|
// If we did not get an error and we are doing the processor
|
|
// that reported the last error, clear things so we do not
|
|
// match previous errors. Since each time we look for an
|
|
// error we start over with the first processor we do not
|
|
// have to worry about multiple processor having stuck
|
|
// errors. We will only be able to see the first one.
|
|
//
|
|
|
|
if (SavedAffinity == CurrentAffinity) {
|
|
SavedMcaStatus = 0;
|
|
SavedBank = 0;
|
|
McaStatusCount = 0;
|
|
SavedAffinity = 0;
|
|
}
|
|
}
|
|
|
|
//
|
|
// If found, return current information
|
|
//
|
|
|
|
if (Status != STATUS_NOT_FOUND) {
|
|
ASSERT (Status != STATUS_SEVERITY_ERROR);
|
|
*Length = BufferSize;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
//
|
|
// Restore threads affinity, release mutex, and return
|
|
//
|
|
|
|
KeRevertToUserAffinityThread();
|
|
HalpMcaUnlockInterface();
|
|
return Status;
|
|
}
|
|
|
|
|
|
// Set the following to check async capability
|
|
|
|
BOOLEAN NoMCABugCheck = FALSE;
|
|
|
|
VOID
|
|
HalpMcaExceptionHandler (
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
Routine Description:
|
|
This is the MCA exception handler.
|
|
|
|
Arguments:
|
|
None
|
|
|
|
Return Value:
|
|
None
|
|
--*/
|
|
|
|
{
|
|
NTSTATUS Status;
|
|
MCA_EXCEPTION BankLog;
|
|
ULONG p1;
|
|
ULONGLONG McgStatus, p3;
|
|
|
|
if (!(HalpFeatureBits & HAL_MCA_PRESENT) ) {
|
|
|
|
//
|
|
// If we have ONLY MCE (and not MCA), read the MC_ADDR and MC_TYPE
|
|
// MSRs, print the values and bugcheck as the errors are not
|
|
// restartable.
|
|
//
|
|
|
|
BankLog.VersionNumber = 1;
|
|
BankLog.ExceptionType = HAL_MCE_RECORD;
|
|
BankLog.u.Mce.Address = RDMSR(PENTIUM_MC_ADDR);
|
|
BankLog.u.Mce.Type = RDMSR(PENTIUM_MC_TYPE);
|
|
Status = STATUS_SEVERITY_ERROR;
|
|
|
|
//
|
|
// Parameters for bugcheck
|
|
//
|
|
|
|
p1 = ((PLARGE_INTEGER)(&BankLog.u.Mce.Type))->LowPart;
|
|
p3 = BankLog.u.Mce.Address;
|
|
|
|
} else {
|
|
|
|
McgStatus = RDMSR(MCG_STATUS);
|
|
ASSERT( (McgStatus & MCG_MC_INPROGRESS) != 0);
|
|
|
|
BankLog.VersionNumber = 2;
|
|
Status = HalpMcaReadProcessorException (&BankLog, TRUE);
|
|
|
|
//
|
|
// Clear MCIP bit in MCG_STATUS register
|
|
//
|
|
|
|
McgStatus = 0;
|
|
WRMSR(MCG_STATUS, McgStatus);
|
|
|
|
//
|
|
// Parameters for bugcheck
|
|
//
|
|
|
|
p1 = BankLog.u.Mca.BankNumber;
|
|
p3 = BankLog.u.Mca.Status.QuadPart;
|
|
}
|
|
|
|
if (Status == STATUS_SEVERITY_ERROR) {
|
|
|
|
//
|
|
// Call the exception callback of the driver so that
|
|
// the error can be logged to NVRAM
|
|
//
|
|
|
|
if (HalpMcaInfo.DriverInfo.ExceptionCallback) {
|
|
HalpMcaInfo.DriverInfo.ExceptionCallback (
|
|
HalpMcaInfo.DriverInfo.DeviceContext,
|
|
&BankLog
|
|
);
|
|
}
|
|
|
|
if (!NoMCABugCheck) {
|
|
|
|
//
|
|
// Bugcheck
|
|
//
|
|
|
|
KeBugCheckEx(
|
|
MACHINE_CHECK_EXCEPTION,
|
|
p1,
|
|
(ULONG_PTR) &BankLog,
|
|
((PLARGE_INTEGER)(&p3))->HighPart,
|
|
((PLARGE_INTEGER)(&p3))->LowPart
|
|
);
|
|
|
|
// NOT REACHED
|
|
}
|
|
}
|
|
|
|
//
|
|
// Must be restartable. Indicate to the timer tick routine that a
|
|
// DPC needs queued for MCA driver.
|
|
//
|
|
|
|
if (HalpMcaInfo.DriverInfo.DpcCallback) {
|
|
HalpClockMcaQueueDpc = 1;
|
|
}
|
|
}
|
|
|
|
VOID
|
|
HalpMcaQueueDpc(
|
|
VOID
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Gets called from the timer tick to check if DPC
|
|
needs to be queued
|
|
|
|
--*/
|
|
|
|
{
|
|
KeInsertQueueDpc(
|
|
&HalpMcaInfo.Dpc,
|
|
NULL,
|
|
NULL
|
|
);
|
|
}
|
|
|
|
|
|
NTSTATUS
|
|
HalpMcaReadRegisterInterface(
|
|
IN UCHAR BankNumber,
|
|
IN OUT PMCA_EXCEPTION Exception
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine reads the given MCA register number from the
|
|
current processor and returns the result in the Exception
|
|
structure.
|
|
|
|
Arguments:
|
|
|
|
BankNumber Number of MCA Bank to be examined.
|
|
Exception Buffer into which the error is reported
|
|
|
|
Return Value:
|
|
|
|
STATUS_SUCCESS if an error was found and the data copied into
|
|
the excption buffer.
|
|
STATUS_UNSUCCESSFUL if the register contains no error information.
|
|
STATUS_NOT_FOUND if the register number exceeds the maximum number
|
|
of registers.
|
|
STATUS_INVALID_PARAMETER if the Exception record is of an unknown type.
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONGLONG McgStatus;
|
|
MCI_STATS istatus;
|
|
NTSTATUS ReturnStatus;
|
|
MCG_CAPABILITY cap;
|
|
ULONG Reg;
|
|
|
|
//
|
|
// Are they asking for a valid register?
|
|
//
|
|
|
|
if (BankNumber >= HalpMcaInfo.NumBanks) {
|
|
return STATUS_NOT_FOUND;
|
|
}
|
|
|
|
//
|
|
// The exception buffer should tell us if it's version 1 or
|
|
// 2. Anything else we don't know how to deal with.
|
|
//
|
|
|
|
if ((Exception->VersionNumber < 1) ||
|
|
(Exception->VersionNumber > 2)) {
|
|
return STATUS_INVALID_PARAMETER;
|
|
}
|
|
|
|
//
|
|
// Read the global status register
|
|
//
|
|
|
|
McgStatus = RDMSR(MCG_STATUS);
|
|
|
|
//
|
|
// Read the Status MSR of the requested bank
|
|
//
|
|
|
|
istatus.QuadPart = RDMSR(MC0_STATUS + BankNumber * MCA_NUM_REGS);
|
|
|
|
|
|
if (istatus.MciStats.Valid == 0) {
|
|
|
|
//
|
|
// No error in this bank.
|
|
//
|
|
|
|
return STATUS_UNSUCCESSFUL;
|
|
}
|
|
|
|
//
|
|
// When MCIP bit is set, the execution can be restarted when
|
|
// (MCi_STATUS.DAM == 0) && (MCG_STATUS.RIPV == 1)
|
|
//
|
|
// Note: STATUS_SEVERITY_ERROR is not a valid status choice.
|
|
//
|
|
|
|
ReturnStatus = STATUS_SUCCESS;
|
|
|
|
if ((McgStatus & MCG_MC_INPROGRESS) &&
|
|
(!(McgStatus & MCG_RESTART_EIP_VALID) ||
|
|
istatus.MciStats.Damage)) {
|
|
|
|
ReturnStatus = STATUS_SEVERITY_ERROR;
|
|
}
|
|
|
|
//
|
|
// Complete extended exception record, if requested.
|
|
//
|
|
|
|
if (Exception->VersionNumber == 2) {
|
|
cap.u.QuadPart = RDMSR(MCG_CAP);
|
|
if (cap.u.hw.McaExtCnt > 0) {
|
|
// Get Version 2 stuff from MSRs.
|
|
Exception->ExtCnt = cap.u.hw.McaExtCnt;
|
|
if (Exception->ExtCnt > MCA_EXTREG_V2MAX) {
|
|
Exception->ExtCnt = MCA_EXTREG_V2MAX;
|
|
}
|
|
for (Reg = 0; Reg < Exception->ExtCnt; Reg++) {
|
|
Exception->ExtReg[Reg] = RDMSR(MCG_EAX+Reg);
|
|
}
|
|
if (cap.u.hw.McaExtCnt >= MCG_EFLAGS_OFFSET) {
|
|
if (RDMSR(MCG_EFLAGS) == 0) {
|
|
// Let user know he got only Version 1 data.
|
|
Exception->VersionNumber = 1;
|
|
}
|
|
}
|
|
} else {
|
|
// Let user know he got only Version 1 data.
|
|
Exception->VersionNumber = 1;
|
|
}
|
|
}
|
|
|
|
//
|
|
// Complete exception record
|
|
//
|
|
|
|
Exception->ExceptionType = HAL_MCA_RECORD;
|
|
Exception->TimeStamp.QuadPart = 0;
|
|
Exception->u.Mca.Address.QuadPart = 0;
|
|
Exception->u.Mca.Misc = 0;
|
|
Exception->u.Mca.BankNumber = BankNumber;
|
|
Exception->u.Mca.Status = istatus;
|
|
|
|
Exception->ProcessorNumber = KeGetCurrentProcessorNumber();
|
|
|
|
#if defined(_AMD64_)
|
|
if (KeGetCurrentIrql() != CLOCK_LEVEL) {
|
|
#else
|
|
if (KeGetCurrentIrql() != CLOCK2_LEVEL) {
|
|
#endif
|
|
KeQuerySystemTime(&Exception->TimeStamp);
|
|
}
|
|
|
|
if (istatus.MciStats.AddressValid) {
|
|
Exception->u.Mca.Address.QuadPart =
|
|
RDMSR(MC0_ADDR + BankNumber * MCA_NUM_REGS);
|
|
}
|
|
|
|
//
|
|
// Although MiscValid should never be set on P6 it
|
|
// seems that sometimes it is. It is not implemented
|
|
// on P6 and above so don't read it there.
|
|
//
|
|
|
|
if (istatus.MciStats.MiscValid &&
|
|
(KeGetCurrentPrcb()->CpuType != 6)) {
|
|
Exception->u.Mca.Misc =
|
|
RDMSR(MC0_MISC + BankNumber * MCA_NUM_REGS);
|
|
}
|
|
|
|
//
|
|
// Clear Machine Check in MCi_STATUS register
|
|
//
|
|
|
|
WRMSR(MC0_STATUS + Exception->u.Mca.BankNumber * MCA_NUM_REGS, 0);
|
|
|
|
//
|
|
// Clear Register state in MCG_EFLAGS
|
|
//
|
|
|
|
if (Exception->VersionNumber != 1) {
|
|
WRMSR(MCG_EFLAGS, 0);
|
|
}
|
|
|
|
//
|
|
// When the Valid bit of status register is cleared, hardware may write
|
|
// a new buffered error report into the error reporting area. The
|
|
// serializing instruction is required to permit the update to complete
|
|
//
|
|
|
|
HalpSerialize();
|
|
return(ReturnStatus);
|
|
}
|
|
|
|
|
|
NTSTATUS
|
|
HalpMcaReadProcessorException (
|
|
IN OUT PMCA_EXCEPTION Exception,
|
|
IN BOOLEAN NonRestartableOnly
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine logs the errors from the MCA banks on one processor.
|
|
Necessary checks for the restartability are performed. The routine
|
|
1> Checks for restartability, and for each bank identifies valid bank
|
|
entries and logs error.
|
|
2> If the error is not restartable provides additional information about
|
|
bank and the MCA registers.
|
|
3> Resets the Status registers for each bank
|
|
|
|
Arguments:
|
|
Exception: Into which we log the error if found
|
|
NonRestartableOnly: Get any error vs. look for error that is not-restartable
|
|
|
|
Return Values:
|
|
STATUS_SEVERITY_ERROR: Detected non-restartable error.
|
|
STATUS_SUCCESS: Successfully logged bank values
|
|
STATUS_NOT_FOUND: No error found on any bank
|
|
|
|
--*/
|
|
|
|
{
|
|
UCHAR BankNumber;
|
|
NTSTATUS ReturnStatus = STATUS_NOT_FOUND;
|
|
|
|
//
|
|
// scan banks on current processor and log contents of first valid bank
|
|
// reporting error. Once we find a valid error, no need to read remaining
|
|
// banks. It is the application responsibility to read more errors.
|
|
//
|
|
|
|
for (BankNumber = 0; BankNumber < HalpMcaInfo.NumBanks; BankNumber++) {
|
|
|
|
ReturnStatus = HalpMcaReadRegisterInterface(BankNumber, Exception);
|
|
|
|
if ((ReturnStatus == STATUS_UNSUCCESSFUL) ||
|
|
((ReturnStatus == STATUS_SUCCESS) &&
|
|
(NonRestartableOnly == TRUE))) {
|
|
|
|
//
|
|
// No error in this bank or only looking for non-restartable
|
|
// errors, skip this one.
|
|
//
|
|
|
|
ReturnStatus = STATUS_NOT_FOUND;
|
|
continue;
|
|
}
|
|
|
|
//
|
|
// We either found an uncorrected error OR found a corrected error
|
|
// and we were asked for either corrected or uncorrected error
|
|
// Return this error.
|
|
//
|
|
|
|
ASSERT((ReturnStatus == STATUS_SUCCESS) ||
|
|
(ReturnStatus == STATUS_SEVERITY_ERROR));
|
|
break;
|
|
}
|
|
|
|
return(ReturnStatus);
|
|
}
|
|
|
|
|
|
VOID
|
|
HalpMcaGetConfiguration (
|
|
OUT PULONG MCEEnabled,
|
|
OUT PULONG MCAEnabled
|
|
)
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
This routine stores the Machine Check configuration information.
|
|
|
|
Arguments:
|
|
|
|
MCEEnabled - Pointer to the MCEEnabled indicator.
|
|
0 = False, 1 = True (0 if value not present in Registry).
|
|
|
|
MCAEnabled - Pointer to the MCAEnabled indicator.
|
|
0 = False, 1 = True (1 if value not present in Registry).
|
|
|
|
Return Value:
|
|
|
|
None.
|
|
|
|
--*/
|
|
|
|
{
|
|
|
|
RTL_QUERY_REGISTRY_TABLE Parameters[3];
|
|
ULONG DefaultDataMCE;
|
|
ULONG DefaultDataMCA;
|
|
|
|
|
|
RtlZeroMemory(Parameters, sizeof(Parameters));
|
|
DefaultDataMCE = *MCEEnabled = FALSE;
|
|
DefaultDataMCA = *MCAEnabled = TRUE;
|
|
|
|
//
|
|
// Gather all of the "user specified" information from
|
|
// the registry.
|
|
//
|
|
|
|
Parameters[0].Flags = RTL_QUERY_REGISTRY_DIRECT;
|
|
Parameters[0].Name = rgzEnableMCE;
|
|
Parameters[0].EntryContext = MCEEnabled;
|
|
Parameters[0].DefaultType = REG_DWORD;
|
|
Parameters[0].DefaultData = &DefaultDataMCE;
|
|
Parameters[0].DefaultLength = sizeof(ULONG);
|
|
|
|
Parameters[1].Flags = RTL_QUERY_REGISTRY_DIRECT;
|
|
Parameters[1].Name = rgzEnableMCA;
|
|
Parameters[1].EntryContext = MCAEnabled;
|
|
Parameters[1].DefaultType = REG_DWORD;
|
|
Parameters[1].DefaultData = &DefaultDataMCA;
|
|
Parameters[1].DefaultLength = sizeof(ULONG);
|
|
|
|
RtlQueryRegistryValues(
|
|
RTL_REGISTRY_CONTROL | RTL_REGISTRY_OPTIONAL,
|
|
rgzSessionManager,
|
|
Parameters,
|
|
NULL,
|
|
NULL
|
|
);
|
|
}
|
|
|
|
VOID
|
|
HalHandleMcheck (
|
|
IN PKTRAP_FRAME TrapFrame,
|
|
IN PKEXCEPTION_FRAME ExceptionFrame
|
|
)
|
|
{
|
|
HalpMcaExceptionHandler();
|
|
}
|
|
|