459 lines
12 KiB
NASM
459 lines
12 KiB
NASM
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title "Sleep Context"
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;++
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;
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; Copyright (c) 1989 Microsoft Corporation
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;
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; Module Name:
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;
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; ixslpctx.asm
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;
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; Abstract:
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;
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; This module implements the code for saving processor
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; context before putting the machine to sleep. It also
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; contains the code for building a page that a processor
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; in real mode can jump to in order to transition into
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; p-mode and assume a thread context.
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;
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; Author:
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;
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; Jake Oshins (jakeo) March 13, 1998
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;
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; Environment:
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;
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; Kernel mode only.
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;
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; Revision History:
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;
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; Much of this code has been moved from halmps\i386\mpsproca.asm.
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;
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;--
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.386p
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.xlist
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include hal386.inc
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include callconv.inc ; calling convention macros
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include apic.inc
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include i386\ixslpctx.inc
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include mac386.inc
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.list
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extrn _HalpLowStub:DWORD
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extrn _KeSaveStateForHibernate:proc
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ifdef ACPI_HAL
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EXTRNP HalpAcpiFlushCache, 0,,FASTCALL
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endif
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PAGELK16 SEGMENT DWORD PUBLIC USE16 'CODE' ; start 16 bit code
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;++
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;
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; VOID
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; _StartPx_RMStub
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;
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; Routine Description:
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;
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; When a new processor is started, it starts in real-mode and is
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; sent to a copy of this function which has been copied into low memory.
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; (below 1m and accessable from real-mode).
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;
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; Once CR0 has been set, this function jmp's to a StartPx_PMStub
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;
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; Arguments:
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; none
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;
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; Return Value:
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; does not return, jumps to StartPx_PMStub
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;
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;--
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cPublicProc _StartPx_RMStub ,0
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cli
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db 066h ; load the GDT
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lgdt fword ptr cs:[SPx_PB.PsSpecialRegisters.SrGdtr]
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db 066h ; load the IDT
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lidt fword ptr cs:[SPx_PB.PsSpecialRegisters.SrIdtr]
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mov eax, cs:[SPx_TiledCR3]
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nop ; Fill - Ensure 13 non-page split
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nop ; accesses before CR3 load
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nop ; (P6 errata #11 stepping B0)
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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mov cr3, eax
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;
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; Restore CR4 to enable Page Size Extensions
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; before we got real CR3 which might use Large Page.
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; If SrCr4 is non-zero, then CR4 exists
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;
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mov eax, dword ptr cs:[SPx_PB.PsSpecialRegisters.SrCr4]
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or eax, eax
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jz @f
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.586p
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mov cr4, eax
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.386p
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@@:
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mov ebp, dword ptr cs:[SPx_P0EBP]
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mov ecx, dword ptr cs:[SPx_PB.PsContextFrame.CsSegDs]
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mov ebx, dword ptr cs:[SPx_PB.PsSpecialRegisters.SrCr3]
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mov eax, dword ptr cs:[SPx_PB.PsSpecialRegisters.SrCr0]
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mov edi, dword ptr cs:[SPx_flat_addr]
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mov cr0, eax ; into prot mode
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db 066h
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db 0eah ; reload cs:eip
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SPrxPMStub dd 0
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SPrxFlatCS dw 0
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_StartPx_RMStub_Len equ $ - _StartPx_RMStub
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stdENDP _StartPx_RMStub
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PAGELK16 ends ; End 16 bit code
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PAGELK SEGMENT PARA PUBLIC 'CODE' ; Start 32 bit code
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ASSUME DS:FLAT, ES:FLAT, SS:NOTHING, FS:NOTHING, GS:NOTHING
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;++
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;
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; VOID
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; StartPx_PMStub
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;
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; Routine Description:
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;
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; This function completes the processor's state loading, and signals
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; the requesting processor that the state has been loaded.
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;
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; Arguments:
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; ebx - requested CR3 for this processors_state
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; cx - requested ds for this processors_state
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; ebp - EBP of P0
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; edi - p-mode address of startup block
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;
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; Return Value:
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; does not return - completes the loading of the processors_state
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;
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;--
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align dword ; to make sure we don't cross a page boundry
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; before reloading CR3
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cPublicProc _StartPx_PMStub ,0
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; process is now in the load image copy of this function.
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; (ie, it's not the low memory copy)
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mov cr3, ebx ; get real CR3
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mov ds, cx ; set real ds
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lea esi, [edi].SPx_PB.PsSpecialRegisters
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lldt word ptr ds:[esi].SrLdtr ; load ldtr
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;
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; Force the TSS descriptor into a non-busy state, so we don't fault
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; when we load the TR.
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;
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mov eax, ds:[esi].SrGdtr+2 ; (eax)->GDT base
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xor ecx, ecx
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mov cx, word ptr ds:[esi].SrTr
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add eax, 5
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add eax, ecx ; (eax)->TSS Desc. Byte
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and byte ptr [eax],NOT 2
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ltr word ptr ds:[esi].SrTr ; load tss
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lea edx, [edi].SPx_PB.PsContextFrame
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mov es, word ptr ds:[edx].CsSegEs ; Set other selectors
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mov fs, word ptr ds:[edx].CsSegFs
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mov gs, word ptr ds:[edx].CsSegGs
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mov ss, word ptr ds:[edx].CsSegSs
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cld ; make lodsd ascending (below)
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xor eax, eax ; disable debug registers while
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mov dr7, eax ; setting them.
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add esi, SrKernelDr0
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.errnz (SrKernelDr1 - SrKernelDr0 - 1 * 4)
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.errnz (SrKernelDr2 - SrKernelDr0 - 2 * 4)
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.errnz (SrKernelDr3 - SrKernelDr0 - 3 * 4)
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.errnz (SrKernelDr6 - SrKernelDr0 - 4 * 4)
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.errnz (SrKernelDr7 - SrKernelDr0 - 5 * 4)
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lodsd
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mov dr0, eax ; load dr0-dr7
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lodsd
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mov dr1, eax
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lodsd
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mov dr2, eax
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lodsd
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mov dr3, eax
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lodsd
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mov dr6, eax
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lodsd
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mov dr7, eax
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mov esp, dword ptr ds:[edx].CsEsp
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mov ecx, dword ptr ds:[edx].CsEcx
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push dword ptr ds:[edx].CsEflags
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popfd ; load eflags
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push dword ptr ds:[edx].CsEip ; make a copy of remaining
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push dword ptr ds:[edx].CsEax ; registers which need
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push dword ptr ds:[edx].CsEbx ; loaded
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push dword ptr ds:[edx].CsEdx
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push dword ptr ds:[edx].CsEsi
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push dword ptr ds:[edx].CsEdi
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push dword ptr ds:[edx].CsEbp
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inc [edi.SPx_flag] ; Signal p0 that we are
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; done with it's data
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; Set remaining registers
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pop ebp
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pop edi
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pop esi
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pop edx
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pop ebx
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pop eax
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stdRET _StartPx_PMStub
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stdENDP _StartPx_PMStub
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;++
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;
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; VOID
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; StartPx_BuildRealModeStart(
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; IN PUCHAR ParamBlock
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; )
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;
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; Routine Description:
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;
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; This function sets up the real mode startup page
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;
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; Arguments:
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;
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; PxParamBlock -- address of the structure that should end up
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; at the beginning of HalpLowStub
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;
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;--
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ParamBlockAddress equ [ebp + 8]
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cPublicProc _StartPx_BuildRealModeStart ,1
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push ebp
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mov ebp, esp
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push ebx
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push esi
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push edi
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mov edx, ParamBlockAddress
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;
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; Build a jmp to the start of the Real mode startup code
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;
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; This is needed because the Local APIC implementations
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; use a Startup IPI that must be Page aligned. The allocation
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; code int MP_INIT ensures that this is page aligned. The
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; original code was written to place the parameter block first.
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; By adding a jump instruction to the start of the parameter block
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; we can run either way.
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;
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mov eax, size PxParamBlock - 3 ; Jump destination relative to
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; next instruction
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shl eax, 8 ; Need room for jmp instruction
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mov al,0e9h
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mov [edx].SPx_Jmp_Inst, eax
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;
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; Save the p-mode address of PxParamBlock
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;
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mov eax, _HalpLowStub
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mov [edx].SPx_flat_addr, eax
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;
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; Copy RMStub to low memory
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;
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mov esi, OFFSET FLAT:_StartPx_RMStub
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mov ecx, _StartPx_RMStub_Len
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mov edi, _HalpLowStub ; Destination was allocated by MpInit
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add edi, size PxParamBlock ; Parameter Block is placed first
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rep movsb
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;
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; Copy the parameter block to low memory
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;
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mov ecx, size PxParamBlock ; Structure length
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mov esi, ParamBlockAddress ; Parameter Block is placed first
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mov edi, _HalpLowStub ; Destination Address
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rep movsb
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;
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; Now we need to create a pointer allowing the Real Mode code to
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; Branch to the Protected mode code
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;
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mov eax, _HalpLowStub ; low memory Address
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add eax, size PxParamBlock ; Move past the Parameter block
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;
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; In order to get to the label we need to compute the label offset relative
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; to the start of the routine and then use this as a offset from the start of
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; the routine ( HalpLowStub + (size PxParamBlock)) in low memory.
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;
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; The following code creates a pointer to (RMStub - StartPx_RMStub)
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; which can then be used to access code locations via code labels directly.
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; Since the [eax.Label] results in the address (eax + Label) loading eax
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; with the pointer created above results in (RMStub - StartPx_RMStub + Label).
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;
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mov ebx, OFFSET FLAT:_StartPx_RMStub
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sub eax, ebx ; (eax) = adjusted pointer
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;
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; Patch the real mode code with a valid long jump address, first CS then offset
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;
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mov bx, word ptr [edx].SPx_PB.PsContextFrame.CsSegCs
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mov [eax.SPrxFlatCS], bx
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mov [eax.SPrxPMStub], offset _StartPx_PMStub
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pop edi
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pop esi
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pop ebx
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pop ebp
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stdRET _StartPx_BuildRealModeStart
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stdENDP _StartPx_BuildRealModeStart
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subttl "Save Processor State"
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;++
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;
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; VOID
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; HalpSaveProcessorStateAndWait(
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; IN PKPROCESSOR_STATE ProcessorState
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; )
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;
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; Routine Description:
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;
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; This function saves the volatile, non-volatile and special register
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; state of the current processor.
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;
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; N.B. Floating point state is NOT captured.
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;
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; Arguments:
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;
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; ProcessorState (esp+4) - Address of processor state record to fill in.
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;
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; pBarrier - Address of a value to use as a lock.
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;
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; Return Value:
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;
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; None. This function does not return.
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;
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;--
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ProcessorState equ [esp + 8]
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pBarrier equ dword ptr [esp + 12]
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cPublicProc _HalpSaveProcessorStateAndWait,2
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push ebx
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mov ebx, ProcessorState
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cmp ebx, 0 ; if this isn't filled in, don't save context
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jz hspsaw_statesaved
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;
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; Fill in ProcessorState
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;
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push ebx
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call _KeSaveStateForHibernate ; _cdecl function
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add esp, 4
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;; Save return address, not caller's return address
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mov eax,[esp+4]
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mov [ebx.PsContextFrame.CsEip],eax
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;; Save caller's ebp, not caller's return ebp.
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mov [ebx.PsContextFrame.CsEbp],ebp
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;; Set ESP to value just before this function call
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lea eax,[esp+16]
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mov [ebx.PsContextFrame.CsEsp],eax
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hspsaw_statesaved:
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ifdef ACPI_HAL
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;
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; Flush the cache, as the processor may be about
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; to power off.
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;
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fstCall HalpAcpiFlushCache
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endif
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;
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; Signal that this processor has saved its state
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;
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mov ebx, pBarrier
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lock inc dword ptr [ebx]
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;
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; Wait for the hibernation file to be written.
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; Processor 0 will zero Barrier when it is
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; finished.
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;
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; N.B. We can't return from this function
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; before the hibernation file is finished
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; because we would be tearing down the very same
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; stack that we will be jumping onto when the
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; processor resumes. But after the hibernation
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; file is written, it doesn't matter, because
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; the stack will be restored from disk.
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;
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hspsaw_spin:
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YIELD
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cmp dword ptr [ebx], 0
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jne hspsaw_spin
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;
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; Invalidate the processor cache so that any stray gamma
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; rays (I'm serious) that may have flipped cache bits
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; while in S1 will be ignored.
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;
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; Honestly. Intel asked for this. I'm serious.
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;
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;.586
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; invd
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;.386
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pop ebx
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stdRET _HalpSaveProcessorStateAndWait
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stdENDP _HalpSaveProcessorStateAndWait
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PAGELK ends ; end 32 bit code
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end
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