558 lines
15 KiB
C
558 lines
15 KiB
C
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/*
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* SoftPC Revision 2.0
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*
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* Title : Definitions for the CPU
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*
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* Description : Structures, macros and definitions for access to the
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* CPU registers
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*
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* Author : Henry Nash
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*
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* Notes : This file should be portable - but includes a file
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* host_cpu.h which contains machine specific definitions
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* of CPU register mappings etc.
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*/
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/* SccsID[]="@(#)cpu2.h 1.3 12/22/93 Copyright Insignia Solutions Ltd."; */
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#include "host_cpu.h"
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IMPORT VOID host_set_hw_int IPT0();
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IMPORT VOID host_clear_hw_int IPT0();
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/*
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* CPU Data Area
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* These externs are given before host_cpu.h is included so that the
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* variables may be gathreed into a structure and the externs overridden
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* by #defines in host_cpu.h
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*/
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extern word protected_mode; /* =0 no proteced mode warning given
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=1 proteced mode warning given */
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extern word cpu_interrupt_map;
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extern half_word cpu_int_translate[];
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extern word cpu_int_delay;
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extern half_word ica_lock;
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extern void (*(jump_ptrs[]))();
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extern void (*(b_write_ptrs[]))();
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extern void (*(w_write_ptrs[]))();
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extern void (*(b_fill_ptrs[]))();
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extern void (*(w_fill_ptrs[]))();
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#ifdef EGATEST
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extern void (*(b_fwd_move_ptrs[]))();
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extern void (*(w_fwd_move_ptrs[]))();
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extern void (*(b_bwd_move_ptrs[]))();
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extern void (*(w_bwd_move_ptrs[]))();
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#else
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extern void (*(b_move_ptrs[]))();
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extern void (*(w_move_ptrs[]))();
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#endif /* EGATEST */
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extern half_word *haddr_of_src_string;
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/*
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* ============================================================================
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* Structure/Data definitions
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* ============================================================================
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*/
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/*
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* The cpu opcode sliding frame
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*/
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#ifdef BACK_M
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typedef struct
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{
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half_word FOURTH_BYTE;
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half_word THIRD_BYTE;
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half_word SECOND_BYTE;
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half_word OPCODE;
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} OPCODE_FRAME;
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typedef struct
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{
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signed_char FOURTH_BYTE;
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signed_char THIRD_BYTE;
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signed_char SECOND_BYTE;
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signed_char OPCODE;
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} SIGNED_OPCODE_FRAME;
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#else
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typedef struct
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{
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half_word OPCODE;
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half_word SECOND_BYTE;
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half_word THIRD_BYTE;
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half_word FOURTH_BYTE;
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} OPCODE_FRAME;
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typedef struct
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{
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signed_char OPCODE;
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signed_char SECOND_BYTE;
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signed_char THIRD_BYTE;
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signed_char FOURTH_BYTE;
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} SIGNED_OPCODE_FRAME;
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#endif /* BACK_M */
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/*
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* The new ICA uses the following for H/W ints:
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*/
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#define CPU_HW_INT 0
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#define CPU_HW_INT_MASK (1 << CPU_HW_INT)
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/*
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* CPU software interrupt definitions
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*/
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#define CPU_SW_INT 8
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#define CPU_SW_INT_MASK (1 << CPU_SW_INT)
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/*
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* ============================================================================
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* External declarations and macros
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* ============================================================================
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*/
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extern OPCODE_FRAME *opcode_frame; /* C CPU and dasm only */
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/*
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* External declarations for the 80286 registers
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*/
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extern reg A; /* Accumulator */
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extern reg B; /* Base */
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extern reg C; /* Count */
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extern reg D; /* Data */
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extern reg SP; /* Stack Pointer */
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extern reg BP; /* Base pointer */
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extern reg SI; /* Source Index */
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extern reg DI; /* Destination Index */
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extern reg IP; /* Instruction Pointer */
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extern reg CS; /* Code Segment */
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extern reg DS; /* Data Segment */
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extern reg SS; /* Stack Segment */
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extern reg ES; /* Extra Segment */
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/*
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* External function declarations. These may be defined to other things.
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*/
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#ifndef host_simulate
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extern void host_simulate IPT0();
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#endif /* host_simulate */
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#ifndef host_cpu_reset
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extern void host_cpu_reset IPT0();
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#endif /* host_cpu_reset */
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#ifndef host_cpu_init
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extern void host_cpu_init IPT0();
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#endif /* host_cpu_init */
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#ifndef host_cpu_interrupt
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extern void host_cpu_interrupt IPT0();
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#endif /* host_cpu_interrupt */
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/*
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* Definition of Descriptor Table
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*/
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#ifdef BIGEND
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union sixteenbits
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{
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word X;
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struct
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{
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half_word lower;
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half_word upper;
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} word;
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};
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#endif /* BIGEND */
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#ifdef LITTLEND
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union sixteenbits
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{
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word X;
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struct
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{
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half_word upper;
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half_word lower;
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} word;
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};
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#endif /* LITTLEND */
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struct DESC_TABLE
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{
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union sixteenbits misc;
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union sixteenbits base;
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union sixteenbits limit;
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};
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#define CPU_SIGALRM_EXCEPTION 15 /* SIGALRM signal
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*/
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#define CPU_SIGALRM_EXCEPTION_MASK (1 << CPU_SIGALRM_EXCEPTION)
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#define CPU_TRAP_EXCEPTION 11 /* TRAP FLAG
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*/
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#define CPU_TRAP_EXCEPTION_MASK (1 << CPU_TRAP_EXCEPTION)
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#define CPU_YODA_EXCEPTION 13 /* YODA FLAG
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*/
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#define CPU_YODA_EXCEPTION_MASK (1 << CPU_YODA_EXCEPTION)
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#define CPU_SIGIO_EXCEPTION 14 /* SIGIO FLAG
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*/
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#define CPU_SIGIO_EXCEPTION_MASK (1 << CPU_SIGIO_EXCEPTION)
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#define CPU_RESET_EXCEPTION 12 /* RESET FLAG
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*/
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#define CPU_RESET_EXCEPTION_MASK (1 << CPU_RESET_EXCEPTION)
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#ifdef CCPU
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IMPORT void sw_host_simulate IPT0();
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IMPORT int selector_outside_table IPT2(word, selector, sys_addr *, descr_addr);
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IMPORT void cpu_init IPT0();
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/*
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Define descriptor 'super' types.
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*/
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#define INVALID 0x00
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#define AVAILABLE_TSS 0x01
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#define LDT_SEGMENT 0x02
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#define BUSY_TSS 0x03
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#define CALL_GATE 0x04
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#define TASK_GATE 0x05
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#define INTERRUPT_GATE 0x06
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#define TRAP_GATE 0x07
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#define EXPANDUP_READONLY_DATA 0x11
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#define EXPANDUP_WRITEABLE_DATA 0x13
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#define EXPANDDOWN_READONLY_DATA 0x15
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#define EXPANDDOWN_WRITEABLE_DATA 0x17
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#define NONCONFORM_NOREAD_CODE 0x19
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#define NONCONFORM_READABLE_CODE 0x1b
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#define CONFORM_NOREAD_CODE 0x1d
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#define CONFORM_READABLE_CODE 0x1f
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/* Code Segment (Private) */
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extern half_word CS_AR;
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extern sys_addr CS_base;
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extern word CS_limit;
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/* Data Segment (Private) */
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extern half_word DS_AR;
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extern sys_addr DS_base;
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extern word DS_limit;
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/* Stack Segment (Private) */
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extern half_word SS_AR;
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extern sys_addr SS_base;
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extern word SS_limit;
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/* Extra Segment (Private) */
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extern half_word ES_AR;
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extern sys_addr ES_base;
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extern word ES_limit;
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/* Local Descriptor Table Register (Private) */
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extern sys_addr LDTR_base; /* Base Address */
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extern word LDTR_limit; /* Segment 'size' */
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/* Task Register (Private) */
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extern sys_addr TR_base; /* Base Address */
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extern word TR_limit; /* Segment 'size' */
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/* Interrupt status, defines any abnormal processing */
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extern int doing_contributory;
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extern int doing_double_fault;
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/* HOST - decoded access rights */
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extern int ALC_CS;
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extern int ALC_DS;
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extern int ALC_ES;
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extern int ALC_SS;
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#define X_REAL 0
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#define C_UPRO 1
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#define C_DNRO 6
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#define C_PROT 2
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#define C_UPRW 7
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#define C_DNRW 8
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#define S_UP 3
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#define S_DOWN 4
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#define S_BAD 5
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#define D_CODE 1
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#define D_UPRO 1
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#define D_DNRO 6
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#define D_UPRW 7
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#define D_DNRW 8
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#define D_BAD 2
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/*
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*
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*******************************************************************
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* The 'C' cpu register access functions. *
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*******************************************************************
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*
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*/
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#define getCS_SELECTOR() CS.X
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#define getDS_SELECTOR() DS.X
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#define getSS_SELECTOR() SS.X
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#define getES_SELECTOR() ES.X
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#define getCS_AR() CS_AR
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#define getDS_AR() DS_AR
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#define getSS_AR() SS_AR
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#define getES_AR() ES_AR
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#define getCS_BASE() CS_base
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#define getDS_BASE() DS_base
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#define getSS_BASE() SS_base
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#define getES_BASE() ES_base
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#define getCS_LIMIT() CS_limit
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#define getDS_LIMIT() DS_limit
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#define getSS_LIMIT() SS_limit
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#define getES_LIMIT() ES_limit
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#define getLDT_BASE() LDTR_base
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#define getLDT_LIMIT() LDTR_limit
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#define getTR_BASE() TR_base
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#define getTR_LIMIT() TR_limit
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#define setCS_SELECTOR(val) CS.X = val
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#define setDS_SELECTOR(val) DS.X = val
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#define setSS_SELECTOR(val) SS.X = val
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#define setES_SELECTOR(val) ES.X = val
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#define setCS_AR(val) CS_AR = val
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#define setDS_AR(val) DS_AR = val
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#define setSS_AR(val) SS_AR = val
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#define setES_AR(val) ES_AR = val
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#define setCS_BASE(val) CS_base = val
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#define setDS_BASE(val) DS_base = val
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#define setSS_BASE(val) SS_base = val
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#define setES_BASE(val) ES_base = val
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#define setCS_LIMIT(val) CS_limit = val
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#define setDS_LIMIT(val) DS_limit = val
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#define setSS_LIMIT(val) SS_limit = val
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#define setES_LIMIT(val) ES_limit = val
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#define setLDT_BASE(val) LDTR_base = val
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#define setLDT_LIMIT(val) LDTR_limit = val
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#define setTR_BASE(val) TR_base = val
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#define setTR_LIMIT(val) TR_limit = val
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/*
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* The Machine Status Word structure
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*/
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typedef struct
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{
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unsigned int :16;
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unsigned int reserved:12;
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unsigned int TS:1;
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unsigned int EM:1;
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unsigned int MP:1;
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unsigned int PE:1;
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} mreg;
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extern sys_addr address_line_mask;
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extern int CPL; /* Current Privilege Level */
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/* Global Descriptor Table Register */
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extern sys_addr GDTR_base; /* Base Address */
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extern word GDTR_limit; /* Segment 'size' */
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/* Interrupt Descriptor Table Register */
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extern sys_addr IDTR_base; /* Base Address */
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extern word IDTR_limit; /* Segment 'size' */
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/* Local Descriptor Table Register */
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extern reg LDTR; /* Selector */
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/* Task Register */
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extern reg TR; /* Selector */
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extern mreg MSW; /* Machine Status Word */
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extern int STATUS_CF;
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extern int STATUS_SF;
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extern int STATUS_ZF;
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extern int STATUS_AF;
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extern int STATUS_OF;
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extern int STATUS_PF;
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extern int STATUS_TF;
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extern int STATUS_IF;
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extern int STATUS_DF;
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extern int STATUS_NT;
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extern int STATUS_IOPL;
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/*
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**==========================================================================
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** The CCPU basic register access macros. These may be overridden in
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** host-cpu.h.
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**==========================================================================
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*/
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#ifndef getAX
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/* READ functions */
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#define getAX() (A.X)
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#define getAH() (A.byte.high)
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#define getAL() (A.byte.low)
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#define getBX() (B.X)
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#define getBH() (B.byte.high)
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#define getBL() (B.byte.low)
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#define getCX() (C.X)
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#define getCH() (C.byte.high)
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#define getCL() (C.byte.low)
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#define getDX() (D.X)
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#define getDH() (D.byte.high)
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#define getDL() (D.byte.low)
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#define getSP() (SP.X)
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#define getBP() (BP.X)
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#define getSI() (SI.X)
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#define getDI() (DI.X)
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#define getIP() (IP.X)
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#define getCS() (CS.X)
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#define getDS() (DS.X)
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#define getES() (ES.X)
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#define getSS() (SS.X)
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#define getMSW() (m_s_w)
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#define getDF() (STATUS_DF)
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#define getIF() (STATUS_IF)
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#define getTF() (STATUS_TF)
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#define getPF() (STATUS_PF)
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#define getAF() (STATUS_AF)
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#define getSF() (STATUS_SF)
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#define getZF() (STATUS_ZF)
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#define getOF() (STATUS_OF)
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#define getCF() (STATUS_CF)
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#define getCPL() (CPL)
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#define getGDT_BASE() (GDTR_base)
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#define getGDT_LIMIT() (GDTR_limit)
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#define getIDT_BASE() (IDTR_base)
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#define getIDT_LIMIT() (IDTR_limit)
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#define getLDT_SELECTOR() (LDTR.X)
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#define getTR_SELECTOR() (TR.X)
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#define getMSW_reserved() (MSW.reserved)
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#define getTS() (MSW.TS)
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#define getEM() (MSW.EM)
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#define getMP() (MSW.MP)
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#define getPE() (MSW.PE)
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#define getNT() (STATUS_NT)
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#define getIOPL() (STATUS_IOPL)
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#define getSTATUS() (getCF() | \
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getOF() << 11 | \
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getZF() << 6 | \
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getSF() << 7 | \
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getAF() << 4 | \
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getPF() << 2 | \
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getTF() << 8 | \
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getIF() << 9 | \
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getDF() << 10 | \
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getIOPL() << 12 | \
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getNT() << 14)
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extern ext_load_CS();
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extern ext_load_DS();
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extern ext_load_ES();
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extern ext_load_SS();
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/* WRITE functions */
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#define setAX(val) (A.X = (val))
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#define setAH(val) (A.byte.high = (val))
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#define setAL(val) (A.byte.low = (val))
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#define setBX(val) (B.X = (val))
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#define setBH(val) (B.byte.high = (val))
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#define setBL(val) (B.byte.low = (val))
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#define setCX(val) (C.X = (val))
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#define setCH(val) (C.byte.high = (val))
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#define setCL(val) (C.byte.low = (val))
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#define setDX(val) (D.X = (val))
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#define setDH(val) (D.byte.high = (val))
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#define setDL(val) (D.byte.low = (val))
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#define setSP(val) (SP.X = (val))
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#define setBP(val) (BP.X = (val))
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#define setSI(val) (SI.X = (val))
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#define setDI(val) (DI.X = (val))
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#define setIP(val) (IP.X = (val))
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#define setCS(val) ext_load_CS (val)
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#define setDS(val) ext_load_DS (val)
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#define setES(val) ext_load_ES (val)
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#define setSS(val) ext_load_SS (val)
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#define setMSW(val) (m_s_w = (val))
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#define setDF(val) (STATUS_DF = (val))
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#define setIF(val) (STATUS_IF = (val))
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#define setTF(val) (STATUS_TF = (val))
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#define setPF(val) (STATUS_PF = (val))
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#define setAF(val) (STATUS_AF = (val))
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#define setSF(val) (STATUS_SF = (val))
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#define setZF(val) (STATUS_ZF = (val))
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#define setOF(val) (STATUS_OF = (val))
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#define setCF(val) (STATUS_CF = (val))
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#define setCPL(val) (CPL = (val))
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#define setGDT_BASE(val) (GDTR_base = (val))
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#define setGDT_LIMIT(val) (GDTR_limit = (val))
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#define setIDT_BASE(val) (IDTR_base = (val))
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#define setIDT_LIMIT(val) (IDTR_limit = (val))
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#define setLDT_SELECTOR(val) (LDTR.X = (val))
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#define setTR_SELECTOR(val) (TR.X = (val))
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#define setMSW_reserved(val) (MSW.reserved = (val))
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#define setTS(val) (MSW.TS = (val))
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#define setEM(val) (MSW.EM = (val))
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#define setMP(val) (MSW.MP = (val))
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#define setPE(val) (MSW.PE = (val))
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#define setNT(val) (STATUS_NT = (val))
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#define setIOPL(val) (STATUS_IOPL = (val))
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#endif /* getAX - default CCPU register access macros */
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#endif /* CCPU */
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/*
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* No non-386 cpu can run in VM mode, so getVM is always zero.
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*
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* We also have definition of the GetInstructionPointer and GetStackPointer
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* interfaces, which on a non-386 can only be the 16 bit versions.
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*/
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#ifndef SPC386
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#define getVM() 0
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#define GetInstructionPointer() ((IU32)getIP())
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#define GetStackPointer() ((IU32getSP())
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#endif
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#ifdef CPU_PRIVATE
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/*
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* Map new "private" cpu interface -> old interface
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*/
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#define setIDT_BASE_LIMIT(base,limit) { setIDT_BASE(base); setIDT_LIMIT(limit); }
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#define setGDT_BASE_LIMIT(base,limit) { setGDT_BASE(base); setGDT_LIMIT(limit); }
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#define setLDT_BASE_LIMIT(base,limit) { setLDT_BASE(base); setLDT_LIMIT(limit); }
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#define setTR_BASE_LIMIT(base,limit) { setTR_BASE(base); setTR_LIMIT(limit); }
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#define setCS_BASE_LIMIT_AR(base,limit,ar) { setCS_BASE(base); setCS_LIMIT(limit); setCS_AR(ar); }
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#define setES_BASE_LIMIT_AR(base,limit,ar) { setES_BASE(base); setES_LIMIT(limit); setES_AR(ar); }
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#define setSS_BASE_LIMIT_AR(base,limit,ar) { setSS_BASE(base); setSS_LIMIT(limit); setSS_AR(ar); }
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#define setDS_BASE_LIMIT_AR(base,limit,ar) { setDS_BASE(base); setDS_LIMIT(limit); setDS_AR(ar); }
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#define setFS_BASE_LIMIT_AR(base,limit,ar) { setFS_BASE(base); setFS_LIMIT(limit); setFS_AR(ar); }
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#define setGS_BASE_LIMIT_AR(base,limit,ar) { setGS_BASE(base); setGS_LIMIT(limit); setGS_AR(ar); }
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#endif /* CPU_PRIVATE */
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