1191 lines
39 KiB
C
1191 lines
39 KiB
C
/*++
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Copyright (c) 1992 Microsoft Corporation
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Module Name:
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ia64 psr
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Abstract:
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KD Extension Api
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Author:
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Thierry Fevrier (v-thief)
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Environment:
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User Mode.
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Revision History:
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--*/
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#include "precomp.h"
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#pragma hdrstop
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#include "ia64.h"
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//
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// EmPsrFields: EM register fields for the Processor Status Register.
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//
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EM_REG_FIELD EmPsrFields[] = {
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{ "rv", "reserved0" , 0x1, 0 }, // 0
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{ "be", "Big-Endian" , 0x1, 1 }, // 1
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{ "up", "User Performance monitor enable", 0x1, 2 }, // 2
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{ "ac", "Alignment Check", 0x1, 3 }, // 3
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{ "mfl", "Lower floating-point registers written", 0x1, 4 }, // 4
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{ "mfh", "Upper floating-point registers written", 0x1, 5 }, // 5
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{ "rv", "reserved1", 0x7, 6 }, // 6-12
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{ "ic", "Interruption Collection", 0x1, 13 }, // 13
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{ "i", "Interrupt enable", 0x1, 14 }, // 14
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{ "pk", "Protection Key enable", 0x1, 15 }, // 15
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{ "rv", "reserved2", 0x1, 16 }, // 16
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{ "dt", "Data Address Translation enable", 0x1, 17 }, // 17
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{ "dfl", "Disabled Floating-point Low register set", 0x1, 18 }, // 18
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{ "dfh", "Disabled Floating-point High register set", 0x1, 19 }, // 19
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{ "sp", "Secure Performance monitors", 0x1, 20 }, // 20
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{ "pp", "Privileged Performance monitor enable", 0x1, 21 }, // 21
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{ "di", "Disable Instruction set transition", 0x1, 22 }, // 22
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{ "si", "Secure Interval timer", 0x1, 23 }, // 23
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{ "db", "Debug Breakpoint fault enable", 0x1, 24 }, // 24
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{ "lp", "Lower Privilege transfer trap enable", 0x1, 25 }, // 25
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{ "tb", "Taken Branch trap enable", 0x1, 26 }, // 26
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{ "rt", "Register stack translation enable", 0x1, 27 }, // 27
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{ "rv", "reserved3", 0x4, 28 }, // 28-31
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{ "cpl", "Current Privilege Level", 0x2, 32 }, // 32-33
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{ "is", "Instruction Set", 0x1, 34 }, // 34
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{ "mc", "Machine Abort Mask delivery disable", 0x1, 35 }, // 35
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{ "it", "Instruction address Translation enable", 0x1, 36 }, // 36
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{ "id", "Instruction Debug fault disable", 0x1, 37 }, // 37
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{ "da", "Disable Data Access and Dirty-bit faults", 0x1, 38 }, // 38
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{ "dd", "Data Debug fault disable", 0x1, 39 }, // 39
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{ "ss", "Single Step enable", 0x1, 40 }, // 40
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{ "ri", "Restart Instruction", 0x2, 41 }, // 41-42
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{ "ed", "Exception Deferral", 0x1, 43 }, // 43
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{ "bn", "register Bank", 0x1, 44 }, // 44
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{ "ia", "Disable Instruction Access-bit faults", 0x1, 45 }, // 45
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{ "rv", "reserved4", 0x12, 46 } // 46-63
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};
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VOID
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DisplayPsrIA64(
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IN const PCHAR Header,
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IN EM_PSR EmPsr,
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IN DISPLAY_MODE DisplayMode
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)
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{
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dprintf("%s", Header ? Header : "" );
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if ( DisplayMode >= DISPLAY_MED ) {
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DisplayFullEmReg( EM_PSRToULong64(EmPsr), EmPsrFields, DisplayMode );
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}
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else {
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dprintf(
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"ia bn ed ri ss dd da id it mc is cpl rt tb lp db\n\t\t "
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"%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x\n\t\t"
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"si di pp sp dfh dfl dt pk i ic | mfh mfl ac up be\n\t\t "
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"%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x | %1I64x %1I64x %1I64x %1I64x %1I64x\n",
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EmPsr.ia,
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EmPsr.bn,
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EmPsr.ed,
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EmPsr.ri,
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EmPsr.ss,
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EmPsr.dd,
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EmPsr.da,
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EmPsr.id,
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EmPsr.it,
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EmPsr.mc,
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EmPsr.is,
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EmPsr.cpl,
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EmPsr.rt,
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EmPsr.tb,
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EmPsr.lp,
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EmPsr.db,
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EmPsr.si,
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EmPsr.di,
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EmPsr.pp,
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EmPsr.sp,
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EmPsr.dfh,
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EmPsr.dfl,
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EmPsr.dt,
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EmPsr.pk,
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EmPsr.i,
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EmPsr.ic,
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EmPsr.mfh,
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EmPsr.mfl,
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EmPsr.ac,
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EmPsr.up,
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EmPsr.be
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);
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}
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return;
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} // DisplayPsrIA64()
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DECLARE_API( psr )
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/*++
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Routine Description:
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Dumps an IA64 Processor Status Word
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Arguments:
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args - Supplies the address in hex.
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Return Value:
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None
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--*/
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{
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ULONG64 psrValue;
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ULONG result;
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ULONG flags = 0;
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char *header;
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result = sscanf(args,"%X %lx", &psrValue, &flags);
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psrValue = GetExpression(args);
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if ((result != 1) && (result != 2)) {
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//
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// If user specified "@ipsr"...
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//
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char ipsrStr[16];
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result = sscanf(args, "%s %lx", ipsrStr, &flags);
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if ( ((result != 1) && (result != 2)) || strcmp(ipsrStr,"@ipsr") ) {
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dprintf("USAGE: !psr 0xValue [display_mode:0,1,2]\n");
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dprintf("USAGE: !psr @ipsr [display_mode:0,1,2]\n");
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return E_INVALIDARG;
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}
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psrValue = GetExpression("@ipsr");
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}
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header = (flags > DISPLAY_MIN) ? NULL : "\tpsr:\t";
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if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
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{
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dprintf("!psr not implemented for this architecture.\n");
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}
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else
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{
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DisplayPsrIA64( header, ULong64ToEM_PSR(psrValue), flags );
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}
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return S_OK;
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} // !psr
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//
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// EmPspFields: EM register fields for the Processor State Parameter.
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//
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EM_REG_FIELD EmPspFields[] = {
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{ "rv", "reserved0" , 0x2, 0 },
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{ "rz", "Rendez-vous successful" , 0x1, 2 },
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{ "ra", "Rendez-vous attempted" , 0x1, 3 },
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{ "me", "Distinct Multiple errors" , 0x1, 4 },
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{ "mn", "Min-state Save Area registered" , 0x1, 5 },
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{ "sy", "Storage integrity synchronized" , 0x1, 6 },
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{ "co", "Continuable" , 0x1, 7 },
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{ "ci", "Machine Check isolated" , 0x1, 8 },
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{ "us", "Uncontained Storage damage" , 0x1, 9 },
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{ "hd", "Hardware damage" , 0x1, 10 },
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{ "tl", "Trap lost" , 0x1, 11 },
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{ "mi", "More Information" , 0x1, 12 },
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{ "pi", "Precise Instruction pointer" , 0x1, 13 },
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{ "pm", "Precise Min-state Save Area" , 0x1, 14 },
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{ "dy", "Processor Dynamic State valid" , 0x1, 15 },
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{ "in", "INIT interruption" , 0x1, 16 },
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{ "rs", "RSE valid" , 0x1, 17 },
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{ "cm", "Machine Check corrected" , 0x1, 18 },
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{ "ex", "Machine Check expected" , 0x1, 19 },
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{ "cr", "Control Registers valid" , 0x1, 20 },
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{ "pc", "Performance Counters valid" , 0x1, 21 },
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{ "dr", "Debug Registers valid" , 0x1, 22 },
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{ "tr", "Translation Registers valid" , 0x1, 23 },
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{ "rr", "Region Registers valid" , 0x1, 24 },
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{ "ar", "Application Registers valid" , 0x1, 25 },
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{ "br", "Branch Registers valid" , 0x1, 26 },
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{ "pr", "Predicate Registers valid" , 0x1, 27 },
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{ "fp", "Floating-Point Registers valid" , 0x1, 28 },
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{ "b1", "Preserved Bank 1 General Registers valid" , 0x1, 29 },
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{ "b0", "Preserved Bank 0 General Registers valid" , 0x1, 30 },
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{ "gr", "General Registers valid" , 0x1, 31 },
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{ "dsize", "Processor Dynamic State size" , 0x10, 32 },
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{ "rv", "reserved1" , 0xB, 48 },
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{ "cc", "Cache Check" , 0x1, 59 },
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{ "tc", "TLB Check" , 0x1, 60 },
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{ "bc", "Bus Check" , 0x1, 61 },
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{ "rc", "Register File Check" , 0x1, 62 },
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{ "uc", "Micro-Architectural Check" , 0x1, 63 }
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};
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VOID
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DisplayPspIA64(
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IN const PCHAR Header,
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IN EM_PSP EmPsp,
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IN DISPLAY_MODE DisplayMode
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)
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{
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dprintf("%s", Header ? Header : "" );
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if ( DisplayMode >= DISPLAY_MED ) {
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DisplayFullEmReg( EM_PSPToULong64(EmPsp), EmPspFields, DisplayMode );
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}
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else {
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dprintf(
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"gr b0 b1 fp pr br ar rr tr dr pc cr ex cm rs in dy pm pi mi tl hd us ci co sy mn me ra rz\n\t\t "
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"%1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x %1I64x\n\t\t"
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"uc rc bc tc cc dsize\n\t\t "
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"%1I64x %1I64x %1I64x %1I64x %1I64x %I64x\n",
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EmPsp.gr,
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EmPsp.b0,
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EmPsp.b1,
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EmPsp.fp,
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EmPsp.pr,
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EmPsp.br,
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EmPsp.ar,
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EmPsp.rr,
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EmPsp.tr,
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EmPsp.dr,
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EmPsp.pc,
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EmPsp.cr,
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EmPsp.ex,
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EmPsp.cm,
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EmPsp.rs,
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EmPsp.in,
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EmPsp.dy,
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EmPsp.pm,
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EmPsp.pi,
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EmPsp.mi,
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EmPsp.tl,
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EmPsp.hd,
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EmPsp.us,
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EmPsp.ci,
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EmPsp.co,
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EmPsp.sy,
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EmPsp.mn,
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EmPsp.me,
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EmPsp.ra,
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EmPsp.rz,
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EmPsp.uc,
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EmPsp.rc,
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EmPsp.bc,
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EmPsp.tc,
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EmPsp.cc,
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EmPsp.dsize
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);
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}
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return;
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} // DisplayPspIA64()
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DECLARE_API( psp )
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/*++
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Routine Description:
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Dumps an IA64 Processor State Parameter
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Arguments:
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args - Supplies the address in hex.
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Return Value:
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None
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--*/
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{
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ULONG64 pspValue;
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ULONG result;
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ULONG flags = 0;
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char *header;
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INIT_API();
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pspValue = (ULONG64)0;
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flags = 0;
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if ( GetExpressionEx( args, &pspValue, &args ) ) {
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if ( args && *args ) {
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flags = (ULONG) GetExpression( args );
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}
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}
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header = (flags > DISPLAY_MIN) ? NULL : "\tpsp:\t";
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if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
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{
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dprintf("!psp not implemented for this architecture.\n");
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}
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else
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{
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DisplayPspIA64( header, ULong64ToEM_PSP(pspValue), flags );
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}
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EXIT_API();
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return S_OK;
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} // !psp
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#define PROCESSOR_MINSTATE_SAVE_AREA_FORMAT_IA64 \
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"\tGRNats : 0x%I64x\n" \
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"\tGR1 : 0x%I64x\n" \
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"\tGR2 : 0x%I64x\n" \
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"\tGR3 : 0x%I64x\n" \
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"\tGR4 : 0x%I64x\n" \
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"\tGR5 : 0x%I64x\n" \
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"\tGR6 : 0x%I64x\n" \
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"\tGR7 : 0x%I64x\n" \
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"\tGR8 : 0x%I64x\n" \
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"\tGR9 : 0x%I64x\n" \
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"\tGR10 : 0x%I64x\n" \
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"\tGR11 : 0x%I64x\n" \
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"\tGR12 : 0x%I64x\n" \
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"\tGR13 : 0x%I64x\n" \
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"\tGR14 : 0x%I64x\n" \
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"\tGR15 : 0x%I64x\n" \
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"\tBank0GR16 : 0x%I64x\n" \
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"\tBank0GR17 : 0x%I64x\n" \
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"\tBank0GR18 : 0x%I64x\n" \
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"\tBank0GR19 : 0x%I64x\n" \
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"\tBank0GR20 : 0x%I64x\n" \
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"\tBank0GR21 : 0x%I64x\n" \
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"\tBank0GR22 : 0x%I64x\n" \
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"\tBank0GR23 : 0x%I64x\n" \
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"\tBank0GR24 : 0x%I64x\n" \
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"\tBank0GR25 : 0x%I64x\n" \
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"\tBank0GR26 : 0x%I64x\n" \
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"\tBank0GR27 : 0x%I64x\n" \
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"\tBank0GR28 : 0x%I64x\n" \
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"\tBank0GR29 : 0x%I64x\n" \
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"\tBank0GR30 : 0x%I64x\n" \
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"\tBank0GR31 : 0x%I64x\n" \
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"\tBank1GR16 : 0x%I64x\n" \
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"\tBank1GR17 : 0x%I64x\n" \
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"\tBank1GR18 : 0x%I64x\n" \
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"\tBank1GR19 : 0x%I64x\n" \
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"\tBank1GR20 : 0x%I64x\n" \
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"\tBank1GR21 : 0x%I64x\n" \
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"\tBank1GR22 : 0x%I64x\n" \
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"\tBank1GR23 : 0x%I64x\n" \
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"\tBank1GR24 : 0x%I64x\n" \
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"\tBank1GR25 : 0x%I64x\n" \
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"\tBank1GR26 : 0x%I64x\n" \
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"\tBank1GR27 : 0x%I64x\n" \
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"\tBank1GR28 : 0x%I64x\n" \
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"\tBank1GR29 : 0x%I64x\n" \
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"\tBank1GR30 : 0x%I64x\n" \
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"\tBank1GR31 : 0x%I64x\n" \
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"\tPreds : 0x%I64x\n" \
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"\tBR0 : 0x%I64x\n" \
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"\tRSC : 0x%I64x\n" \
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"\tIIP : 0x%I64x\n" \
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"\tIPSR : 0x%I64x\n" \
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"\tIFS : 0x%I64x\n" \
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"\tXIP : 0x%I64x\n" \
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"\tXPSR : 0x%I64x\n" \
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"\tXFS : 0x%I64x\n\n"
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VOID
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DisplayProcessorMinStateSaveArea(
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ULONG64 Pmssa
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)
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{
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ULONG pmssaSize;
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pmssaSize = GetTypeSize("hal!_PROCESSOR_MINSTATE_SAVE_AREA");
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dprintf("\tProcessor MinState Save Area @ 0x%I64x\n", Pmssa );
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if ( pmssaSize ) {
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CHAR cmd[MAX_PATH];
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sprintf(cmd, "dt -o -r hal!_PROCESSOR_MINSTATE_SAVE_AREA 0x%I64x", Pmssa);
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ExecCommand(cmd);
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}
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else {
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PROCESSOR_MINSTATE_SAVE_AREA_IA64 minStateSaveArea;
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ULONG bytesRead = 0;
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pmssaSize = sizeof(minStateSaveArea);
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ReadMemory( Pmssa, &minStateSaveArea, pmssaSize, &bytesRead );
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if ( bytesRead >= pmssaSize ) {
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dprintf( PROCESSOR_MINSTATE_SAVE_AREA_FORMAT_IA64,
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minStateSaveArea.GRNats,
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minStateSaveArea.GR1,
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minStateSaveArea.GR2,
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minStateSaveArea.GR3,
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minStateSaveArea.GR4,
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minStateSaveArea.GR5,
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minStateSaveArea.GR6,
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minStateSaveArea.GR7,
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minStateSaveArea.GR8,
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minStateSaveArea.GR9,
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minStateSaveArea.GR10,
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minStateSaveArea.GR11,
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minStateSaveArea.GR12,
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minStateSaveArea.GR13,
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minStateSaveArea.GR14,
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minStateSaveArea.GR15,
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minStateSaveArea.Bank0GR16,
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minStateSaveArea.Bank0GR17,
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minStateSaveArea.Bank0GR18,
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minStateSaveArea.Bank0GR19,
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minStateSaveArea.Bank0GR20,
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minStateSaveArea.Bank0GR21,
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minStateSaveArea.Bank0GR22,
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minStateSaveArea.Bank0GR23,
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minStateSaveArea.Bank0GR24,
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minStateSaveArea.Bank0GR25,
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minStateSaveArea.Bank0GR26,
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minStateSaveArea.Bank0GR27,
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minStateSaveArea.Bank0GR28,
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minStateSaveArea.Bank0GR29,
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minStateSaveArea.Bank0GR30,
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minStateSaveArea.Bank0GR31,
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minStateSaveArea.Bank1GR16,
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minStateSaveArea.Bank1GR17,
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minStateSaveArea.Bank1GR18,
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minStateSaveArea.Bank1GR19,
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minStateSaveArea.Bank1GR20,
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minStateSaveArea.Bank1GR21,
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minStateSaveArea.Bank1GR22,
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minStateSaveArea.Bank1GR23,
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minStateSaveArea.Bank1GR24,
|
|
minStateSaveArea.Bank1GR25,
|
|
minStateSaveArea.Bank1GR26,
|
|
minStateSaveArea.Bank1GR27,
|
|
minStateSaveArea.Bank1GR28,
|
|
minStateSaveArea.Bank1GR29,
|
|
minStateSaveArea.Bank1GR30,
|
|
minStateSaveArea.Bank1GR31,
|
|
minStateSaveArea.Preds,
|
|
minStateSaveArea.BR0,
|
|
minStateSaveArea.RSC,
|
|
minStateSaveArea.IIP,
|
|
minStateSaveArea.IPSR,
|
|
minStateSaveArea.IFS,
|
|
minStateSaveArea.XIP,
|
|
minStateSaveArea.XPSR,
|
|
minStateSaveArea.XFS
|
|
);
|
|
}
|
|
else {
|
|
dprintf("Reading _PROCESSOR_MINSTATE_SAVE_AREA directly from memory failed @ 0x%I64x.\n", Pmssa );
|
|
}
|
|
}
|
|
|
|
return;
|
|
|
|
} // DisplayProcessorMinStateSaveArea()
|
|
|
|
DECLARE_API( pmssa )
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Dumps memory address as an IA64 Processor Min-State Save Area.
|
|
|
|
Arguments:
|
|
|
|
args - Supplies the address in hex.
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG64 pmssaValue;
|
|
ULONG result;
|
|
|
|
char *header;
|
|
|
|
pmssaValue = GetExpression(args);
|
|
if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
|
|
{
|
|
dprintf("!pmssa not implemented for this architecture.\n");
|
|
}
|
|
else
|
|
{
|
|
if ( pmssaValue ) {
|
|
DisplayProcessorMinStateSaveArea( pmssaValue );
|
|
}
|
|
else {
|
|
dprintf("usage: pmssa <address>\n");
|
|
}
|
|
}
|
|
|
|
return S_OK;
|
|
|
|
} // !pmssa
|
|
|
|
#define PROCESSOR_CONTROL_REGISTERS_FORMAT_IA64 \
|
|
"\tDCR : 0x%I64x\n" \
|
|
"\tITM : 0x%I64x\n" \
|
|
"\tIVA : 0x%I64x\n" \
|
|
"\tCR3 : 0x%I64x\n" \
|
|
"\tCR4 : 0x%I64x\n" \
|
|
"\tCR5 : 0x%I64x\n" \
|
|
"\tCR6 : 0x%I64x\n" \
|
|
"\tCR7 : 0x%I64x\n" \
|
|
"\tPTA : 0x%I64x\n" \
|
|
"\tGPTA : 0x%I64x\n" \
|
|
"\tCR10 : 0x%I64x\n" \
|
|
"\tCR11 : 0x%I64x\n" \
|
|
"\tCR12 : 0x%I64x\n" \
|
|
"\tCR13 : 0x%I64x\n" \
|
|
"\tCR14 : 0x%I64x\n" \
|
|
"\tCR15 : 0x%I64x\n" \
|
|
"\tIPSR : 0x%I64x\n" \
|
|
"\tISR : 0x%I64x\n" \
|
|
"\tCR18 : 0x%I64x\n" \
|
|
"\tIIP : 0x%I64x\n" \
|
|
"\tIFA : 0x%I64x\n" \
|
|
"\tITIR : 0x%I64x\n" \
|
|
"\tIFS : 0x%I64x\n" \
|
|
"\tIIM : 0x%I64x\n" \
|
|
"\tIHA : 0x%I64x\n" \
|
|
"\tCR26 : 0x%I64x\n" \
|
|
"\tCR27 : 0x%I64x\n" \
|
|
"\tCR28 : 0x%I64x\n" \
|
|
"\tCR29 : 0x%I64x\n" \
|
|
"\tCR30 : 0x%I64x\n" \
|
|
"\tCR31 : 0x%I64x\n" \
|
|
"\tCR32 : 0x%I64x\n" \
|
|
"\tCR33 : 0x%I64x\n" \
|
|
"\tCR34 : 0x%I64x\n" \
|
|
"\tCR35 : 0x%I64x\n" \
|
|
"\tCR36 : 0x%I64x\n" \
|
|
"\tCR37 : 0x%I64x\n" \
|
|
"\tCR38 : 0x%I64x\n" \
|
|
"\tCR39 : 0x%I64x\n" \
|
|
"\tCR40 : 0x%I64x\n" \
|
|
"\tCR41 : 0x%I64x\n" \
|
|
"\tCR42 : 0x%I64x\n" \
|
|
"\tCR43 : 0x%I64x\n" \
|
|
"\tCR44 : 0x%I64x\n" \
|
|
"\tCR45 : 0x%I64x\n" \
|
|
"\tCR46 : 0x%I64x\n" \
|
|
"\tCR47 : 0x%I64x\n" \
|
|
"\tCR48 : 0x%I64x\n" \
|
|
"\tCR49 : 0x%I64x\n" \
|
|
"\tCR50 : 0x%I64x\n" \
|
|
"\tCR51 : 0x%I64x\n" \
|
|
"\tCR52 : 0x%I64x\n" \
|
|
"\tCR53 : 0x%I64x\n" \
|
|
"\tCR54 : 0x%I64x\n" \
|
|
"\tCR55 : 0x%I64x\n" \
|
|
"\tCR56 : 0x%I64x\n" \
|
|
"\tCR57 : 0x%I64x\n" \
|
|
"\tCR58 : 0x%I64x\n" \
|
|
"\tCR59 : 0x%I64x\n" \
|
|
"\tCR60 : 0x%I64x\n" \
|
|
"\tCR61 : 0x%I64x\n" \
|
|
"\tCR62 : 0x%I64x\n" \
|
|
"\tCR63 : 0x%I64x\n" \
|
|
"\tLID : 0x%I64x\n" \
|
|
"\tIVR : 0x%I64x\n" \
|
|
"\tTPR : 0x%I64x\n" \
|
|
"\tEOI : 0x%I64x\n" \
|
|
"\tIRR0 : 0x%I64x\n" \
|
|
"\tIRR1 : 0x%I64x\n" \
|
|
"\tIRR2 : 0x%I64x\n" \
|
|
"\tIRR3 : 0x%I64x\n" \
|
|
"\tITV : 0x%I64x\n" \
|
|
"\tPMV : 0x%I64x\n" \
|
|
"\tCMCV : 0x%I64x\n" \
|
|
"\tCR75 : 0x%I64x\n" \
|
|
"\tCR76 : 0x%I64x\n" \
|
|
"\tCR77 : 0x%I64x\n" \
|
|
"\tCR78 : 0x%I64x\n" \
|
|
"\tCR79 : 0x%I64x\n" \
|
|
"\tLRR0 : 0x%I64x\n" \
|
|
"\tLRR1 : 0x%I64x\n" \
|
|
"\tCR82 : 0x%I64x\n" \
|
|
"\tCR83 : 0x%I64x\n" \
|
|
"\tCR84 : 0x%I64x\n" \
|
|
"\tCR85 : 0x%I64x\n" \
|
|
"\tCR86 : 0x%I64x\n" \
|
|
"\tCR87 : 0x%I64x\n" \
|
|
"\tCR88 : 0x%I64x\n" \
|
|
"\tCR89 : 0x%I64x\n" \
|
|
"\tCR90 : 0x%I64x\n" \
|
|
"\tCR91 : 0x%I64x\n" \
|
|
"\tCR92 : 0x%I64x\n" \
|
|
"\tCR93 : 0x%I64x\n" \
|
|
"\tCR94 : 0x%I64x\n" \
|
|
"\tCR95 : 0x%I64x\n" \
|
|
"\tCR96 : 0x%I64x\n" \
|
|
"\tCR97 : 0x%I64x\n" \
|
|
"\tCR98 : 0x%I64x\n" \
|
|
"\tCR99 : 0x%I64x\n" \
|
|
"\tCR100 : 0x%I64x\n" \
|
|
"\tCR101 : 0x%I64x\n" \
|
|
"\tCR102 : 0x%I64x\n" \
|
|
"\tCR103 : 0x%I64x\n" \
|
|
"\tCR104 : 0x%I64x\n" \
|
|
"\tCR105 : 0x%I64x\n" \
|
|
"\tCR106 : 0x%I64x\n" \
|
|
"\tCR107 : 0x%I64x\n" \
|
|
"\tCR108 : 0x%I64x\n" \
|
|
"\tCR109 : 0x%I64x\n" \
|
|
"\tCR110 : 0x%I64x\n" \
|
|
"\tCR111 : 0x%I64x\n" \
|
|
"\tCR112 : 0x%I64x\n" \
|
|
"\tCR113 : 0x%I64x\n" \
|
|
"\tCR114 : 0x%I64x\n" \
|
|
"\tCR115 : 0x%I64x\n" \
|
|
"\tCR116 : 0x%I64x\n" \
|
|
"\tCR117 : 0x%I64x\n" \
|
|
"\tCR118 : 0x%I64x\n" \
|
|
"\tCR119 : 0x%I64x\n" \
|
|
"\tCR120 : 0x%I64x\n" \
|
|
"\tCR121 : 0x%I64x\n" \
|
|
"\tCR122 : 0x%I64x\n" \
|
|
"\tCR123 : 0x%I64x\n" \
|
|
"\tCR124 : 0x%I64x\n" \
|
|
"\tCR125 : 0x%I64x\n" \
|
|
"\tCR126 : 0x%I64x\n" \
|
|
"\tCR127 : 0x%I64x\n"
|
|
|
|
VOID
|
|
DisplayProcessorControlRegisters(
|
|
ULONG64 Pcrs
|
|
)
|
|
{
|
|
ULONG pcrsSize;
|
|
|
|
pcrsSize = GetTypeSize("hal!_PROCESSOR_CONTROL_REGISTERS");
|
|
dprintf("\tProcessor Control Registers File @ 0x%I64x\n", Pcrs );
|
|
if ( pcrsSize ) {
|
|
CHAR cmd[MAX_PATH];
|
|
sprintf(cmd, "dt -o -r hal!_PROCESSOR_CONTROL_REGISTERS 0x%I64x", Pcrs);
|
|
ExecCommand(cmd);
|
|
}
|
|
else {
|
|
PROCESSOR_CONTROL_REGISTERS_IA64 controlRegisters;
|
|
ULONG bytesRead = 0;
|
|
pcrsSize = sizeof(controlRegisters);
|
|
ReadMemory( Pcrs, &controlRegisters, pcrsSize, &bytesRead );
|
|
if ( bytesRead >= pcrsSize ) {
|
|
dprintf( PROCESSOR_CONTROL_REGISTERS_FORMAT_IA64,
|
|
controlRegisters.DCR,
|
|
controlRegisters.ITM,
|
|
controlRegisters.IVA,
|
|
controlRegisters.CR3,
|
|
controlRegisters.CR4,
|
|
controlRegisters.CR5,
|
|
controlRegisters.CR6,
|
|
controlRegisters.CR7,
|
|
controlRegisters.PTA,
|
|
controlRegisters.GPTA,
|
|
controlRegisters.CR10,
|
|
controlRegisters.CR11,
|
|
controlRegisters.CR12,
|
|
controlRegisters.CR13,
|
|
controlRegisters.CR14,
|
|
controlRegisters.CR15,
|
|
controlRegisters.IPSR,
|
|
controlRegisters.ISR,
|
|
controlRegisters.CR18,
|
|
controlRegisters.IIP,
|
|
controlRegisters.IFA,
|
|
controlRegisters.ITIR,
|
|
controlRegisters.IFS,
|
|
controlRegisters.IIM,
|
|
controlRegisters.IHA,
|
|
controlRegisters.CR26,
|
|
controlRegisters.CR27,
|
|
controlRegisters.CR28,
|
|
controlRegisters.CR29,
|
|
controlRegisters.CR30,
|
|
controlRegisters.CR31,
|
|
controlRegisters.CR32,
|
|
controlRegisters.CR33,
|
|
controlRegisters.CR34,
|
|
controlRegisters.CR35,
|
|
controlRegisters.CR36,
|
|
controlRegisters.CR37,
|
|
controlRegisters.CR38,
|
|
controlRegisters.CR39,
|
|
controlRegisters.CR40,
|
|
controlRegisters.CR41,
|
|
controlRegisters.CR42,
|
|
controlRegisters.CR43,
|
|
controlRegisters.CR44,
|
|
controlRegisters.CR45,
|
|
controlRegisters.CR46,
|
|
controlRegisters.CR47,
|
|
controlRegisters.CR48,
|
|
controlRegisters.CR49,
|
|
controlRegisters.CR50,
|
|
controlRegisters.CR51,
|
|
controlRegisters.CR52,
|
|
controlRegisters.CR53,
|
|
controlRegisters.CR54,
|
|
controlRegisters.CR55,
|
|
controlRegisters.CR56,
|
|
controlRegisters.CR57,
|
|
controlRegisters.CR58,
|
|
controlRegisters.CR59,
|
|
controlRegisters.CR60,
|
|
controlRegisters.CR61,
|
|
controlRegisters.CR62,
|
|
controlRegisters.CR63,
|
|
controlRegisters.LID,
|
|
controlRegisters.IVR,
|
|
controlRegisters.TPR,
|
|
controlRegisters.EOI,
|
|
controlRegisters.IRR0,
|
|
controlRegisters.IRR1,
|
|
controlRegisters.IRR2,
|
|
controlRegisters.IRR3,
|
|
controlRegisters.ITV,
|
|
controlRegisters.PMV,
|
|
controlRegisters.CMCV,
|
|
controlRegisters.CR75,
|
|
controlRegisters.CR76,
|
|
controlRegisters.CR77,
|
|
controlRegisters.CR78,
|
|
controlRegisters.CR79,
|
|
controlRegisters.LRR0,
|
|
controlRegisters.LRR1,
|
|
controlRegisters.CR82,
|
|
controlRegisters.CR83,
|
|
controlRegisters.CR84,
|
|
controlRegisters.CR85,
|
|
controlRegisters.CR86,
|
|
controlRegisters.CR87,
|
|
controlRegisters.CR88,
|
|
controlRegisters.CR89,
|
|
controlRegisters.CR90,
|
|
controlRegisters.CR91,
|
|
controlRegisters.CR92,
|
|
controlRegisters.CR93,
|
|
controlRegisters.CR94,
|
|
controlRegisters.CR95,
|
|
controlRegisters.CR96,
|
|
controlRegisters.CR97,
|
|
controlRegisters.CR98,
|
|
controlRegisters.CR99,
|
|
controlRegisters.CR100,
|
|
controlRegisters.CR101,
|
|
controlRegisters.CR102,
|
|
controlRegisters.CR103,
|
|
controlRegisters.CR104,
|
|
controlRegisters.CR105,
|
|
controlRegisters.CR106,
|
|
controlRegisters.CR107,
|
|
controlRegisters.CR108,
|
|
controlRegisters.CR109,
|
|
controlRegisters.CR110,
|
|
controlRegisters.CR111,
|
|
controlRegisters.CR112,
|
|
controlRegisters.CR113,
|
|
controlRegisters.CR114,
|
|
controlRegisters.CR115,
|
|
controlRegisters.CR116,
|
|
controlRegisters.CR117,
|
|
controlRegisters.CR118,
|
|
controlRegisters.CR119,
|
|
controlRegisters.CR120,
|
|
controlRegisters.CR121,
|
|
controlRegisters.CR122,
|
|
controlRegisters.CR123,
|
|
controlRegisters.CR124,
|
|
controlRegisters.CR125,
|
|
controlRegisters.CR126,
|
|
controlRegisters.CR127
|
|
);
|
|
}
|
|
else {
|
|
dprintf("Reading _PROCESSOR_CONTROL_REGISTERS directly from memory failed @ 0x%I64x.\n", Pcrs );
|
|
}
|
|
}
|
|
|
|
return;
|
|
|
|
} // DisplayProcessorControlRegisters()
|
|
|
|
DECLARE_API( pcrs )
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Dumps memory address as an IA64 Processor Control Registers file.
|
|
|
|
Arguments:
|
|
|
|
args - Supplies the address in hex.
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG64 pcrsValue;
|
|
ULONG result;
|
|
|
|
char *header;
|
|
|
|
pcrsValue = GetExpression(args);
|
|
if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
|
|
{
|
|
dprintf("!pcrs not implemented for this architecture.\n");
|
|
}
|
|
else
|
|
{
|
|
if ( pcrsValue ) {
|
|
DisplayProcessorControlRegisters( pcrsValue );
|
|
}
|
|
else {
|
|
dprintf("usage: pcrs <address>\n");
|
|
}
|
|
}
|
|
|
|
return S_OK;
|
|
|
|
} // !pcrs
|
|
|
|
#define PROCESSOR_APPLICATION_REGISTERS_FORMAT_IA64 \
|
|
"\tKR0 : 0x%I64x\n" \
|
|
"\tKR1 : 0x%I64x\n" \
|
|
"\tKR2 : 0x%I64x\n" \
|
|
"\tKR3 : 0x%I64x\n" \
|
|
"\tKR4 : 0x%I64x\n" \
|
|
"\tKR5 : 0x%I64x\n" \
|
|
"\tKR6 : 0x%I64x\n" \
|
|
"\tKR7 : 0x%I64x\n" \
|
|
"\tAR8 : 0x%I64x\n" \
|
|
"\tAR9 : 0x%I64x\n" \
|
|
"\tAR10 : 0x%I64x\n" \
|
|
"\tAR11 : 0x%I64x\n" \
|
|
"\tAR12 : 0x%I64x\n" \
|
|
"\tAR13 : 0x%I64x\n" \
|
|
"\tAR14 : 0x%I64x\n" \
|
|
"\tAR15 : 0x%I64x\n" \
|
|
"\tRSC : 0x%I64x\n" \
|
|
"\tBSP : 0x%I64x\n" \
|
|
"\tBSPSTORE : 0x%I64x\n" \
|
|
"\tRNAT : 0x%I64x\n" \
|
|
"\tAR20 : 0x%I64x\n" \
|
|
"\tFCR : 0x%I64x\n" \
|
|
"\tAR22 : 0x%I64x\n" \
|
|
"\tAR23 : 0x%I64x\n" \
|
|
"\tEFLAG : 0x%I64x\n" \
|
|
"\tCSD : 0x%I64x\n" \
|
|
"\tSSD : 0x%I64x\n" \
|
|
"\tCFLG : 0x%I64x\n" \
|
|
"\tFSR : 0x%I64x\n" \
|
|
"\tFIR : 0x%I64x\n" \
|
|
"\tFDR : 0x%I64x\n" \
|
|
"\tAR31 : 0x%I64x\n" \
|
|
"\tCCV : 0x%I64x\n" \
|
|
"\tAR33 : 0x%I64x\n" \
|
|
"\tAR34 : 0x%I64x\n" \
|
|
"\tAR35 : 0x%I64x\n" \
|
|
"\tUNAT : 0x%I64x\n" \
|
|
"\tAR37 : 0x%I64x\n" \
|
|
"\tAR38 : 0x%I64x\n" \
|
|
"\tAR39 : 0x%I64x\n" \
|
|
"\tFPSR : 0x%I64x\n" \
|
|
"\tAR41 : 0x%I64x\n" \
|
|
"\tAR42 : 0x%I64x\n" \
|
|
"\tAR43 : 0x%I64x\n" \
|
|
"\tITC : 0x%I64x\n" \
|
|
"\tAR45 : 0x%I64x\n" \
|
|
"\tAR46 : 0x%I64x\n" \
|
|
"\tAR47 : 0x%I64x\n" \
|
|
"\tAR48 : 0x%I64x\n" \
|
|
"\tAR49 : 0x%I64x\n" \
|
|
"\tAR50 : 0x%I64x\n" \
|
|
"\tAR51 : 0x%I64x\n" \
|
|
"\tAR52 : 0x%I64x\n" \
|
|
"\tAR53 : 0x%I64x\n" \
|
|
"\tAR54 : 0x%I64x\n" \
|
|
"\tAR55 : 0x%I64x\n" \
|
|
"\tAR56 : 0x%I64x\n" \
|
|
"\tAR57 : 0x%I64x\n" \
|
|
"\tAR58 : 0x%I64x\n" \
|
|
"\tAR59 : 0x%I64x\n" \
|
|
"\tAR60 : 0x%I64x\n" \
|
|
"\tAR61 : 0x%I64x\n" \
|
|
"\tAR62 : 0x%I64x\n" \
|
|
"\tAR63 : 0x%I64x\n" \
|
|
"\tPFS : 0x%I64x\n" \
|
|
"\tLC : 0x%I64x\n" \
|
|
"\tEC : 0x%I64x\n" \
|
|
"\tAR67 : 0x%I64x\n" \
|
|
"\tAR68 : 0x%I64x\n" \
|
|
"\tAR69 : 0x%I64x\n" \
|
|
"\tAR70 : 0x%I64x\n" \
|
|
"\tAR71 : 0x%I64x\n" \
|
|
"\tAR72 : 0x%I64x\n" \
|
|
"\tAR73 : 0x%I64x\n" \
|
|
"\tAR74 : 0x%I64x\n" \
|
|
"\tAR75 : 0x%I64x\n" \
|
|
"\tAR76 : 0x%I64x\n" \
|
|
"\tAR77 : 0x%I64x\n" \
|
|
"\tAR78 : 0x%I64x\n" \
|
|
"\tAR79 : 0x%I64x\n" \
|
|
"\tAR80 : 0x%I64x\n" \
|
|
"\tAR81 : 0x%I64x\n" \
|
|
"\tAR82 : 0x%I64x\n" \
|
|
"\tAR83 : 0x%I64x\n" \
|
|
"\tAR84 : 0x%I64x\n" \
|
|
"\tAR85 : 0x%I64x\n" \
|
|
"\tAR86 : 0x%I64x\n" \
|
|
"\tAR87 : 0x%I64x\n" \
|
|
"\tAR88 : 0x%I64x\n" \
|
|
"\tAR89 : 0x%I64x\n" \
|
|
"\tAR90 : 0x%I64x\n" \
|
|
"\tAR91 : 0x%I64x\n" \
|
|
"\tAR92 : 0x%I64x\n" \
|
|
"\tAR93 : 0x%I64x\n" \
|
|
"\tAR94 : 0x%I64x\n" \
|
|
"\tAR95 : 0x%I64x\n" \
|
|
"\tAR96 : 0x%I64x\n" \
|
|
"\tAR97 : 0x%I64x\n" \
|
|
"\tAR98 : 0x%I64x\n" \
|
|
"\tAR99 : 0x%I64x\n" \
|
|
"\tAR100 : 0x%I64x\n" \
|
|
"\tAR101 : 0x%I64x\n" \
|
|
"\tAR102 : 0x%I64x\n" \
|
|
"\tAR103 : 0x%I64x\n" \
|
|
"\tAR104 : 0x%I64x\n" \
|
|
"\tAR105 : 0x%I64x\n" \
|
|
"\tAR106 : 0x%I64x\n" \
|
|
"\tAR107 : 0x%I64x\n" \
|
|
"\tAR108 : 0x%I64x\n" \
|
|
"\tAR109 : 0x%I64x\n" \
|
|
"\tAR110 : 0x%I64x\n" \
|
|
"\tAR111 : 0x%I64x\n" \
|
|
"\tAR112 : 0x%I64x\n" \
|
|
"\tAR113 : 0x%I64x\n" \
|
|
"\tAR114 : 0x%I64x\n" \
|
|
"\tAR115 : 0x%I64x\n" \
|
|
"\tAR116 : 0x%I64x\n" \
|
|
"\tAR117 : 0x%I64x\n" \
|
|
"\tAR118 : 0x%I64x\n" \
|
|
"\tAR119 : 0x%I64x\n" \
|
|
"\tAR120 : 0x%I64x\n" \
|
|
"\tAR121 : 0x%I64x\n" \
|
|
"\tAR122 : 0x%I64x\n" \
|
|
"\tAR123 : 0x%I64x\n" \
|
|
"\tAR124 : 0x%I64x\n" \
|
|
"\tAR125 : 0x%I64x\n" \
|
|
"\tAR126 : 0x%I64x\n" \
|
|
"\tAR127 : 0x%I64x\n"
|
|
|
|
VOID
|
|
DisplayProcessorApplicationRegisters(
|
|
ULONG64 Pars
|
|
)
|
|
{
|
|
ULONG parsSize;
|
|
|
|
parsSize = GetTypeSize("hal!_PROCESSOR_APPLICATION_REGISTERS");
|
|
dprintf("\tProcessor Application Registers File @ 0x%I64x\n", Pars );
|
|
if ( parsSize ) {
|
|
CHAR cmd[MAX_PATH];
|
|
sprintf(cmd, "dt -o -r hal!_PROCESSOR_APPLICATION_REGISTERS 0x%I64x", Pars);
|
|
ExecCommand(cmd);
|
|
}
|
|
else {
|
|
PROCESSOR_APPLICATION_REGISTERS_IA64 applicationRegisters;
|
|
ULONG bytesRead = 0;
|
|
parsSize = sizeof(applicationRegisters);
|
|
ReadMemory( Pars, &applicationRegisters, parsSize, &bytesRead );
|
|
if ( bytesRead >= parsSize ) {
|
|
dprintf( PROCESSOR_APPLICATION_REGISTERS_FORMAT_IA64,
|
|
applicationRegisters.KR0,
|
|
applicationRegisters.KR1,
|
|
applicationRegisters.KR2,
|
|
applicationRegisters.KR3,
|
|
applicationRegisters.KR4,
|
|
applicationRegisters.KR5,
|
|
applicationRegisters.KR6,
|
|
applicationRegisters.KR7,
|
|
applicationRegisters.AR8,
|
|
applicationRegisters.AR9,
|
|
applicationRegisters.AR10,
|
|
applicationRegisters.AR11,
|
|
applicationRegisters.AR12,
|
|
applicationRegisters.AR13,
|
|
applicationRegisters.AR14,
|
|
applicationRegisters.AR15,
|
|
applicationRegisters.RSC,
|
|
applicationRegisters.BSP,
|
|
applicationRegisters.BSPSTORE,
|
|
applicationRegisters.RNAT,
|
|
applicationRegisters.AR20,
|
|
applicationRegisters.FCR,
|
|
applicationRegisters.AR22,
|
|
applicationRegisters.AR23,
|
|
applicationRegisters.EFLAG,
|
|
applicationRegisters.CSD,
|
|
applicationRegisters.SSD,
|
|
applicationRegisters.CFLG,
|
|
applicationRegisters.FSR,
|
|
applicationRegisters.FIR,
|
|
applicationRegisters.FDR,
|
|
applicationRegisters.AR31,
|
|
applicationRegisters.CCV,
|
|
applicationRegisters.AR33,
|
|
applicationRegisters.AR34,
|
|
applicationRegisters.AR35,
|
|
applicationRegisters.UNAT,
|
|
applicationRegisters.AR37,
|
|
applicationRegisters.AR38,
|
|
applicationRegisters.AR39,
|
|
applicationRegisters.FPSR,
|
|
applicationRegisters.AR41,
|
|
applicationRegisters.AR42,
|
|
applicationRegisters.AR43,
|
|
applicationRegisters.ITC,
|
|
applicationRegisters.AR45,
|
|
applicationRegisters.AR46,
|
|
applicationRegisters.AR47,
|
|
applicationRegisters.AR48,
|
|
applicationRegisters.AR49,
|
|
applicationRegisters.AR50,
|
|
applicationRegisters.AR51,
|
|
applicationRegisters.AR52,
|
|
applicationRegisters.AR53,
|
|
applicationRegisters.AR54,
|
|
applicationRegisters.AR55,
|
|
applicationRegisters.AR56,
|
|
applicationRegisters.AR57,
|
|
applicationRegisters.AR58,
|
|
applicationRegisters.AR59,
|
|
applicationRegisters.AR60,
|
|
applicationRegisters.AR61,
|
|
applicationRegisters.AR62,
|
|
applicationRegisters.AR63,
|
|
applicationRegisters.PFS,
|
|
applicationRegisters.LC,
|
|
applicationRegisters.EC,
|
|
applicationRegisters.AR67,
|
|
applicationRegisters.AR68,
|
|
applicationRegisters.AR69,
|
|
applicationRegisters.AR70,
|
|
applicationRegisters.AR71,
|
|
applicationRegisters.AR72,
|
|
applicationRegisters.AR73,
|
|
applicationRegisters.AR74,
|
|
applicationRegisters.AR75,
|
|
applicationRegisters.AR76,
|
|
applicationRegisters.AR77,
|
|
applicationRegisters.AR78,
|
|
applicationRegisters.AR79,
|
|
applicationRegisters.AR80,
|
|
applicationRegisters.AR81,
|
|
applicationRegisters.AR82,
|
|
applicationRegisters.AR83,
|
|
applicationRegisters.AR84,
|
|
applicationRegisters.AR85,
|
|
applicationRegisters.AR86,
|
|
applicationRegisters.AR87,
|
|
applicationRegisters.AR88,
|
|
applicationRegisters.AR89,
|
|
applicationRegisters.AR90,
|
|
applicationRegisters.AR91,
|
|
applicationRegisters.AR92,
|
|
applicationRegisters.AR93,
|
|
applicationRegisters.AR94,
|
|
applicationRegisters.AR95,
|
|
applicationRegisters.AR96,
|
|
applicationRegisters.AR97,
|
|
applicationRegisters.AR98,
|
|
applicationRegisters.AR99,
|
|
applicationRegisters.AR100,
|
|
applicationRegisters.AR101,
|
|
applicationRegisters.AR102,
|
|
applicationRegisters.AR103,
|
|
applicationRegisters.AR104,
|
|
applicationRegisters.AR105,
|
|
applicationRegisters.AR106,
|
|
applicationRegisters.AR107,
|
|
applicationRegisters.AR108,
|
|
applicationRegisters.AR109,
|
|
applicationRegisters.AR110,
|
|
applicationRegisters.AR111,
|
|
applicationRegisters.AR112,
|
|
applicationRegisters.AR113,
|
|
applicationRegisters.AR114,
|
|
applicationRegisters.AR115,
|
|
applicationRegisters.AR116,
|
|
applicationRegisters.AR117,
|
|
applicationRegisters.AR118,
|
|
applicationRegisters.AR119,
|
|
applicationRegisters.AR120,
|
|
applicationRegisters.AR121,
|
|
applicationRegisters.AR122,
|
|
applicationRegisters.AR123,
|
|
applicationRegisters.AR124,
|
|
applicationRegisters.AR125,
|
|
applicationRegisters.AR126,
|
|
applicationRegisters.AR127
|
|
);
|
|
}
|
|
else {
|
|
dprintf("Reading _PROCESSOR_APPLICATION_REGISTERS directly from memory failed @ 0x%I64x.\n", Pars );
|
|
}
|
|
}
|
|
|
|
return;
|
|
|
|
} // DisplayProcessorApplicationRegisters()
|
|
|
|
DECLARE_API( pars )
|
|
|
|
/*++
|
|
|
|
Routine Description:
|
|
|
|
Dumps memory address as an IA64 Processor Control Registers file.
|
|
|
|
Arguments:
|
|
|
|
args - Supplies the address in hex.
|
|
|
|
Return Value:
|
|
|
|
None
|
|
|
|
--*/
|
|
|
|
{
|
|
ULONG64 parsValue;
|
|
ULONG result;
|
|
|
|
char *header;
|
|
|
|
parsValue = GetExpression(args);
|
|
if (TargetMachine != IMAGE_FILE_MACHINE_IA64)
|
|
{
|
|
dprintf("!pars not implemented for this architecture.\n");
|
|
}
|
|
else
|
|
{
|
|
if ( parsValue ) {
|
|
DisplayProcessorApplicationRegisters( parsValue );
|
|
}
|
|
else {
|
|
dprintf("usage: pars <address>\n");
|
|
}
|
|
}
|
|
|
|
return S_OK;
|
|
|
|
} // !pars
|
|
|