622 lines
12 KiB
C
622 lines
12 KiB
C
/*++
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Copyright (c) 1995-2000 Microsoft Corporation
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Module Name:
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fragmisc.c
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Abstract:
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Miscellaneous instuction fragments.
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Author:
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12-Jun-1995 BarryBo
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Revision History:
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24-Aug-1999 [askhalid] copied from 32-bit wx86 directory and make work for 64bit.
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20-Sept-1999[barrybo] added FRAG2REF(CmpXchg8bFrag32, ULONGLONG)
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--*/
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#include <nt.h>
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#include <ntrtl.h>
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#include <nturtl.h>
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#include <windows.h>
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#include <stdio.h>
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#include <float.h>
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#include "wx86.h"
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#include "wx86nt.h"
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#include "fragp.h"
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#include "fragmisc.h"
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#include "cpunotif.h"
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#include "config.h"
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#include "mrsw.h"
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#include "cpuassrt.h"
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#if MSCPU
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#include "atomic.h"
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#endif
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ASSERTNAME;
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void
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CpupUnlockTCAndDoInterrupt(
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PTHREADSTATE cpu,
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int Interrupt
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)
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{
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MrswReaderExit(&MrswTC);
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cpu->fTCUnlocked = TRUE;
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CpupDoInterrupt(Interrupt);
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// If we get here, CpupDoInterrupt returned due to CONTINUE_EXECUTION.
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// We need to redesign so we can jump to EndTranslatedCode now, as
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// the cache may have been flushed.
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CPUASSERT(FALSE);
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MrswReaderEnter(&MrswTC);
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cpu->fTCUnlocked = FALSE;
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}
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FRAG0(CbwFrag32)
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{
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eax = (signed long)(signed short)ax;
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}
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FRAG0(CbwFrag16)
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{
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ax = (signed short)(signed char)al;
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}
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FRAG0(PushEsFrag)
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{
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PUSH_LONG(ES);
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}
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FRAG0(PopEsFrag)
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{
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DWORD temp;
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POP_LONG(temp);
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ES = (USHORT)temp;
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}
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FRAG0(PushFsFrag)
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{
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PUSH_LONG(FS);
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}
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FRAG0(PopFsFrag)
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{
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DWORD temp;
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POP_LONG(temp);
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FS = (USHORT)temp;
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}
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FRAG0(PushGsFrag)
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{
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PUSH_LONG(GS);
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}
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FRAG0(PopGsFrag)
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{
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DWORD temp;
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POP_LONG(temp);
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GS = (USHORT)temp;
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}
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FRAG0(PushCsFrag)
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{
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PUSH_LONG(CS);
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}
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FRAG0(AasFrag)
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{
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if ( (al & 0x0f) > 9 || GET_AUXFLAG) {
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ah--;
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al = (al-6) & 0x0f;
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SET_CFLAG_ON;
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SET_AUXFLAG_ON;
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} else {
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SET_CFLAG_OFF;
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SET_AUXFLAG_OFF;
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al &= 0xf;
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}
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}
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FRAG0(PushSsFrag)
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{
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PUSH_LONG(SS);
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}
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FRAG0(PopSsFrag)
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{
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DWORD temp;
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POP_LONG(temp);
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SS = (USHORT)temp;
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}
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FRAG0(PushDsFrag)
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{
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PUSH_LONG(DS);
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}
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FRAG0(PopDsFrag)
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{
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DWORD temp;
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POP_LONG(temp);
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DS = (USHORT)temp;
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}
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FRAG0(DaaFrag)
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{
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if ((al & 0x0f) > 9 || GET_AUXFLAG) {
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al += 6;
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SET_AUXFLAG_ON;
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} else {
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SET_AUXFLAG_OFF;
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}
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if ((al & 0xf0) > 0x90 || GET_CFLAG) {
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al += 0x60;
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SET_CFLAG_ON;
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} else {
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SET_CFLAG_OFF;
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}
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SET_ZFLAG(al);
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SET_PFLAG(al);
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SET_SFLAG(al << (31-7)); // SET_SFLAG_IND(al & 0x80);
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}
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FRAG0(DasFrag)
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{
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if ( (al & 0x0f) > 9 || GET_AUXFLAG) {
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al -= 6;
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SET_AUXFLAG_ON;
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} else {
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SET_AUXFLAG_OFF;
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}
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if ( al > 0x9f || GET_CFLAG) {
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al -= 0x60;
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SET_CFLAG_ON;
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} else {
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SET_CFLAG_OFF;
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}
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SET_ZFLAG(al);
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SET_PFLAG(al);
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SET_SFLAG(al << (31-7)); // SET_SFLAG_IND(al & 0x80);
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}
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FRAG0(AaaFrag)
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{
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if ((al & 0x0f) > 9 || GET_AUXFLAG) {
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al=(al+6) & 0x0f;
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ah++; // inc ah
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SET_AUXFLAG_ON;
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SET_CFLAG_ON;
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} else {
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SET_AUXFLAG_OFF;
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SET_CFLAG_OFF;
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al &= 0xf;
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}
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}
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FRAG1IMM(AadFrag, BYTE)
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{
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al += ah * op1;
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ah = 0;
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SET_ZFLAG(al);
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SET_PFLAG(al);
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SET_SFLAG(al << (31-7)); // SET_SFLAG_IND(al & 0x80);
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}
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FRAG2(ImulFrag16, USHORT)
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{
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Imul3ArgFrag16(cpu, pop1, GET_SHORT(pop1), op2);
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}
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FRAG2(ImulFrag16A, USHORT)
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{
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Imul3ArgFrag16A(cpu, pop1, *pop1, op2);
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}
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FRAG3(Imul3ArgFrag16, USHORT, USHORT, USHORT)
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{
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long result;
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result = (long)(short)op2 * (long)(short)op3;
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PUT_SHORT(pop1, (USHORT)(short)result);
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if (HIWORD(result) == 0 || HIWORD(result) == 0xffff) {
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SET_CFLAG_OFF;
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SET_OFLAG_OFF;
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} else {
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SET_CFLAG_ON;
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SET_OFLAG_ON;
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}
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}
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FRAG3(Imul3ArgFrag16A, USHORT, USHORT, USHORT)
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{
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long result;
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result = (short)op2 * (short)op3;
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*pop1 = (USHORT)(short)result;
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if (HIWORD(result) == 0 || HIWORD(result) == 0xffff) {
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SET_CFLAG_OFF;
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SET_OFLAG_OFF;
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} else {
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SET_CFLAG_ON;
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SET_OFLAG_ON;
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}
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}
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FRAG2(ImulNoFlagsFrag16, USHORT)
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{
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short op1 = (short)GET_SHORT(pop1);
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PUT_SHORT(pop1, (op2 * (short)op2));
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}
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FRAG2(ImulNoFlagsFrag16A, USHORT)
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{
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*(short *)pop1 *= (short)op2;
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}
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FRAG3(Imul3ArgNoFlagsFrag16, USHORT, USHORT, USHORT)
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{
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PUT_SHORT(pop1, ((short)op2 * (short)op3));
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}
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FRAG3(Imul3ArgNoFlagsFrag16A, USHORT, USHORT, USHORT)
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{
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*pop1 = (USHORT)((short)op2 * (short)op3);
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}
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FRAG2(ImulFrag32, DWORD)
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{
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Imul3ArgFrag32(cpu, pop1, GET_LONG(pop1), op2);
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}
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FRAG2(ImulFrag32A, DWORD)
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{
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Imul3ArgFrag32A(cpu, pop1, *pop1, (long)op2);
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}
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FRAG3(Imul3ArgFrag32A, DWORD, DWORD, DWORD)
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{
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LARGE_INTEGER result;
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LONGLONG ll;
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ll = Int32x32To64((long)op2, (long)op3);
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result = *(LARGE_INTEGER *)≪
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*pop1 = result.LowPart;
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if (result.HighPart == 0 || result.HighPart == 0xffffffff) {
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SET_CFLAG_OFF;
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SET_OFLAG_OFF;
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} else {
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SET_CFLAG_ON;
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SET_OFLAG_ON;
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}
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}
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FRAG3(Imul3ArgFrag32, DWORD, DWORD, DWORD)
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{
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LARGE_INTEGER result;
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LONGLONG ll;
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ll = Int32x32To64((long)op2, (long)op3);
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result = *(LARGE_INTEGER *)≪
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PUT_LONG(pop1, result.LowPart);
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if (result.HighPart == 0 || result.HighPart == 0xffffffff) {
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SET_CFLAG_OFF;
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SET_OFLAG_OFF;
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} else {
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SET_CFLAG_ON;
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SET_OFLAG_ON;
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}
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}
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FRAG2(ImulNoFlagsFrag32, DWORD)
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{
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long op1 = (LONG)GET_LONG(pop1);
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PUT_LONG(pop1, (op1 * (long)op2));
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}
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FRAG2(ImulNoFlagsFrag32A, DWORD)
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{
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*(long *)pop1 *= (long)op2;
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}
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FRAG3(Imul3ArgNoFlagsFrag32A, DWORD, DWORD, DWORD)
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{
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*pop1 = (DWORD)( (long)op2 * (long)op3);
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}
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FRAG3(Imul3ArgNoFlagsFrag32, DWORD, DWORD, DWORD)
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{
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PUT_LONG(pop1, ((long)op2 * (long)op3));
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}
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FRAG0(SahfFrag)
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{
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DWORD dw = (DWORD)ah;
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SET_CFLAG(dw << 31); // CFLAG is low-bit of ah
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SET_PFLAG (!(dw & FLAG_PF)); // flag_pf contains an index into ParityBit[] array
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SET_AUXFLAG(dw); // AUX bit is already in the right place
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SET_ZFLAG (!(dw & FLAG_ZF)); // zf has inverse logic
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SET_SFLAG(dw << (31-7)); // SFLAG is bit 7 in AH
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}
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FRAG0(LahfFrag)
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{
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ah= 2 | // this bit is always set on Intel
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((GET_CFLAG) ? FLAG_CF : 0) |
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((GET_PFLAG) ? FLAG_PF : 0) |
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((GET_AUXFLAG)? FLAG_AUX: 0) |
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((cpu->flag_zf) ? 0 : FLAG_ZF) | // zf has inverse logic
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((GET_SFLAG) ? FLAG_SF : 0);
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}
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FRAG1IMM(AamFrag, BYTE)
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{
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ah = al / op1;
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al %= op1;
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SET_ZFLAG(al);
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SET_PFLAG(al);
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SET_SFLAG(al << (31-7));
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}
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FRAG0(XlatFrag)
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{
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al = GET_BYTE(ebx+al);
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}
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FRAG0(CmcFrag)
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{
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SET_CFLAG_IND(!GET_CFLAG);
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}
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FRAG0(ClcFrag)
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{
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SET_CFLAG_OFF;
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}
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FRAG0(StcFrag)
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{
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SET_CFLAG_ON;
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}
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FRAG0(CldFrag)
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{
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cpu->flag_df = 1;
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}
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FRAG0(StdFrag)
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{
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cpu->flag_df = 0xffffffff;
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}
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FRAG1(SetoFrag, BYTE)
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{
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PUT_BYTE(pop1, (BYTE)GET_OFLAGZO);
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}
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FRAG1(SetnoFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_OFLAG == 0));
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}
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FRAG1(SetbFrag, BYTE)
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{
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PUT_BYTE(pop1, (BYTE)GET_CFLAGZO);
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}
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FRAG1(SetaeFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_CFLAG == 0));
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}
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FRAG1(SeteFrag, BYTE)
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{
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PUT_BYTE(pop1, (cpu->flag_zf == 0)); // inverse logic
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}
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FRAG1(SetneFrag, BYTE)
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{
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PUT_BYTE(pop1, (cpu->flag_zf != 0)); // inverse logic
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}
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FRAG1(SetbeFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_CFLAG || cpu->flag_zf == 0)); // inverse logic
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}
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FRAG1(SetaFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_CFLAG == 0 && cpu->flag_zf != 0)); // inverse logic
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}
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FRAG1(SetsFrag, BYTE)
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{
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PUT_BYTE(pop1, (BYTE)GET_SFLAGZO);
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}
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FRAG1(SetnsFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_SFLAG == 0));
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}
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FRAG1(SetpFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_PFLAG != 0));
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}
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FRAG1(SetnpFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_PFLAG == 0));
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}
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FRAG1(SetlFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_SFLAG != GET_OFLAG));
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}
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FRAG1(SetgeFrag, BYTE)
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{
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PUT_BYTE(pop1, (GET_SFLAGZO == GET_OFLAGZO));
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}
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FRAG1(SetleFrag, BYTE)
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{
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PUT_BYTE(pop1, (!cpu->flag_zf || (GET_SFLAG != GET_OFLAG))); // inverse logic
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}
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FRAG1(SetgFrag, BYTE)
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{
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PUT_BYTE(pop1, (cpu->flag_zf && !(GET_SFLAG ^ GET_OFLAG))); // inverse logic
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}
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FRAG2(Movzx8ToFrag16, USHORT)
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{
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PUT_SHORT(pop1, (USHORT)(BYTE)op2);
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}
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FRAG2(Movzx8ToFrag16A, USHORT)
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{
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*pop1 = (USHORT)(BYTE)op2;
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}
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FRAG2(Movsx8ToFrag16, USHORT)
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{
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PUT_SHORT(pop1, (USHORT)(short)(char)(BYTE)op2);
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}
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FRAG2(Movsx8ToFrag16A, USHORT)
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{
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*pop1 = (USHORT)(short)(char)(BYTE)op2;
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}
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FRAG2(Movzx8ToFrag32, DWORD)
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{
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PUT_LONG(pop1, (DWORD)(BYTE)op2);
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}
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FRAG2(Movzx8ToFrag32A, DWORD)
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{
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*pop1 = (DWORD)(BYTE)op2;
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}
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FRAG2(Movsx8ToFrag32, DWORD)
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{
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PUT_LONG(pop1, (DWORD)(long)(char)(BYTE)op2);
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}
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FRAG2(Movsx8ToFrag32A, DWORD)
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{
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*pop1 = (DWORD)(long)(char)(BYTE)op2;
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}
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FRAG2(Movzx16ToFrag32, DWORD)
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{
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PUT_LONG(pop1, (DWORD)(USHORT)op2);
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}
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FRAG2(Movzx16ToFrag32A, DWORD)
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{
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*pop1 = (DWORD)(USHORT)op2;
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}
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FRAG2(Movsx16ToFrag32, DWORD)
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{
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PUT_LONG(pop1, (DWORD)(long)(short)(USHORT)op2);
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}
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FRAG2(Movsx16ToFrag32A, DWORD)
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{
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*pop1 = (DWORD)(long)(short)(USHORT)op2;
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}
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FRAG1(BswapFrag32, DWORD)
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{
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DWORD d;
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PBYTE pSrc = (PBYTE)pop1;
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d = (pSrc[0] << 24) | (pSrc[1] << 16) | (pSrc[2] << 8) | pSrc[3];
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// pop1 is always a pointer to a register, so an ALIGNED store is correct
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*pop1 = d;
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}
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FRAG2(ArplFrag, USHORT)
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{
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USHORT op1 = GET_SHORT(pop1);
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op2 &= 3; // just get the RPL bits of the selector
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if ((op1&3) < op2) {
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// RPL bits of DEST < RPL bits of SRC
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op1 = (op1 & ~3) | op2; // copy RPL bits from SRC to DEST
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PUT_SHORT(pop1, op1); // store DEST
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SET_ZFLAG(0); // ZF=1
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} else {
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SET_ZFLAG(1);
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}
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}
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FRAG1(VerrFrag, USHORT)
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{
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USHORT op1 = GET_SHORT(pop1) & ~3; // mask off RPL bits
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if (op1 == KGDT_R3_CODE || // CS: selector
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op1 == KGDT_R3_DATA || // DS:, SS:, ES: selector
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op1 == KGDT_R3_TEB // FS: selector
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) {
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SET_ZFLAG(0); // ZF=1
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} else {
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SET_ZFLAG(1); // ZF=0
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}
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}
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FRAG1(VerwFrag, USHORT)
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{
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USHORT op1 = GET_SHORT(pop1) & ~3; // mask off RPL bits
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if (op1 == KGDT_R3_DATA || // DS:, SS:, ES: selector
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op1 == KGDT_R3_TEB // FS: selector
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) {
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SET_ZFLAG(0); // ZF=1
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} else {
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SET_ZFLAG(1); // ZF=0
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}
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}
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FRAG1(SmswFrag, USHORT)
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{
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//
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// This value is empirically discovered by running it on a Pentium
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// machine. CR0_PE, CR0_EX, and CR0_NE bits were set, and all others
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// notably CR0_MP, are clear.
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//
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PUT_SHORT(pop1, 0x31);
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}
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#if MSCPU
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|
FRAG0(IntOFrag)
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|
{
|
|
if (GET_OFLAG) {
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|
Int4(); // raise overflow
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|
}
|
|
}
|
|
FRAG0(NopFrag)
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|
{
|
|
}
|
|
FRAG0(PrivilegedInstructionFrag)
|
|
{
|
|
PRIVILEGED_INSTR;
|
|
}
|
|
FRAG0(BadInstructionFrag)
|
|
{
|
|
Int6(); // Throw invalid opcode exception
|
|
}
|
|
FRAG2(FaultFrag, DWORD)
|
|
{
|
|
// pop1 = exception code
|
|
// op2 = address where fault occurred
|
|
#if DBG
|
|
LOGPRINT((TRACELOG, "CPU: FaultFrag called\r\n"));
|
|
#endif
|
|
|
|
RtlRaiseStatus((NTSTATUS)(ULONGLONG)pop1);
|
|
}
|
|
#endif //MSCPU
|
|
FRAG0(CPUID)
|
|
{
|
|
switch (eax) {
|
|
case 0:
|
|
eax = 1; // We are a 486 with CPUID (PPro returns 2)
|
|
//ebx = 0x756e6547; // "GenuineIntel"
|
|
//edx = 0x49656e69;
|
|
//ecx = 0x6c65746e;
|
|
ebx = 0x7263694d; // "Micr" with M in the low nibble of BL
|
|
edx = 0x666f736f; // "osof" with o in the low nibble of DL
|
|
ecx = 0x55504374; // "tCPU" with t in the low nibble of CL
|
|
break;
|
|
|
|
case 1:
|
|
eax = (0 << 12) | // Type = 0 (2 bits) Original OEM Processor
|
|
(4 << 8) | // Family = 4 (4 bits) 80486
|
|
(1 << 4) | // Model = 1 (4 bits)
|
|
0; // Stepping=0 (4 bits)
|
|
edx = (fUseNPXEM) ? 1: 0; // bit 0: FPU on-chip. wx86cpu doesn't
|
|
// support any other features.
|
|
break;
|
|
|
|
default:
|
|
//
|
|
// The Intel behavior indicates that if eax is out-of-range, the
|
|
// results returned in the regsiters are unpredictable but it
|
|
// doesn't fault.
|
|
//
|
|
break;
|
|
}
|
|
}
|
|
FRAG2REF(CmpXchg8bFrag32, ULONGLONG)
|
|
{
|
|
ULONGLONG EdxEax;
|
|
ULONGLONG Value;
|
|
|
|
EdxEax = (((ULONGLONG)edx) << 32) | (ULONGLONG)eax;
|
|
Value = *(ULONGLONG UNALIGNED *)pop1;
|
|
|
|
if (Value == EdxEax) {
|
|
ULONGLONG EcxEbx;
|
|
|
|
EcxEbx = (ULONGLONG)ecx << 32 | (ULONGLONG)ebx;
|
|
*(ULONGLONG UNALIGNED *)pop1 = EcxEbx;
|
|
SET_ZFLAG(0); // zf has inverse logic
|
|
} else {
|
|
eax = (ULONG)Value;
|
|
edx = (ULONG)(Value >> 32);
|
|
SET_ZFLAG(1); // zf has inverse logic
|
|
}
|
|
}
|
|
FRAG0(Rdtsc)
|
|
{
|
|
LARGE_INTEGER Counter;
|
|
|
|
// This is cheese, but it will at least return a value that increases
|
|
// over time.
|
|
NtQueryPerformanceCounter(&Counter, NULL);
|
|
edx = Counter.HighPart;
|
|
eax = Counter.LowPart;
|
|
}
|
|
|