339 lines
12 KiB
C
339 lines
12 KiB
C
/**************************************************************************************************************************
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* STIR4200.H - SigmaTel STIr4200 hardware (register) specific definitions
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**************************************************************************************************************************
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* (C) Unpublished Copyright of Sigmatel, Inc. All Rights Reserved.
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*
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*
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* Created: 04/06/2000
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* Version 0.9
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* Edited: 04/27/2000
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* Version 0.92
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* Edited: 05/03/2000
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* Version 0.93
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* Edited: 05/12/2000
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* Version 0.94
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* Edited: 05/19/2000
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* Version 0.95
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* Edited: 06/29/2000
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* Version 0.97
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* Edited: 08/22/2000
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* Version 1.02
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* Edited: 09/16/2000
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* Version 1.03
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* Edited: 09/25/2000
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* Version 1.10
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* Edited: 11/10/2000
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* Version 1.12
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* Edited: 12/29/2000
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* Version 1.13
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* Edited: 01/16/2001
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* Version 1.14
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*
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*
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**************************************************************************************************************************/
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#ifndef __STIR4200_H__
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#define __STIR4200_H__
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#define STIR4200_FIFO_SIZE 4096
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//
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// Some useful macros
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//
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#define MAKEUSHORT(lo, hi) ((unsigned short)(((unsigned char)(lo)) | ((unsigned short)((unsigned char)(hi))) << 8))
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#define MAKEULONG(lo, hi) ((unsigned long)(((unsigned short)(lo)) | ((unsigned long)((unsigned short)(hi))) << 16))
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#ifndef LOWORD
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#define LOWORD(l) ((unsigned short)(l))
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#endif
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#ifndef HIWORD
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#define HIWORD(l) ((unsigned short)(((unsigned long)(l) >> 16) & 0xFFFF))
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#endif
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#ifndef LOBYTE
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#define LOBYTE(w) ((unsigned char)(w))
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#endif
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#ifndef HIBYTE
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#define HIBYTE(w) ((unsigned char)(((unsigned short)(w) >> 8) & 0xFF))
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#endif
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/**************************************************************************************************************************/
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/* STIr4200 Tranceiver Hardware Model Definitions */
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/**************************************************************************************************************************/
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typedef struct _STIR4200_TRANCEIVER
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{
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UCHAR FifoDataReg;
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UCHAR ModeReg;
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UCHAR BaudrateReg;
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UCHAR ControlReg;
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UCHAR SensitivityReg;
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UCHAR StatusReg;
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UCHAR FifoCntLsbReg;
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UCHAR FifoCntMsbReg;
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UCHAR DpllTuneReg;
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UCHAR IrdigSetupReg;
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UCHAR Reserved1Reg;
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UCHAR Reserved2Reg;
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UCHAR Reserved3Reg;
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UCHAR Reserved4Reg;
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UCHAR Reserved5Reg;
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UCHAR TestReg;
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} STIR4200_TRANCEIVER, *PSTIR4200_TRANCEIVER;
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/**************************************************************************************************************************/
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/* STIr4200 Receiver State */
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/**************************************************************************************************************************/
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typedef enum
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{
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STATE_INIT = 0,
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STATE_GOT_FIR_BOF,
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STATE_GOT_BOF,
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STATE_ACCEPTING,
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STATE_ESC_SEQUENCE,
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STATE_SAW_FIR_BOF,
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STATE_SAW_EOF,
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STATE_CLEANUP
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} PORT_RCV_STATE;
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#define STATE_GOT_MIR_BOF STATE_GOT_FIR_BOF
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#define STATE_SAW_MIR_BOF STATE_SAW_FIR_BOF
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/**************************************************************************************************************************/
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/* Register Offsets */
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/**************************************************************************************************************************/
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#define STIR4200_FIFO_DATA_REG 0
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#define STIR4200_MODE_REG 1
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#define STIR4200_BAUDRATE_REG 2
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#define STIR4200_CONTROL_REG 3
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#define STIR4200_SENSITIVITY_REG 4
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#define STIR4200_STATUS_REG 5
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#define STIR4200_FIFOCNT_LSB_REG 6
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#define STIR4200_FIFOCNT_MSB_REG 7
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#define STIR4200_DPLLTUNE_REG 8
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#define STIR4200_IRDIG_SETUP_REG 9
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#define STIR4200_RESERVE1_REG 10
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#define STIR4200_RESERVE2_REG 11
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#define STIR4200_RESERVE3_REG 12
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#define STIR4200_RESERVE4_REG 13
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#define STIR4200_RESERVE5_REG 14
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#define STIR4200_TEST_REG 15
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#define STIR4200_MAX_REG STIR4200_TEST_REG
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/**************************************************************************************************************************/
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/* Register Bit Definitions */
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/**************************************************************************************************************************/
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#define STIR4200_MODE_PDLCK8 0x01
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#define STIR4200_MODE_RESET_OFF 0x02
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#define STIR4200_MODE_AUTO_RESET 0x04
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#define STIR4200_MODE_BULKIN_FIX 0x08
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#define STIR4200_MODE_FIR 0x80
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#define STIR4200_MODE_MIR 0x40
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#define STIR4200_MODE_SIR 0x20
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#define STIR4200_MODE_ASK 0x10
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#define STIR4200_MODE_MASK (STIR4200_MODE_FIR | STIR4200_MODE_MIR | STIR4200_MODE_SIR | STIR4200_MODE_ASK)
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#define STIR4200_CTRL_SDMODE 0x80
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#define STIR4200_CTRL_RXSLOW 0x40
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#define STIR4200_CTRL_DLOOP1 0x20
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#define STIR4200_CTRL_TXPWD 0x10
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#define STIR4200_CTRL_RXPWD 0x08
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#define STIR4200_CTRL_SRESET 0x01
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#define STIR4200_SENS_IDMASK 0x07
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#define STIR4200_SENS_SPWIDTH 0x08
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#define STIR4200_SENS_BSTUFF 0x10
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#define STIR4200_SENS_RXDSNS_DEFAULT 0x20
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#define STIR4200_SENS_RXDSNS_4012_SIR_9600 0x20
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#define STIR4200_SENS_RXDSNS_4012_SIR 0x00
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#define STIR4200_SENS_RXDSNS_4012_FIR 0x20
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#define STIR4200_SENS_RXDSNS_INFI_SIR 0x07
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#define STIR4200_SENS_RXDSNS_INFI_FIR 0x27
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#define STIR4200_STAT_EOFRAME 0x80
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#define STIR4200_STAT_FFUNDER 0x40
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#define STIR4200_STAT_FFOVER 0x20
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#define STIR4200_STAT_FFDIR 0x10
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#define STIR4200_STAT_FFCLR 0x08
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#define STIR4200_STAT_FFEMPTY 0x04
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#define STIR4200_STAT_FFRXERR 0x02
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#define STIR4200_STAT_FFTXERR 0x01
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#define STIR4200_DPLL_DESIRED_4012 0x05
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#define STIR4200_DPLL_DESIRED_4012_SIR 0x06
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#define STIR4200_DPLL_DESIRED_4012_FIR 0x05
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#define STIR4200_DPLL_DESIRED_4000 0x15
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#define STIR4200_DPLL_DESIRED_VISHAY 0x15
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#define STIR4200_DPLL_DESIRED_INFI 0x15
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#define STIR4200_DPLL_DEFAULT 0x52
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#define STIR4200_TEST_EN_OSC_SUSPEND 0x10
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/**************************************************************************************************************************/
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/* Vendor Specific Device Requests */
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/**************************************************************************************************************************/
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#define STIR4200_WRITE_REGS_REQ 0
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#define STIR4200_READ_REGS_REQ 1
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#define STIR4200_READ_ROM_REQ 2
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#define STIR4200_WRITE_REG_REQ 3
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#define STIR4200_CLEAR_STALL_REQ 1
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/**************************************************************************************************************************/
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/* STIr4200 Frame Header ID Definitions */
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/**************************************************************************************************************************/
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#define STIR4200_HEADERID_BYTE1 0x55
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#define STIR4200_HEADERID_BYTE2 0xAA
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typedef struct _STIR4200_FRAME_HEADER
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{
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UCHAR id1; // header id byte 1
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UCHAR id2; // header id byte 2
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UCHAR sizlsb; // frame size LSB
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UCHAR sizmsb; // frame size MSB
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} STIR4200_FRAME_HEADER, *PSTIR4200_FRAME_HEADER;
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/**************************************************************************************************************************/
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/* STIr4200 Frame Definitions */
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/**************************************************************************************************************************/
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#define STIR4200_FIR_PREAMBLE 0x7f
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#define STIR4200_FIR_PREAMBLE_SIZ 16
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#define STIR4200_FIR_BOF 0x7E
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#define STIR4200_FIR_EOF 0x7E
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#define STIR4200_FIR_BOF_SIZ 2
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#define STIR4200_FIR_EOF_SIZ 2
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#define STIR4200_FIR_ESC_CHAR 0x7d
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#define STIR4200_FIR_ESC_DATA_7D 0x5d
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#define STIR4200_FIR_ESC_DATA_7E 0x5e
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#define STIR4200_FIR_ESC_DATA_7F 0x5f
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#define STIR4200_MIR_BOF 0x7E
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#define STIR4200_MIR_EOF 0x7E
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#define STIR4200_MIR_BOF_SIZ 2
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#define STIR4200_MIR_EOF_SIZ 2
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#define STIR4200_MIR_ESC_CHAR 0x7d
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#define STIR4200_MIR_ESC_DATA_7D 0x5d
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#define STIR4200_MIR_ESC_DATA_7E 0x5e
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//
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// A few workaroud definitions
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//
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#define STIR4200_READ_DELAY 3000
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#define STIR4200_MULTIPLE_READ_DELAY 2500
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#define STIR4200_DELTA_DELAY 250
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#define STIR4200_MAX_BOOST_DELAY 1000
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#define STIR4200_MULTIPLE_READ_THREHOLD 2048
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#define STIR4200_WRITE_DELAY 2000
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#define STIR4200_ESC_PACKET_SIZE 3072
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#define STIR4200_SMALL_PACKET_MAX_SIZE 32
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#define STIR4200_LARGE_PACKET_MIN_SIZE 1024
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#define STIR4200_ACK_WINDOW 20
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#define STIR4200_FIFO_OVERRUN_THRESHOLD 100
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#define STIR4200_SEND_TIMEOUT 2000
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/**************************************************************************************************************************/
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/* Prototypes of functions that access the hardware */
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/**************************************************************************************************************************/
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NTSTATUS
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St4200ResetFifo(
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IN PVOID pDevice
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);
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NTSTATUS
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St4200DoubleResetFifo(
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IN PVOID pDevice
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);
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NTSTATUS
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St4200SoftReset(
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IN PVOID pDevice
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);
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NTSTATUS
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St4200SetSpeed(
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IN OUT PVOID pDevice
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);
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NTSTATUS
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St4200SetIrMode(
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IN OUT PVOID pDevice,
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ULONG mode
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);
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NTSTATUS
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St4200GetFifoCount(
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IN PVOID pDevice,
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OUT PULONG pCountFifo
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);
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NTSTATUS
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St4200TuneDpllAndSensitivity(
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IN OUT PVOID pDevice,
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ULONG Speed
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);
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NTSTATUS
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St4200TurnOffReceiver(
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IN OUT PVOID pDevice
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);
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NTSTATUS
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St4200TurnOnReceiver(
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IN OUT PVOID pDevice
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);
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NTSTATUS
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St4200EnableOscillatorPowerDown(
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IN OUT PVOID pDevice
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);
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NTSTATUS
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St4200TurnOnSuspend(
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IN OUT PVOID pDevice
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);
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NTSTATUS
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St4200TurnOffSuspend(
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IN OUT PVOID pDevice
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);
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NTSTATUS
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St4200WriteMultipleRegisters(
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IN PVOID pDevice,
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UCHAR FirstRegister,
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UCHAR RegistersToWrite
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);
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NTSTATUS
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St4200WriteRegister(
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IN PVOID pDevice,
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UCHAR RegisterToWrite
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);
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NTSTATUS
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St4200ReadRegisters(
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IN OUT PVOID pDevice,
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UCHAR FirstRegister,
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UCHAR RegistersToRead
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);
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NTSTATUS
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St4200FakeSend(
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IN PVOID pDevice,
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PUCHAR pData,
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ULONG DataSize
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);
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NTSTATUS
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St4200CompleteReadWriteRequest(
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IN PDEVICE_OBJECT pUsbDevObj,
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IN PIRP pIrp,
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IN PVOID Context
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);
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/**************************************************************************************************************************/
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#endif // __STIR4200_H__
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