661 lines
18 KiB
C
661 lines
18 KiB
C
//+-------------------------------------------------------------------------
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//
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// Microsoft Windows
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//
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// Copyright (C) Microsoft Corporation, 1999 - 1999
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//
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// File: idep.h
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//
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//--------------------------------------------------------------------------
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#if !defined (___idep_h___)
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#define ___idep_h___
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#include "ide.h"
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#include "wmilib.h"
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// go to ntddscsi.h
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#define SRB_FUNCTION_ATA_POWER_PASS_THROUGH 0xC7
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#define SRB_FUNCTION_ATA_PASS_THROUGH 0xC8
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#define ATA_PTFLAGS_BUS_RESET (1 << 0)
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#define ATA_PTFLAGS_OK_TO_FAIL (1 << 1)
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#define ATA_PTFLAGS_EMPTY_CHANNEL_TEST (1 << 2)
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#define ATA_PTFLAGS_INLINE_HARD_RESET (1 << 3)
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#define ATA_PTFLAGS_ENUM_PROBING (1 << 4)
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#define ATA_PTFLAGS_NO_OP (1 << 5)
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#define ATA_PTFLAGS_STATUS_DRDY_REQUIRED (1 << 6)
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#define ATA_PTFLAGS_URGENT (1 << 7)
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#define MAX_TRANSFER_SIZE_PER_SRB (0x100 * 0x200) // 128k ATA limits
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typedef struct _ATA_PASS_THROUGH {
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IDEREGS IdeReg;
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ULONG DataBufferSize; // byte size of DataBuffer[]
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UCHAR DataBuffer[1];
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}ATA_PASS_THROUGH, *PATA_PASS_THROUGH;
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#define NUM_PNP_MINOR_FUNCTION (0x19)
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#define NUM_POWER_MINOR_FUNCTION (0x04)
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#define NUM_WMI_MINOR_FUNCTION (0xc)
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#define SAMPLE_CYLINDER_LOW_VALUE 0x55
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#define SAMPLE_CYLINDER_HIGH_VALUE 0xaa
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//
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// Scsiops to suuport dvd operation
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// Should go to scsi.h?
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//
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#if 0
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#define SCSIOP_DVD_READ 0xA8
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#endif
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//
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// IDE drive control definitions
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//
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#define IDE_DC_DISABLE_INTERRUPTS 0x02
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#define IDE_DC_RESET_CONTROLLER 0x04
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#define IDE_DC_REENABLE_CONTROLLER 0x00
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//
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// IDE status definitions
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//
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#define IDE_STATUS_ERROR 0x01
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#define IDE_STATUS_INDEX 0x02
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#define IDE_STATUS_CORRECTED_ERROR 0x04
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#define IDE_STATUS_DRQ 0x08
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#define IDE_STATUS_DSC 0x10
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#define IDE_STATUS_DRDY 0x40
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#define IDE_STATUS_IDLE 0x50
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#define IDE_STATUS_BUSY 0x80
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#define GetStatus(BaseIoAddress, Status) \
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Status = READ_PORT_UCHAR((BaseIoAddress)->Command);
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//
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// NEC 98: ide control port.
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//
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#define CURRENT_INTERRUPT_SENCE (PUCHAR)0x430
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#define SELECT_IDE_PORT (PUCHAR)0x432
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//
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// NEC 98: dip-switch 2 system port.
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//
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#define SYSTEM_PORT_A (PUCHAR)0x31
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//
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// NEC 98: check enhanced ide support.
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//
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#define EnhancedIdeSupport() \
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(READ_PORT_UCHAR(CURRENT_INTERRUPT_SENCE)&0x40)?TRUE:FALSE
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//
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// Checking legacy ide on NEC 98.
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//
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#ifdef IsNEC_98
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#undef IsNEC_98
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#endif
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#define IsNEC_98 0
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#define Is98LegacyIde(BaseIoAddress) \
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(BOOLEAN)(IsNEC_98 && \
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((BaseIoAddress)->RegistersBaseAddress == \
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(PUCHAR)IDE_NEC98_COMMAND_PORT_ADDRESS))
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//
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// Select IDE line(Primary or Secondary).
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// lineNumber:
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// 0 - Primary
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// 1 - Secondary
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//
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#define SelectIdeLine(BaseIoAddress,lineNumber) \
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{ \
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if (Is98LegacyIde(BaseIoAddress)) { \
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WRITE_PORT_UCHAR (SELECT_IDE_PORT, (UCHAR)((lineNumber) & 0x1)); \
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} \
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}
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#define SelectIdeDevice(BaseIoAddress, deviceNumber, additional) {\
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SelectIdeLine(BaseIoAddress, (deviceNumber) >>1);\
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WRITE_PORT_UCHAR ((BaseIoAddress)->DriveSelect, (UCHAR)((((deviceNumber) & 0x1) << 4) | 0xA0 | additional));\
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}
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#define GetSelectedIdeDevice(BaseIoAddress, cmd) {\
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cmd=READ_PORT_UCHAR((BaseIoAddress)->DriveSelect);\
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}
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#define ReSelectIdeDevice(BaseIoAddress, cmd) {\
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WRITE_PORT_UCHAR ((BaseIoAddress)->DriveSelect, (UCHAR)cmd);\
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}
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//
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// ISSUE: 08/30/2000 How can I reserve this ioctl value?
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//
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//#define IOCTL_IDE_BIND_BUSMASTER_PARENT CTL_CODE(FILE_DEVICE_CONTROLLER, 0x0500, METHOD_BUFFERED, FILE_ANY_ACCESS)
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//#define IOCTL_IDE_UNBIND_BUSMASTER_PARENT CTL_CODE(FILE_DEVICE_CONTROLLER, 0x0502, METHOD_BUFFERED, FILE_ANY_ACCESS)
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//#define IOCTL_IDE_GET_SYNC_ACCESS CTL_CODE(FILE_DEVICE_CONTROLLER, 0x0503, METHOD_BUFFERED, FILE_ANY_ACCESS)
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//#define IOCTL_IDE_TRANSFER_MODE_SELECT CTL_CODE(FILE_DEVICE_CONTROLLER, 0x0504, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define IOCTL_IDE_GET_RESOURCES_ALLOCATED CTL_CODE(FILE_DEVICE_CONTROLLER, 0x0505, METHOD_BUFFERED, FILE_ANY_ACCESS)
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#define MAX_IDE_DEVICE 2
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#define MAX_IDE_LINE 2
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#define MAX_IDE_CHANNEL 2
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#define MAX_IDE_BUS 1
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#define MAX_IDE_PATH MAX_IDE_BUS
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#define MAX_IDE_TARGETID MAX_IDE_DEVICE
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#define MAX_IDE_LUN 8
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#define IDE_STANDARD_PRIMARY_ADDRESS (0x1f0)
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#define IDE_STANDARD_SECONDARY_ADDRESS (0x170)
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#define IDE_NEC98_COMMAND_PORT_ADDRESS (0x640)
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typedef ULONG BMSTATUS;
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#define BMSTATUS_NO_ERROR (0)
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#define BMSTATUS_NOT_REACH_END_OF_TRANSFER (1 << 0)
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#define BMSTATUS_ERROR_TRANSFER (1 << 1)
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#define BMSTATUS_INTERRUPT (1 << 2)
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#define BMSTATUS_SUCCESS(x) ((x & ~BMSTATUS_INTERRUPT) == 0)
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//
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// IDE Cycle Timing
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//
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#define PIO_MODE0_CYCLE_TIME 600
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#define PIO_MODE1_CYCLE_TIME 383
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#define PIO_MODE2_CYCLE_TIME 240
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#define PIO_MODE3_CYCLE_TIME 180
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#define PIO_MODE4_CYCLE_TIME 120
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#define SWDMA_MODE0_CYCLE_TIME 960
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#define SWDMA_MODE1_CYCLE_TIME 480
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#define SWDMA_MODE2_CYCLE_TIME 240
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#define MWDMA_MODE0_CYCLE_TIME 480
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#define MWDMA_MODE1_CYCLE_TIME 150
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#define MWDMA_MODE2_CYCLE_TIME 120
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#define UDMA_MODE0_CYCLE_TIME 120
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#define UDMA_MODE1_CYCLE_TIME 80
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#define UDMA_MODE2_CYCLE_TIME 60
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#define UDMA_MODE3_CYCLE_TIME 45
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#define UDMA_MODE4_CYCLE_TIME 30
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#define UDMA_MODE5_CYCLE_TIME 20
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typedef union _IDE_PATH_ID {
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struct {
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ULONG Lun:8;
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ULONG TargetId:8;
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ULONG Path:8;
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ULONG Reserved:8;
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} b;
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ULONG l;
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} IDE_PATH_ID, *PIDE_PATH_ID;
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typedef struct _IDE_REGISTERS_1 {
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PUCHAR RegistersBaseAddress;
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PUSHORT Data;
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PUCHAR Error;
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PUCHAR BlockCount;
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PUCHAR BlockNumber;
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PUCHAR CylinderLow;
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PUCHAR CylinderHigh;
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PUCHAR DriveSelect;
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PUCHAR Command;
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} IDE_REGISTERS_1, *PIDE_REGISTERS_1;
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typedef struct _IDE_REGISTERS_2 {
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PUCHAR RegistersBaseAddress;
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PUCHAR DeviceControl;
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PUCHAR DriveAddress;
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} IDE_REGISTERS_2, *PIDE_REGISTERS_2;
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//
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// device extension header
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//
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#define EXTENSION_COMMON_HEADER PDEVICE_OBJECT AttacheeDeviceObject; \
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PDEVICE_OBJECT AttacheePdo; \
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PDRIVER_OBJECT DriverObject; \
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PDEVICE_OBJECT DeviceObject; \
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ULONG PagingPathCount; /* keep track of page path */ \
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ULONG HiberPathCount; /* keep track of hiber path */ \
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ULONG CrashDumpPathCount; /* keep track of crashdump path */ \
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SYSTEM_POWER_STATE SystemPowerState; \
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DEVICE_POWER_STATE DevicePowerState; \
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WMILIB_CONTEXT WmiLibInfo; \
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PIRP PendingSystemPowerIrp; /* DEBUG */ \
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PIRP PendingDevicePowerIrp; /* DEBUG */ \
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PDRIVER_DISPATCH DefaultDispatch; \
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PDRIVER_DISPATCH *PnPDispatchTable; \
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PDRIVER_DISPATCH *PowerDispatchTable; \
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PDRIVER_DISPATCH *WmiDispatchTable
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typedef struct _DEVICE_EXTENSION_HEADER {
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EXTENSION_COMMON_HEADER;
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} DEVICE_EXTENSION_HEADER, * PDEVICE_EXTENSION_HEADER;
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typedef struct _PCIIDE_BUSMASTER_INTERFACE {
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ULONG Size;
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ULONG SupportedTransferMode[MAX_IDE_DEVICE * MAX_IDE_LINE];
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ULONG MaxTransferByteSize;
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PVOID Context;
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NTSTATUS
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(* BmSetup) (
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IN PVOID Context,
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IN PVOID DataVirtualAddress,
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IN ULONG TransferByteCount,
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IN PMDL Mdl,
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IN BOOLEAN DataIn,
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IN VOID (*BmCallback) (PVOID Context),
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IN PVOID CallbackContext
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);
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NTSTATUS
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(* BmArm) (
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IN PVOID Context
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);
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BMSTATUS
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(* BmDisarm) (
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IN PVOID Context
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);
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BMSTATUS
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(* BmFlush) (
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IN PVOID Context
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);
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BMSTATUS
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(* BmStatus) (
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IN PVOID Context
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);
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NTSTATUS
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(* BmTimingSetup) (
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IN PVOID Context
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);
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BOOLEAN IgnoreActiveBitForAtaDevice;
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BOOLEAN AlwaysClearBusMasterInterrupt;
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ULONG ContextSize;
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NTSTATUS
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(* BmSetupOnePage) (
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IN PVOID Context,
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IN PVOID DataVirtualPageAddress,
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IN ULONG TransferByteCount,
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IN PMDL Mdl,
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IN BOOLEAN DataIn,
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IN PVOID RegionDescriptorTablePage
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);
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NTSTATUS
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(* BmCrashDumpInitialize) (
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IN PVOID Context
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);
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NTSTATUS
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(* BmFlushAdapterBuffers) (
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IN PVOID Context,
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IN PVOID DataVirtualPageAddress,
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IN ULONG TransferByteCount,
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IN PMDL Mdl,
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IN BOOLEAN DataIn
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);
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} PCIIDE_BUSMASTER_INTERFACE, * PPCIIDE_BUSMASTER_INTERFACE;
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typedef struct _PCIIDE_SYNC_ACCESS_INTERFACE {
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VOID
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(*AllocateAccessToken) (
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PVOID Token,
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PDRIVER_CONTROL Callback,
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PVOID CallbackContext
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);
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VOID
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(*FreeAccessToken) (
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PVOID Token
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);
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PVOID Token;
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} PCIIDE_SYNC_ACCESS_INTERFACE, *PPCIIDE_SYNC_ACCESS_INTERFACE;
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typedef enum PCIIDE_XFER_MODE_SUPPORT_LEVEL {
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PciIdeBasicXferModeSupport,
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PciIdeFullXferModeSupport
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} PCIIDE_XFER_MODE_SUPPORT_LEVEL;
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typedef struct _PCIIDE_INTERRUPT_INTERFACE {
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NTSTATUS
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(*PciIdeInterruptControl) (
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PVOID Context,
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ULONG Disable
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);
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PVOID Context;
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} PCIIDE_INTERRUPT_INTERFACE, *PPCIIDE_INTERRUPT_INTERFACE;
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typedef struct _PCIIDE_XFER_MODE_INTERFACE {
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PCIIDE_XFER_MODE_SUPPORT_LEVEL SupportLevel;
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PVOID VendorSpecificDeviceExtension;
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NTSTATUS
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(*TransferModeSelect) (
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PVOID Context,
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PPCIIDE_TRANSFER_MODE_SELECT XferMode
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);
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ULONG
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(*UseDma) (
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PVOID deviceExtension,
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PVOID Cdbcmd,
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UCHAR targetId
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);
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PVOID Context;
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PULONG TransferModeTimingTable;
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ULONG TransferModeTableLength;
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NTSTATUS
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(*UdmaModesSupported) (
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IDENTIFY_DATA IdentifyData,
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PULONG BestXferMode,
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PULONG CurrentMode
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);
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} PCIIDE_XFER_MODE_INTERFACE, *PPCIIDE_XFER_MODE_INTERFACE;
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#define PCIIDE_PROGIF_MASTER_IDE (1 << 7)
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typedef IDE_CHANNEL_STATE
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(*PCIIDE_CHANNEL_ENABLED) (
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IN PVOID DeviceExtension,
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IN ULONG Channel
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);
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typedef BOOLEAN
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(*PCIIDE_SYNC_ACCESS_REQUIRED) (
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IN PVOID DeviceExtension
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);
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typedef NTSTATUS
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(*PCIIDE_TRANSFER_MODE_SELECT_FUNC) (
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IN PVOID DeviceExtension,
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IN OUT PPCIIDE_TRANSFER_MODE_SELECT TransferModeSelect
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);
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typedef VOID
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(*PCIIDE_REQUEST_PROPER_RESOURCES) (
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IN PDEVICE_OBJECT PhysicalDeviceObject
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);
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typedef
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NTSTATUS (*PCONTROLLER_PROPERTIES) (
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IN PVOID DeviceExtension,
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IN PIDE_CONTROLLER_PROPERTIES ControllerProperties
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);
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NTSTATUS
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PciIdeXInitialize(
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IN PDRIVER_OBJECT DriverObject,
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IN PUNICODE_STRING RegistryPath,
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IN PCONTROLLER_PROPERTIES PciIdeGetControllerProperties,
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IN ULONG ExtensionSize
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);
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NTSTATUS
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PciIdeXGetBusData(
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IN PVOID DeviceExtension,
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IN PVOID Buffer,
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IN ULONG ConfigDataOffset,
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IN ULONG BufferLength
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);
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NTSTATUS
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PciIdeXSetBusData(
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IN PVOID DeviceExtension,
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IN PVOID Buffer,
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IN PVOID DataMask,
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IN ULONG ConfigDataOffset,
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IN ULONG BufferLength
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);
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NTSTATUS
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PciIdeXSaveDeviceParameter (
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IN PVOID DeviceExtension,
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IN PWSTR ParameterName,
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IN ULONG ParameterValue
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);
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#if DBG
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#define IdePortWaitOnBusyEx(a,b,c) IdePortpWaitOnBusyEx (a,b,c,__FILE__,__LINE__)
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#else
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#define IdePortWaitOnBusyEx(a,b,c) IdePortpWaitOnBusyEx (a,b,c)
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#endif
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#ifdef DPC_FOR_EMPTY_CHANNEL
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#define IdePortWaitOnBusyExK(CmdRegBase, status, BadStatus) {\
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int ki; \
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for (ki=0; ki<20; ki++) {\
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GetStatus(CmdRegBase, status);\
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if (status == BadStatus) {\
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break;\
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} else if (status & IDE_STATUS_BUSY) {\
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KeStallExecutionProcessor(5);\
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continue;\
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} else {\
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break;\
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}\
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}\
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}
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#endif
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NTSTATUS
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IdePortpWaitOnBusyEx (
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IN PIDE_REGISTERS_1 CmdRegBase,
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IN OUT PUCHAR Status,
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IN UCHAR BadStatus
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#if DBG
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,
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IN PCSTR FileName,
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IN ULONG LineNumber
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#endif
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);
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VOID
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IdeCreateIdeDirectory(
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VOID
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);
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#define DEVICE_OJBECT_BASE_NAME L"\\Device\\Ide"
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#define MEMORY_SPACE 0
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#define IO_SPACE 1
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#define CLRMASK(x, mask) ((x) &= ~(mask));
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#define SETMASK(x, mask) ((x) |= (mask));
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#define IS_PDO(doExtension) (doExtension->AttacheeDeviceObject == NULL)
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#define IS_FDO(doExtension) (doExtension->AttacheeDeviceObject != NULL)
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/* 681190ea-e4ea-11d0-ab82-00a0c906962f */
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DEFINE_GUID(GUID_PCIIDE_BUSMASTER_INTERFACE, 0x681190ea, 0xe4ea, 0x11d0, 0xab, 0x82, 0x00, 0xa0, 0xc9, 0x06, 0x96, 0x2f);
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/* 681190eb-e4ea-11d0-ab82-00a0c906962f */
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DEFINE_GUID(GUID_PCIIDE_SYNC_ACCESS_INTERFACE, 0x681190eb, 0xe4ea, 0x11d0, 0xab, 0x82, 0x00, 0xa0, 0xc9, 0x06, 0x96, 0x2f);
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/* 681190ec-e4ea-11d0-ab82-00a0c906962f */
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DEFINE_GUID(GUID_PCIIDE_XFER_MODE_INTERFACE, 0x681190ec, 0xe4ea, 0x11d0, 0xab, 0x82, 0x00, 0xa0, 0xc9, 0x06, 0x96, 0x2f);
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/* 681190ed-e4ea-11d0-ab82-00a0c906962f */
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DEFINE_GUID(GUID_PCIIDE_REQUEST_PROPER_RESOURCES, 0x681190ed, 0xe4ea, 0x11d0, 0xab, 0x82, 0x00, 0xa0, 0xc9, 0x06, 0x96, 0x2f);
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/* 681190ee-e4ea-11d0-ab82-00a0c906962f */
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DEFINE_GUID(GUID_PCIIDE_INTERRUPT_INTERFACE, 0x681190ee, 0xe4ea, 0x11d0, 0xab, 0x82, 0x00, 0xa0, 0xc9, 0x06, 0x96, 0x2f);
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/* {14A001C6-F837-4157-BFC9-496F52C18998} */
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DEFINE_GUID(INTERFACENAME4, 0x14a001c6, 0xf837, 0x4157, 0xbf, 0xc9, 0x49, 0x6f, 0x52, 0xc1, 0x89, 0x98);
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#define max(a,b) (((a) > (b)) ? (a) : (b))
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#define min(a,b) (((a) < (b)) ? (a) : (b))
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#if !DBG
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#define DECLARE_EXTRA_DEBUG_PARAMETER(t, x)
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#else
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#define DECLARE_EXTRA_DEBUG_PARAMETER(t, x) ,t x
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#endif //DBG
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//
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// ATAPI Exports
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//
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BOOLEAN
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IdePortChannelEmpty (
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IN PIDE_REGISTERS_1 CmdRegBase,
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IN PIDE_REGISTERS_2 CtrlRegBase,
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IN ULONG MaxIdeDevice
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);
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#ifdef DPC_FOR_EMPTY_CHANNEL
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ULONG
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IdePortChannelEmptyQuick (
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IN PIDE_REGISTERS_1 CmdRegBase,
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IN PIDE_REGISTERS_2 CtrlRegBase,
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IN ULONG MaxIdeDevice,
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PULONG CurrentIdeDevice,
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PULONG MoreWait,
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PULONG NoRetry
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);
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#endif
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typedef struct _IDE_RESOURCE {
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ULONG CommandBaseAddressSpace;
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ULONG ControlBaseAddressSpace;
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PUCHAR TranslatedCommandBaseAddress;
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PUCHAR TranslatedControlBaseAddress;
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KINTERRUPT_MODE InterruptMode;
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ULONG InterruptLevel;
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//
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// Primary and Secondary at disk address (0x1f0 and 0x170) claimed.
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//
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BOOLEAN AtdiskPrimaryClaimed;
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BOOLEAN AtdiskSecondaryClaimed;
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} IDE_RESOURCE, *PIDE_RESOURCE;
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NTSTATUS
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DigestResourceList (
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IN OUT PIDE_RESOURCE IdeResource,
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IN PCM_RESOURCE_LIST ResourceList,
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OUT PCM_PARTIAL_RESOURCE_DESCRIPTOR *IrqPartialDescriptors
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);
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VOID
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AtapiBuildIoAddress (
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IN PUCHAR CmdBaseAddress,
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IN PUCHAR CtrlBaseAddress,
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OUT PIDE_REGISTERS_1 BaseIoAddress1,
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OUT PIDE_REGISTERS_2 BaseIoAddress2,
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OUT PULONG BaseIoAddress1Length,
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OUT PULONG BaseIoAddress2Length,
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OUT PULONG MaxIdeDevice,
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OUT PULONG MaxIdeTargetId
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);
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NTSTATUS
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IdeGetDeviceCapabilities(
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IN PDEVICE_OBJECT DeviceObject,
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IN PDEVICE_CAPABILITIES DeviceCapabilities
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);
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#if DBG
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static PUCHAR IdeDebugPnpIrpName[NUM_PNP_MINOR_FUNCTION] = {
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"IRP_MN_START_DEVICE",
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"IRP_MN_QUERY_REMOVE_DEVICE",
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"IRP_MN_REMOVE_DEVICE",
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"IRP_MN_CANCEL_REMOVE_DEVICE",
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"IRP_MN_STOP_DEVICE",
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"IRP_MN_QUERY_STOP_DEVICE",
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"IRP_MN_CANCEL_STOP_DEVICE",
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"IRP_MN_QUERY_DEVICE_RELATIONS",
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"IRP_MN_QUERY_INTERFACE",
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"IRP_MN_QUERY_CAPABILITIES",
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"IRP_MN_QUERY_RESOURCES",
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"IRP_MN_QUERY_RESOURCE_REQUIREMENTS",
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"IRP_MN_QUERY_DEVICE_TEXT",
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"IRP_MN_FILTER_RESOURCE_REQUIREMENTS",
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"an undefined PnP IRP",
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"IRP_MN_READ_CONFIG",
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"IRP_MN_WRITE_CONFIG",
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"IRP_MN_EJECT",
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"IRP_MN_SET_LOCK",
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"IRP_MN_QUERY_ID",
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"IRP_MN_QUERY_PNP_DEVICE_STATE",
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"IRP_MN_QUERY_BUS_INFORMATION",
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"IRP_MN_DEVICE_USAGE_NOTIFICATION",
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"IRP_MN_SURPRISE_REMOVAL",
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"IRP_MN_QUERY_LEGACY_BUS_INFORMATION"
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};
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static PUCHAR IdeDebugPowerIrpName[NUM_POWER_MINOR_FUNCTION] = {
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"IRP_MN_WAIT_WAKE",
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"IRP_MN_POWER_SEQUENCE",
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"IRP_MN_SET_POWER",
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"IRP_MN_QUERY_POWER"
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};
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static PUCHAR IdeDebugWmiIrpName[NUM_WMI_MINOR_FUNCTION] = {
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"IRP_MN_QUERY_ALL_DATA",
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"IRP_MN_QUERY_SINGLE_INSTANCE",
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"IRP_MN_CHANGE_SINGLE_INSTANCE",
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"IRP_MN_CHANGE_SINGLE_ITEM",
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"IRP_MN_ENABLE_EVENTS",
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"IRP_MN_DISABLE_EVENTS",
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"IRP_MN_ENABLE_COLLECTION",
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"IRP_MN_DISABLE_COLLECTION",
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"IRP_MN_REGINFO",
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"IRP_MN_EXECUTE_METHOD"
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};
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#endif
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#endif // ___idep_h___
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