1636 lines
64 KiB
C
1636 lines
64 KiB
C
/******************************Module*Header*******************************\
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* Module Name: hw.h
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*
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* All the hardware specific driver file stuff. Parts are mirrored in
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* 'hw.inc'.
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*
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* Copyright (c) 1992-1996 Microsoft Corporation
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* Copyright (c) 1993-1996 Matrox Electronic Systems, Ltd.
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\**************************************************************************/
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// The following is used to define the MGA memory map.
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// MGA map
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#define SrcWin 0x0000
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#define IntReg 0x1c00
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#define DstWin 0x2000
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#define ExtDev 0x3c00
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// Internal registers
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#define VgaReg 0x0000
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#define DwgReg 0x0000
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#define StartDwgReg 0x0100
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#define HstReg 0x0200
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// External devices
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#define RamDac 0x0000
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#define Dubic 0x0080
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#define Viwic 0x0100
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#define ClkGen 0x0180
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#define ExpDev 0x0200
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// TITAN registers
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#define DWGCTL 0x0000
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#define MACCESS 0x0004
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#define MCTLWTST 0x0008
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#define ZORG 0x000C
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#define DST0 0x0010
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#define DST1 0x0014
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#define ZMSK 0x0018
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#define PLNWT 0x001C
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#define BCOL 0x0020
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#define FCOL 0x0024
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#define SRCBLT 0x002C
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#define SRC0 0x0030
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#define SRC1 0x0034
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#define SRC2 0x0038
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#define SRC3 0x003C
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#define XYSTRT 0x0040
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#define XYEND 0x0044
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#define SHIFT 0x0050
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#define SGN 0x0058
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#define LEN 0x005C
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#define AR0 0x0060
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#define AR1 0x0064
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#define AR2 0x0068
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#define AR3 0x006C
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#define AR4 0x0070
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#define AR5 0x0074
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#define AR6 0x0078
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#define CXBNDRY 0x0080
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#define FXBNDRY 0x0084
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#define YDSTLEN 0x0088
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#define PITCH 0x008C
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#define YDST 0x0090
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#define YDSTORG 0x0094
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#define CYTOP 0x0098
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#define CYBOT 0x009C
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#define CXLEFT 0x00A0
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#define CXRIGHT 0x00A4
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#define FXLEFT 0x00A8
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#define FXRIGHT 0x00AC
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#define XDST 0x00B0
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#define DR0 0x00C0
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#define DR1 0x00C4
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#define DR2 0x00C8
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#define DR3 0x00CC
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#define DR4 0x00D0
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#define DR5 0x00D4
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#define DR6 0x00D8
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#define DR7 0x00DC
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#define DR8 0x00E0
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#define DR9 0x00E4
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#define DR10 0x00E8
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#define DR11 0x00EC
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#define DR12 0x00F0
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#define DR13 0x00F4
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#define DR14 0x00F8
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#define DR15 0x00FC
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// VGA registers
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#define CRTC_INDEX 0x03D4
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#define CRTC_DATA 0x03D5
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#define CRTCEXT_INDEX 0x03DE
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#define CRTCEXT_DATA 0x03DF
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#define INSTS1 0x03DA
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// Host registers
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#define SRCPAGE 0x0000
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#define DSTPAGE 0x0004
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#define BYTACCDATA 0x0008
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#define ADRGEN 0x000C
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#define FIFOSTATUS 0x0010
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#define STATUS 0x0014
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#define ICLEAR 0x0018
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#define IEN 0x001C
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#define RST 0x0040
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#define TEST 0x0044
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#define REV 0x0048
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#define CONFIG_REG 0x0050
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#define OPMODE 0x0054
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#define CRTC_CTRL 0x005C
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#define VCOUNT 0x0020
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// Bt485
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#define BT485_PAL_OR_CURS_RAM_WRITE 0x0000
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#define BT485_COLOR_PAL_DATA 0x0004
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#define BT485_PIXEL_MASK 0x0008
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#define BT485_PAL_OR_CURS_RAM_READ 0x000C
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#define BT485_OVS_OR_CURS_COLOR_WRITE 0x0010
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#define BT485_OVS_OR_CURS_COLOR_DATA 0x0014
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#define BT485_COMMAND_0 0x0018
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#define BT485_OVS_OR_CURS_COLOR_READ 0x001C
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#define BT485_COMMAND_1 0x0020
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#define BT485_COMMAND_2 0x0024
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#define BT485_COMMAND_3_OR_STATUS 0x0028
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#define BT485_CURS_RAM_ARRAY 0x002C
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#define BT485_CURS_X_LOW 0x0030
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#define BT485_CURS_X_HIGH 0x0034
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#define BT485_CURS_Y_LOW 0x0038
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#define BT485_CURS_Y_HIGH 0x003C
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// Bt482
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#define BT482_PAL_OR_CURS_RAM_WRITE 0x0000
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#define BT482_COLOR_PAL_DATA 0x0004
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#define BT482_PIXEL_MASK 0x0008
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#define BT482_PAL_OR_CURS_RAM_READ 0x000C
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#define BT482_OVS_OR_CURS_COLOR_WRITE 0x0010
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#define BT482_OVS_OR_CURS_COLOR_DATA 0x0014
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#define BT482_COMMAND_A 0x0018
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#define BT482_OVS_OR_CURS_COLOR_READ 0x001C
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// ViewPoint
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#define VPOINT_PAL_ADDR_WRITE 0x0000
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#define VPOINT_PAL_COLOR 0x0004
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#define VPOINT_PIX_READ_MASK 0x0008
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#define VPOINT_PAL_ADDR_READ 0x000c
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#define VPOINT_RESERVED_4 0x0010
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#define VPOINT_RESERVED_5 0x0014
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#define VPOINT_INDEX 0x0018
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#define VPOINT_DATA 0x001c
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// Dubic
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#define DUB_SEL 0x0080
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#define NDX_PTR 0x0081
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#define DUB_DATA 0x0082
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#define LASER 0x0083
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#define MOUSE0 0x0084
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#define MOUSE1 0x0085
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#define MOUSE2 0x0086
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#define MOUSE3 0x0087
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// Index within NDX_PTR to access the following registers through DUB_DATA
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#define DUB_CTL 0x00
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#define KEY_COL 0x01
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#define KEY_MSK 0x02
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#define DBX_MIN 0x03
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#define DBX_MAX 0x04
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#define DBY_MIN 0x05
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#define DBY_MAX 0x06
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#define OVS_COL 0x07
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#define CUR_X 0x08
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#define CUR_Y 0x09
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#define DUB_CTL2 0x0A
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#define DUB_UnDef 0x0B
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#define CUR_COL0 0x0C
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#define CUR_COL1 0x0D
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#define CRC_CTL 0x0E
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#define CRC_DAT 0x0F
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// **************************************************************************
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// Titan registers: fields definitions
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// DWGCTRL - Drawing Control Register
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#define opcode_LINE_OPEN 0x00000000
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#define opcode_AUTOLINE_OPEN 0x00000001
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#define opcode_LINE_CLOSE 0x00000002
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#define opcode_AUTOLINE_CLOSE 0x00000003
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#define opcode_AUTO 0x00000001
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#define opcode_TRAP 0x00000004
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#define opcode_TEXTURE_TRAP 0x00000005
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#define opcode_RESERVED_1 0x00000006
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#define opcode_RESERVED_2 0x00000007
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#define opcode_BITBLT 0x00000008
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#define opcode_ILOAD 0x00000009
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#define opcode_IDUMP 0x0000000a
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#define opcode_RESERVED_3 0x0000000b
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#define opcode_FBITBLT 0x0000000c
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#define opcode_ILOAD_SCALE 0x0000000d
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#define opcode_RESERVED_4 0x0000000e
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#define opcode_ILOAD_FILTER 0x0000000f
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#define atype_RPL 0x00000000
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#define atype_RSTR 0x00000010
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#define atype_ANTI 0x00000020
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#define atype_ZI 0x00000030
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#define atype_I 0x00000070
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#define blockm_ON 0x00000040
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#define blockm_OFF 0x00000000
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#define linear_XY_BITBLT 0x00000000
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#define linear_LINEAR_BITBLT 0x00000080
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#define zmode_NOZCMP 0x00000000
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#define zmode_RESERVED_1 0x00000100
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#define zmode_ZE 0x00000200
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#define zmode_ZNE 0x00000300
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#define zmode_ZLT 0x00000400
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#define zmode_ZLTE 0x00000500
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#define zmode_ZGT 0x00000600
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#define zmode_ZGTE 0x00000700
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#define solid_NO_SOLID 0x00000000
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#define solid_SOLID 0x00000800
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#define arzero_NO_ZERO 0x00000000
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#define arzero_ZERO 0x00001000
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#define sgnzero_NO_ZERO 0x00000000
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#define sgnzero_ZERO 0x00002000
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#define shftzero_NO_ZERO 0x00000000
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#define shftzero_ZERO 0x00004000
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#define bop_BLACK 0x00000000 // 0 0
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#define bop_BLACKNESS 0x00000000 // 0 0
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#define bop_NOTMERGEPEN 0x00010000 // DPon ~(D | S)
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#define bop_MASKNOTPEN 0x00020000 // DPna D & ~S
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#define bop_NOTCOPYPEN 0x00030000 // Pn ~S
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#define bop_MASKPENNOT 0x00040000 // PDna (~D) & S
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#define bop_NOT 0x00050000 // Dn ~D
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#define bop_XORPEN 0x00060000 // DPx D ^ S
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#define bop_NOTMASKPEN 0x00070000 // DPan ~(D & S)
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#define bop_MASKPEN 0x00080000 // DPa D & S
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#define bop_NOTXORPEN 0x00090000 // DPxn ~(D ^ S)
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#define bop_NOP 0x000a0000 // D D
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#define bop_MERGENOTPEN 0x000b0000 // DPno D | ~S
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#define bop_COPYPEN 0x000c0000 // P S
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#define bop_SRCCOPY 0x000c0000 // P S
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#define bop_MERGEPENNOT 0x000d0000 // PDno (~D)| S
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#define bop_MERGEPEN 0x000e0000 // DPo D | S
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#define bop_MASK 0x000f0000
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#define bop_WHITE 0x000f0000 // 1 1
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#define bop_WHITENESS 0x000f0000 // 1 1
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#define trans_0 0x00000000
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#define trans_1 0x00100000
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#define trans_2 0x00200000
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#define trans_3 0x00300000
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#define trans_4 0x00400000
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#define trans_5 0x00500000
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#define trans_6 0x00600000
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#define trans_7 0x00700000
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#define trans_8 0x00800000
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#define trans_9 0x00900000
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#define trans_10 0x00a00000
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#define trans_11 0x00b00000
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#define trans_12 0x00c00000
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#define trans_13 0x00d00000
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#define trans_14 0x00e00000
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#define trans_15 0x00f00000
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#define alphadit_FOREGROUND 0x00000000
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#define alphadit_RED 0x01000000
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#define bltmod_BMONO 0x00000000
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#define bltmod_BPLAN 0x02000000
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#define bltmod_BFCOL 0x04000000
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#define bltmod_BUCOL 0x06000000
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#define bltmod_BU32BGR 0x06000000
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#define bltmod_BMONOWF 0x08000000
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#define bltmod_BU32RGB 0x0e000000
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#define bltmod_BU24BGR 0x16000000
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#define bltmod_BU24RGB 0x1e000000
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#define bltmod_BUYUV 0x1c000000
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#define zdrwen_NO_DEPTH 0x00000000
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#define zdrwen_DEPTH 0x02000000
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#define zlte_LESS_THEN 0x00000000
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#define zlte_LESS_THEN_OR_EQUAL 0x04000000
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#define afor_DATA_ALU 0x00000000
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#define afor_FORE_COL 0x08000000
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#define hbgr_SRC_RGB 0x00000000
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#define hbgr_SRC_BGR 0x08000000
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#define hbgr_SRC_EG3 0x00000000
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#define hbgr_SRC_WINDOWS 0x08000000
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#define abac_OLD_DATA 0x00000000
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#define abac_BG_COLOR 0x10000000
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#define hcprs_SRC_32_BPP 0x00000000
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#define hcprs_SRC_24_BPP 0x10000000
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#define pattern_OFF 0x00000000
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#define pattern_ON 0x20000000
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#define transc_BIT 30 // bit #30
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#define transc_BG_OPAQUE 0x00000000
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#define transc_BG_TRANSP 0x40000000
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// MACCESS - Memory Access Register
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#define pwidth_PW8 0x00000000
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#define pwidth_PW16 0x00000001
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#define pwidth_PW32 0x00000002
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#define pwidth_PW24 0x00000003
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#define dither_DISABLE 0x40000000
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#define dither_555 0x80000000
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#define dither_565 0x00000000
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#define fbc_SBUF 0x00000000
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#define fbc_RESERVED 0x00000004
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#define fbc_DBUFA 0x00000008
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#define fbc_DBUFB 0x0000000c
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// MCTLWTST - Memory Control Wait State Register
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// DST0, DST1 - Destination in Register
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// ZMASK - Z Mask Control Register
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// PLNWT - Plane Write Mask
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#define plnwt_MASK_8BPP 0xffffffff
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#define plnwt_MASK_15BPP 0x7fff7fff
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#define plnwt_MASK_16BPP 0xffffffff
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#define plnwt_MASK_24BPP 0xffffffff
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#define plnwt_MASK_32BPP 0xffffffff
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#define plnwt_ALL 0xffffffff
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#define plnwt_FREE 0xff000000
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#define plnwt_RED 0x00ff0000
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#define plnwt_GREEN 0x0000ff00
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#define plnwt_BLUE 0x000000ff
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// BCOL - Background Color
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// FCOL - ForeGround Color
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// SRCBLT - Source Register for Blit
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// SRC0, SRC1, SRC2, SRC3 - Source Register
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// XYSTART - X Y Start Address
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// XYEND - X Y End Address
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// SHIFT - Funnel Shifter Control Register
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#define funoff_MASK 0xffc0ffff
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#define funoff_RED_TO_FREE 0x00380000 // -8
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#define funoff_GREEN_TO_FREE 0x00300000 // -16
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#define funoff_BLUE_TO_FREE 0x00280000 // -24
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#define funoff_FREE_TO_RED 0x00080000 // 8
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#define funoff_FREE_TO_GREEN 0x00100000 // 16
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#define funoff_FREE_TO_BLUE 0x00180000 // 24
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#define funoff_X_TO_FREE_STEP 0x00080000
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#define funoff_FREE_TO_X_STEP 0x00080000
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// SGN - Sign Register
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#define sdydxl_MAJOR_Y 0x00000000
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#define sdydxl_MAJOR_X 0x00000001
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#define scanleft_LEFT 0x00000001
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#define scanleft_RIGHT 0x00000000
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#define sdxl_ADD 0x00000000
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#define sdxl_SUB 0x00000002
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#define sdy_ADD 0x00000000
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#define sdy_SUB 0x00000004
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#define sdxr_INC 0x00000000
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#define sdxr_DEC 0x00000020
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#define scanleft_LEFT_TO_RIGHT 0x00000000
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#define scanleft_RIGHT_TO_LEFT 0x00000001
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#define sdy_TOP_TO_BOTTOM 0x00000000
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#define sdy_BOTTOM_TO_TOP 0x00000004
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#define DRAWING_DIR_TBLR sdy_TOP_TO_BOTTOM+scanleft_RIGHT // 0x00
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#define DRAWING_DIR_TBRL sdy_TOP_TO_BOTTOM+scanleft_LEFT // 0x01
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#define DRAWING_DIR_BTLR sdy_BOTTOM_TO_TOP+scanleft_RIGHT // 0x04
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#define DRAWING_DIR_BTRL sdy_BOTTOM_TO_TOP+scanleft_LEFT // 0x05
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// LEN - length register
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// AR0
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#define ARX_BIT_MASK 0x0001ffff
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// AR1
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// AR2
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// AR3
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// AR4
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// AR5
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// AR6
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// CXBNDRY
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#define bcxleft_MASK 0x000007ff
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#define bcxleft_SHIFT 0
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#define bcxright_MASK 0x07ff0000
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#define bcxright_SHIFT 16
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// FXBNDRY
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#define bfxleft_MASK 0x0000ffff
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#define bfxleft_SHIFT 0
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#define bfxright_MASK 0xffff0000
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#define bfxright_SHIFT 16
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// YDSTLEN
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#define ylength_MASK 0x0000ffff
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#define ylength_SHIFT 0
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#define yval_MASK 0xffff0000
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#define yval_SHIFT 16
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// PITCH - Memory Pitch
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#define iy_512 0x00000200
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#define iy_640 0x00000280
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#define iy_768 0x00000300
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#define iy_800 0x00000320
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#define iy_1024 0x00000400
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#define iy_1152 0x00000480
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#define iy_1280 0x00000500
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#define iy_1536 0x00000600
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#define iy_1600 0x00000640
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#define ylin_LINEARIZE 0x00000000
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#define ylin_LINEARIZE_NOT 0x00008000
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#define iy_MASK 0x00001fe0
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// YDST - Y Address Register
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// YDSTORG - memory origin register
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// YTOP - Clipper Y Top Boundary
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// YBOT - Clipper Y Bottom Boundary
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// CXLEFT - Clipper X Minimum Boundary
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// CXRIGHT - Clipper X Maximum Boundary
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// FXLEFT - X Address Register (Left)
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// FXRIGHT - X Address Register (Right)
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// XDST - X Destination Address Register
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// DR0
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// DR1
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// DR2
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// DR3
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// DR4
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// DR5
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// DR6
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// DR7
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// DR8
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// DR9
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// DR10
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// DR11
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// DR12
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// DR13
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// DR14
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// DR15
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// **************************************************************************
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// Host registers: fields definitions
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// SRCPAGE - Source Page Register
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// DSTPAGE - Destination Page Register
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// BYTEACCDATA - Byte Accumulator Data
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// ADRGEN - Address Generator Register
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// FIFOSTATUS - Bus FIFO Status Register
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#define fifocount_MASK 0x0000007f
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#define bfull_MASK 0x00000100
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#define bempty_MASK 0x00000200
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#define byteaccaddr_MASK 0x007f0000
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#define addrgenstate_MASK 0x3f000000
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// STATUS - Status Register
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#define bferrists_MASK 0x00000001
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#define dmatcists_MASK 0x00000002
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#define pickists_MASK 0x00000004
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#define vsyncsts_MASK 0x00000008
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#define byteflag_MASK 0x00000f00
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#define dwgengsts_MASK 0x00010000
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// ICLEAR - Interrupt Clear Register
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#define bferriclr_OFF 0x00000000
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#define bferriclr_ON 0x00000001
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#define dmactciclr_OFF 0x00000000
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#define dmactciclr_ON 0x00000002
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#define pickiclr_OFF 0x00000000
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#define pickiclr_ON 0x00000004
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// IEN - Interrupt Enable Register
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#define bferrien_OFF 0x00000000
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#define bferrien_ON 0x00000001
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#define dmactien_OFF 0x00000000
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#define dmactien_ON 0x00000002
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#define pickien_OFF 0x00000000
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#define pickien_ON 0x00000004
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#define vsyncien_OFF 0x00000000
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#define vsyncien_ON 0x00000008
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// RST - Reset Register
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#define softreset 0x00000001
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// TEST - Test Register
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#define vgatest 0x00000001
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#define robitwren 0x00000100
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// REV - Revision Register
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// CONFIG_REG - Configuration Register
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// OPMODE - Operating Mode Register
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#define OPMODE_OTHER_INFO 0xfffffff0
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#define pseudodma_OFF 0x00000000
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#define pseudodma_ON 0x00000001
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#define dmaact_OFF 0x00000000
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#define dmaact_ON 0x00000002
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#define dmamod_GENERAL_PURPOSE 0x00000000
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#define dmamod_BLIT_WRITE 0x00000004
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#define dmamod_VECTOR_WRITE 0x00000008
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#define dmamod_BLIT_READ 0x0000000c
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// CRTC_CTRL - CRTC Control
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// VCOUNT - VCOUNT Register
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// COLOR PATTERN
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#define PATTERN_PITCH 32
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#define PATTERN_PITCH_SHIFT 5
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// DMA
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#define DMAWINSIZE 7*1024 / 4 // 7k in DWORDS
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// FIFO
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#define FIFOSIZE 32
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#define INTEL_PAGESIZE 4*1024 // 4k bytes per page
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#define INTEL_PAGESIZE_DW 4*1024/4 // 1k dwords per page
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// Accelerator flags
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#define NO_CACHE 0
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#define SIGN_CACHE 1 // 1 is also the nb of registers affected
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#define ARX_CACHE 2
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#define PATTERN_CACHE 4 // 4 is also the nb of registers affected
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#define GET_CACHE_FLAGS(ppdev,fl) (ppdev->HopeFlags & (fl))
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// MGA Rop definitions
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#define MGA_BLACKNESS 0x0000 // 0 0
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#define MGA_NOTMERGEPEN 0x0001 // DPon ~(D | S)
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#define MGA_MASKNOTPEN 0x0002 // DPna D & ~S
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#define MGA_NOTCOPYPEN 0x0003 // Pn ~S
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#define MGA_MASKPENNOT 0x0004 // PDna (~D) & S
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#define MGA_NOT 0x0005 // Dn ~D
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#define MGA_XORPEN 0x0006 // DPx D ^ S
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#define MGA_NOTMASKPEN 0x0007 // DPan ~(D & S)
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#define MGA_MASKPEN 0x0008 // DPa D & S
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#define MGA_NOTXORPEN 0x0009 // DPxn ~(D ^ S)
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#define MGA_NOP 0x000a // D D
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#define MGA_MERGENOTPEN 0x000b // DPno D | ~S
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#define MGA_SRCCOPY 0x000c // P S
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#define MGA_MERGEPENNOT 0x000d // PDno (~D)| S
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#define MGA_MERGEPEN 0x000e // DPo D | S
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#define MGA_WHITENESS 0x000f // 1 1
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// Special MCTLWTST value for IDUMPs
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#define IDUMP_MCTLWTST 0xc4001000
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// **************************************************************************
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// Explicit register offsets.
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#define DMAWND SrcWin
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#define SRCWND SrcWin
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#define DSTWND DstWin
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#define DWG_DWGCTL IntReg+DwgReg+DWGCTL
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#define DWG_MACCESS IntReg+DwgReg+MACCESS
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#define DWG_MCTLWTST IntReg+DwgReg+MCTLWTST
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#define DWG_ZORG IntReg+DwgReg+ZORG
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#define DWG_DST0 IntReg+DwgReg+DST0
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#define DWG_DST1 IntReg+DwgReg+DST1
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#define DWG_ZMSK IntReg+DwgReg+ZMSK
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#define DWG_PLNWT IntReg+DwgReg+PLNWT
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#define DWG_BCOL IntReg+DwgReg+BCOL
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#define DWG_FCOL IntReg+DwgReg+FCOL
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#define DWG_SRCBLT IntReg+DwgReg+SRCBLT
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#define DWG_SRC0 IntReg+DwgReg+SRC0
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#define DWG_SRC1 IntReg+DwgReg+SRC1
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#define DWG_SRC2 IntReg+DwgReg+SRC2
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#define DWG_SRC3 IntReg+DwgReg+SRC3
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#define DWG_XYSTRT IntReg+DwgReg+XYSTRT
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#define DWG_XYEND IntReg+DwgReg+XYEND
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#define DWG_SHIFT IntReg+DwgReg+SHIFT
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#define DWG_SGN IntReg+DwgReg+SGN
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#define DWG_LEN IntReg+DwgReg+LEN
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#define DWG_AR0 IntReg+DwgReg+AR0
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#define DWG_AR1 IntReg+DwgReg+AR1
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#define DWG_AR2 IntReg+DwgReg+AR2
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#define DWG_AR3 IntReg+DwgReg+AR3
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#define DWG_AR4 IntReg+DwgReg+AR4
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#define DWG_AR5 IntReg+DwgReg+AR5
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#define DWG_AR6 IntReg+DwgReg+AR6
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#define DWG_PITCH IntReg+DwgReg+PITCH
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#define DWG_YDST IntReg+DwgReg+YDST
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#define DWG_YDSTLEN IntReg+DwgReg+YDSTLEN
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#define DWG_YDSTORG IntReg+DwgReg+YDSTORG
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#define DWG_CYTOP IntReg+DwgReg+CYTOP
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#define DWG_CYBOT IntReg+DwgReg+CYBOT
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#define DWG_CXBNDRY IntReg+DwgReg+CXBNDRY
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#define DWG_CXLEFT IntReg+DwgReg+CXLEFT
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#define DWG_CXRIGHT IntReg+DwgReg+CXRIGHT
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#define DWG_FXBNDRY IntReg+DwgReg+FXBNDRY
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#define DWG_FXLEFT IntReg+DwgReg+FXLEFT
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#define DWG_FXRIGHT IntReg+DwgReg+FXRIGHT
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#define DWG_XDST IntReg+DwgReg+XDST
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#define DWG_DR0 IntReg+DwgReg+DR0
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#define DWG_DR1 IntReg+DwgReg+DR1
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#define DWG_DR2 IntReg+DwgReg+DR2
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#define DWG_DR3 IntReg+DwgReg+DR3
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#define DWG_DR4 IntReg+DwgReg+DR4
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#define DWG_DR5 IntReg+DwgReg+DR5
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#define DWG_DR6 IntReg+DwgReg+DR6
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#define DWG_DR7 IntReg+DwgReg+DR7
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#define DWG_DR8 IntReg+DwgReg+DR8
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#define DWG_DR9 IntReg+DwgReg+DR9
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#define DWG_DR10 IntReg+DwgReg+DR10
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#define DWG_DR11 IntReg+DwgReg+DR11
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#define DWG_DR12 IntReg+DwgReg+DR12
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#define DWG_DR13 IntReg+DwgReg+DR13
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#define DWG_DR14 IntReg+DwgReg+DR14
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#define DWG_DR15 IntReg+DwgReg+DR15
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#define HST_SRCPAGE IntReg+HstReg+SRCPAGE
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#define HST_DSTPAGE IntReg+HstReg+DSTPAGE
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#define HST_BYTACCDATA IntReg+HstReg+BYTACCDATA
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#define HST_ADRGEN IntReg+HstReg+ADRGEN
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#define HST_FIFOSTATUS IntReg+HstReg+FIFOSTATUS
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#define HST_STATUS IntReg+HstReg+STATUS
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#define HST_ICLEAR IntReg+HstReg+ICLEAR
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#define HST_IEN IntReg+HstReg+IEN
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#define HST_RST IntReg+HstReg+RST
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#define HST_TEST IntReg+HstReg+TEST
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#define HST_REV IntReg+HstReg+REV
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#define HST_CONFIG_REG IntReg+HstReg+CONFIG_REG
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#define HST_OPMODE IntReg+HstReg+OPMODE
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#define HST_CRTC_CTRL IntReg+HstReg+CRTC_CTRL
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#define HST_VCOUNT IntReg+HstReg+VCOUNT
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#define VGA_CRTC_INDEX IntReg+VgaReg+CRTC_INDEX
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#define VGA_CRTC_DATA IntReg+VgaReg+CRTC_DATA
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#define VGA_CRTCEXT_INDEX IntReg+VgaReg+CRTCEXT_INDEX
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#define VGA_CRTCEXT_DATA IntReg+VgaReg+CRTCEXT_DATA
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#define VGA_INSTS1 IntReg+VgaReg+INSTS1
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#define BT485_PALETTE_RAM_WRITE ExtDev+RamDac+BT485_PAL_OR_CURS_RAM_WRITE
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#define BT485_CURSOR_RAM_WRITE ExtDev+RamDac+BT485_PAL_OR_CURS_RAM_WRITE
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#define BT485_PALETTE_DATA ExtDev+RamDac+BT485_COLOR_PAL_DATA
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#define BT485_PEL_MASK ExtDev+RamDac+BT485_PIXEL_MASK
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#define BT485_PALETTE_RAM_READ ExtDev+RamDac+BT485_PAL_OR_CURS_RAM_READ
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#define BT485_CURSOR_RAM_READ ExtDev+RamDac+BT485_PAL_OR_CURS_RAM_READ
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#define BT485_CURSOR_COLOR_WRITE ExtDev+RamDac+BT485_OVS_OR_CURS_COLOR_WRITE
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#define BT485_OVSCAN_COLOR_WRITE ExtDev+RamDac+BT485_OVS_OR_CURS_COLOR_WRITE
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#define BT485_CURSOR_COLOR_DATA ExtDev+RamDac+BT485_OVS_OR_CURS_COLOR_DATA
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#define BT485_OVSCAN_COLOR_DATA ExtDev+RamDac+BT485_OVS_OR_CURS_COLOR_DATA
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#define BT485_COMMAND_REG0 ExtDev+RamDac+BT485_COMMAND_0
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#define BT485_CURSOR_COLOR_READ ExtDev+RamDac+BT485_OVS_OR_CURS_COLOR_READ
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#define BT485_OVSCAN_COLOR_READ ExtDev+RamDac+BT485_OVS_OR_CURS_COLOR_READ
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#define BT485_COMMAND_REG1 ExtDev+RamDac+BT485_COMMAND_1
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#define BT485_COMMAND_REG2 ExtDev+RamDac+BT485_COMMAND_2
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#define BT485_COMMAND_REG3 ExtDev+RamDac+BT485_COMMAND_3_OR_STATUS
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#define BT485_STATUS ExtDev+RamDac+BT485_COMMAND_3_OR_STATUS
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#define BT485_CURSOR_RAM_DATA ExtDev+RamDac+BT485_CURS_RAM_ARRAY
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#define BT485_CURSOR_X_LOW ExtDev+RamDac+BT485_CURS_X_LOW
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#define BT485_CURSOR_X_HIGH ExtDev+RamDac+BT485_CURS_X_HIGH
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#define BT485_CURSOR_Y_LOW ExtDev+RamDac+BT485_CURS_Y_LOW
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#define BT485_CURSOR_Y_HIGH ExtDev+RamDac+BT485_CURS_Y_HIGH
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#define BT482_PALETTE_RAM_WRITE ExtDev+RamDac+BT482_PAL_OR_CURS_RAM_WRITE
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#define BT482_CURSOR_RAM_WRITE ExtDev+RamDac+BT482_PAL_OR_CURS_RAM_WRITE
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#define BT482_PALETTE_DATA ExtDev+RamDac+BT482_COLOR_PAL_DATA
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#define BT482_PEL_MASK ExtDev+RamDac+BT482_PIXEL_MASK
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#define BT482_PALETTE_RAM_READ ExtDev+RamDac+BT482_PAL_OR_CURS_RAM_READ
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#define BT482_CURSOR_RAM_READ ExtDev+RamDac+BT482_PAL_OR_CURS_RAM_READ
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#define BT482_CURSOR_COLOR_WRITE ExtDev+RamDac+BT482_OVS_OR_CURS_COLOR_WRITE
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#define BT482_OVRLAY_COLOR_WRITE ExtDev+RamDac+BT482_OVS_OR_CURS_COLOR_WRITE
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#define BT482_OVRLAY_REGS ExtDev+RamDac+BT482_OVS_OR_CURS_COLOR_DATA
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#define BT482_COMMAND_REGA ExtDev+RamDac+BT482_COMMAND_A
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#define BT482_CURSOR_COLOR_READ ExtDev+RamDac+BT482_OVS_OR_CURS_COLOR_READ
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#define BT482_OVRLAY_COLOR_READ ExtDev+RamDac+BT482_OVS_OR_CURS_COLOR_READ
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#define VIEWPOINT_PAL_ADDR_WRITE ExtDev+RamDac+VPOINT_PAL_ADDR_WRITE
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#define VIEWPOINT_PAL_COLOR ExtDev+RamDac+VPOINT_PAL_COLOR
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#define VIEWPOINT_PIX_READ_MASK ExtDev+RamDac+VPOINT_PIX_READ_MASK
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#define VIEWPOINT_PAL_ADDR_READ ExtDev+RamDac+VPOINT_PAL_ADDR_READ
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#define VIEWPOINT_RESERVED_4 ExtDev+RamDac+VPOINT_RESERVED_4
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#define VIEWPOINT_RESERVED_5 ExtDev+RamDac+VPOINT_RESERVED_5
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#define VIEWPOINT_INDEX ExtDev+RamDac+VPOINT_INDEX
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#define VIEWPOINT_DATA ExtDev+RamDac+VPOINT_DATA
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#define DUBIC_DUB_SEL ExtDev+Dubic+DUB_SEL
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#define DUBIC_NDX_PTR ExtDev+Dubic+NDX_PTR
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#define DUBIC_DUB_DATA ExtDev+Dubic+DUB_DATA
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#define DUBIC_LASER ExtDev+Dubic+LASER
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#define DUBIC_MOUSE0 ExtDev+Dubic+MOUSE0
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#define DUBIC_MOUSE1 ExtDev+Dubic+MOUSE1
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#define DUBIC_MOUSE2 ExtDev+Dubic+MOUSE2
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#define DUBIC_MOUSE3 ExtDev+Dubic+MOUSE3
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// **************************************************************************
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// RAMDAC registers fields
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// Bt482 --------------------------------------------------------------------
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// Extended registers
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#define READ_MASK_REG 0x00
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#define OVERLAY_MASK_REG 0x01
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#define COMMAND_B_REG 0x02
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#define CURS_REG 0x03
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#define CURS_X_LOW_REG 0x04
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#define CURS_X_HIGH_REG 0x05
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#define CURS_Y_LOW_REG 0x06
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#define CURS_Y_HIGH_REG 0x07
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// COMMAND_A
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#define BT482_PSEUDO_COLOR 0x00
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#define BT482_DUAL_EDGE_CLOCK_555 0x80
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#define BT482_DUAL_EDGE_CLOCK_565 0xc0
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#define BT482_SINGLE_EDGE_CLOCK_555 0xa0
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#define BT482_SINGLE_EDGE_CLOCK_565 0xe0
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#define BT482_DUAL_EDGE_CLOCK_888OL 0x90
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#define BT482_SINGLE_EDGE_CLOCK_888 0xF0
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#define BT482_EXTENDED_REG_SELECT 0x01
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#define BT482_EXTENDED_REG_UNSELECT 0x00
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// COMMAND_B_REG
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#define BT482_OVERLAY_REG_DISABLED 0x00
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#define BT482_OVERLAY_REG_ENABLED 0x40
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#define BT482_SETUP_00_IRE 0x00
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#define BT482_SETUP_75_IRE 0x20
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#define BT482_NO_SYNC_ON_BLUE 0x00
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#define BT482_SYNC_ON_BLUE 0x10
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#define BT482_NO_SYNC_ON_GREEN 0x00
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#define BT482_SYNC_ON_GREEN 0x08
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#define BT482_NO_SYNC_ON_RED 0x00
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#define BT482_SYNC_ON_RED 0x04
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#define BT482_COLOR_6_BIT 0x00
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#define BT482_COLOR_8_BIT 0x02
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#define BT482_SLEEP_UNSELECT 0x00
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#define BT482_SLEEP_SELECT 0x01
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// CURSOR_REG
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#define BT482_INTERNAL_CURSOR 0x00
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#define BT482_EXTERNAL_CURSOR 0x20
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#define BT482_NONINTERLACED_DISPLAY 0x00
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#define BT482_INTERLACED_DISPLAY 0x10
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#define BT482_CURSOR_COLOR_PALETTE_SELECT 0x00
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#define BT482_CURSOR_RAM_SELECT 0x08
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#define BT482_CURSOR_OP_ENABLED 0x00
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#define BT482_CURSOR_OP_DISABLED 0x04
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#define BT482_CURSOR_FIELDS 0x03
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#define BT482_CURSOR_DISABLED 0x00
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#define BT482_CURSOR_3_COLOR 0x01
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#define BT482_CURSOR_WINDOWS 0x02
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#define BT482_CURSOR_XWINDOWS 0x03
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// Bt485 --------------------------------------------------------------------
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// COMMAND_0
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#define BT485_REG3_UNSELECT 0x00
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#define BT485_REG3_SELECT 0x80
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#define BT485_INT_CLOCK_ENABLED 0x00
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#define BT485_INT_CLOCK_DISABLED 0x40
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#define BT485_SETUP_00_IRE 0x00
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#define BT485_SETUP_75_IRE 0x20
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#define BT485_NO_SYNC_ON_BLUE 0x00
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#define BT485_SYNC_ON_BLUE 0x10
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#define BT485_NO_SYNC_ON_GREEN 0x00
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#define BT485_SYNC_ON_GREEN 0x08
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#define BT485_NO_SYNC_ON_RED 0x00
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#define BT485_SYNC_ON_RED 0x04
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#define BT485_COLOR_6_BIT 0x00
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#define BT485_COLOR_8_BIT 0x02
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#define BT485_SLEEP_UNSELECT 0x00
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#define BT485_SLEEP_SELECT 0x01
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// COMMAND_1
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#define BT485_24BPP 0x00
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#define BT485_16BPP 0x20
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#define BT485_8BPP 0x40
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#define BT485_4BPP 0x60
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#define BT485_TRUECOLOR_BYPASS_DISABLED 0x00
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#define BT485_TRUECOLOR_BYPASS_ENABLED 0x10
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#define BT485_RGB_555 0x00
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#define BT485_RGB_565 0x08
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#define BT485_2_1_MUX 0x00
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#define BT485_1_1_MUX 0x04
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#define BT485_MUX_PORT_CR10 0x00
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#define BT485_MUX_PORT_P7D 0x02
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#define BT485_MUX_PORT_B_A 0x00
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#define BT485_MUX_PORT_D_C 0x01
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// COMMAND_2
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#define BT485_SCLK_ENABLED 0x00
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#define BT485_SCLK_DISABLED 0x80
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#define BT485_TEST_PATH_DISABLED 0x00
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#define BT485_TEST_PATH_ENABLED 0x40
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#define BT485_PORTSEL_MASKED 0x00
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#define BT485_PORTSEL_NONMASKED 0x20
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#define BT485_PCLK0_SELECT 0x00
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#define BT485_PCLK1_SELECT 0x10
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#define BT485_NONINTERLACED_DISPLAY 0x00
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#define BT485_INTERLACED_DISPLAY 0x08
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#define BT485_SPARSE_INDEXING 0x00
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#define BT485_CONTIGUOUS_INDEXING 0x04
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#define BT485_CURSOR_FIELDS 0x03
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#define BT485_CURSOR_DISABLED 0x00
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#define BT485_CURSOR_3_COLOR 0x01
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#define BT485_CURSOR_WINDOWS 0x02
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#define BT485_CURSOR_XWINDOWS 0x03
|
|
|
|
// COMMAND_3
|
|
|
|
#define BT485_2X_CLOCK_DISABLED 0x00
|
|
#define BT485_2X_CLOCK_ENABLED 0x08
|
|
|
|
#define BT485_CURSOR_32X32 0x00
|
|
#define BT485_CURSOR_64X64 0x04
|
|
|
|
#define BT485_CURSOR_64X64_FIELDS 0x03
|
|
#define BT485_CURSOR_64X64_XOR_000 0x00
|
|
#define BT485_CURSOR_64X64_XOR_100 0x01
|
|
#define BT485_CURSOR_64X64_AND_000 0x02
|
|
#define BT485_CURSOR_64X64_AND_100 0x03
|
|
|
|
// ViewPoint ----------------------------------------------------------------
|
|
|
|
// Indirect register map
|
|
|
|
#define VPOINT_CUR_X_LSB 0x00
|
|
#define VPOINT_CUR_X_MSB 0x01
|
|
#define VPOINT_CUR_Y_LSB 0x02
|
|
#define VPOINT_CUR_Y_MSB 0x03
|
|
#define VPOINT_SPRITE_X 0x04
|
|
#define VPOINT_SPRITE_Y 0x05
|
|
#define VPOINT_CUR_CTL 0x06
|
|
#define VPOINT_RESERVED_07 0x07
|
|
#define VPOINT_CUR_RAM_LSB 0x08
|
|
#define VPOINT_CUR_RAM_MSB 0x09
|
|
#define VPOINT_CUR_RAM_DATA 0x0a
|
|
#define VPOINT_RESERVED_0b 0x0b
|
|
#define VPOINT_RESERVED_0c 0x0c
|
|
#define VPOINT_RESERVED_0d 0x0d
|
|
#define VPOINT_RESERVED_0e 0x0e
|
|
#define VPOINT_RESERVED_0f 0x0f
|
|
#define VPOINT_WIN_XSTART_LSB 0x10
|
|
#define VPOINT_WIN_XSTART_MSB 0x11
|
|
#define VPOINT_WIN_XSTOP_LSB 0x12
|
|
#define VPOINT_WIN_XSTOP_MSB 0x13
|
|
#define VPOINT_WIN_YSTART_LSB 0x14
|
|
#define VPOINT_WIN_YSTART_MSB 0x15
|
|
#define VPOINT_WIN_YSTOP_LSB 0x16
|
|
#define VPOINT_WIN_YSTOP_MSB 0x17
|
|
#define VPOINT_MUX_CTL1 0x18
|
|
#define VPOINT_MUX_CTL2 0x19
|
|
#define VPOINT_INPUT_CLK 0x1a
|
|
#define VPOINT_OUTPUT_CLK 0x1b
|
|
#define VPOINT_PAL_PAGE 0x1c
|
|
#define VPOINT_GEN_CTL 0x1d
|
|
#define VPOINT_RESERVED_1e 0x1e
|
|
#define VPOINT_RESERVED_1f 0x1f
|
|
#define VPOINT_OVS_RED 0x20
|
|
#define VPOINT_OVS_GREEN 0x21
|
|
#define VPOINT_OVS_BLUE 0x22
|
|
#define VPOINT_CUR_COL0_RED 0x23
|
|
#define VPOINT_CUR_COL0_GREEN 0x24
|
|
#define VPOINT_CUR_COL0_BLUE 0x25
|
|
#define VPOINT_CUR_COL1_RED 0x26
|
|
#define VPOINT_CUR_COL1_GREEN 0x27
|
|
#define VPOINT_CUR_COL1_BLUE 0x28
|
|
#define VPOINT_AUX_CTL 0x29
|
|
#define VPOINT_GEN_IO_CTL 0x2a
|
|
#define VPOINT_GEN_IO_DATA 0x2b
|
|
#define VPOINT_RESERVED_2c 0x2c
|
|
#define VPOINT_RESERVED_2d 0x2d
|
|
#define VPOINT_RESERVED_2e 0x2e
|
|
#define VPOINT_RESERVED_2f 0x2f
|
|
#define VPOINT_KEY_OLVGA_LOW 0x30
|
|
#define VPOINT_KEY_OLVGA_HIGH 0x31
|
|
#define VPOINT_KEY_RED_LOW 0x32
|
|
#define VPOINT_KEY_RED_HI 0x33
|
|
#define VPOINT_KEY_GREEN_LOW 0x34
|
|
#define VPOINT_KEY_GREEN_HI 0x35
|
|
#define VPOINT_KEY_BLUE_LOW 0x36
|
|
#define VPOINT_KEY_BLUE_HI 0x37
|
|
#define VPOINT_KEY_CTL 0x38
|
|
#define VPOINT_RESERVED_39 0x39
|
|
#define VPOINT_SENSE_TEST 0x3a
|
|
#define VPOINT_TEST_DATA 0x3b
|
|
#define VPOINT_CRC_LSB 0x3c
|
|
#define VPOINT_CRC_MSB 0x3d
|
|
#define VPOINT_CRC_CTL 0x3e
|
|
#define VPOINT_ID 0x3f
|
|
#define VPOINT_RESET 0xff
|
|
|
|
#define VIEWPOINT_CURSOR_ON 0x40 //enable XGA + enable sprite
|
|
#define VIEWPOINT_CURSOR_OFF 0x00 //disable XGA cursor
|
|
|
|
// TVP3026 ------------------------------------------------------------------
|
|
|
|
// Direct Register Map
|
|
|
|
// For the Millenium, scale will be 0, for older chips, scale will be 2
|
|
|
|
#define TVP3026_PAL_ADDR_WR(scale) ExtDev+RamDac+(0x00<<scale) //Palette RAM Address Write
|
|
#define TVP3026_CUR_ADDR_WR(scale) ExtDev+RamDac+(0x00<<scale) //Cursor RAM Address Write
|
|
#define TVP3026_INDIRECT_INDEX(scale) ExtDev+RamDac+(0x00<<scale) //Indirect Index
|
|
#define TVP3026_PAL_DATA(scale) ExtDev+RamDac+(0x01<<scale) //Palette RAM Data
|
|
#define TVP3026_PIX_RD_MSK(scale) ExtDev+RamDac+(0x02<<scale) //Pixel Read Mask
|
|
#define TVP3026_PAL_ADDR_RD(scale) ExtDev+RamDac+(0x03<<scale) //Palette RAM A.address Read
|
|
#define TVP3026_CUR_ADDR_RD(scale) ExtDev+RamDac+(0x03<<scale) //Cursor RAM Address Read
|
|
#define TVP3026_CUR_COLOR_ADDR_WR(scale) ExtDev+RamDac+(0x04<<scale) //Cursor Color Address Write
|
|
#define TVP3026_OVS_COLOR_ADDR_WR(scale) ExtDev+RamDac+(0x04<<scale) //Overscan Color Address Write
|
|
#define TVP3026_CUR_COLOR_DATA(scale) ExtDev+RamDac+(0x05<<scale) //Cursor Color Data
|
|
#define TVP3026_OVS_COLOR_DATA(scale) ExtDev+RamDac+(0x05<<scale) //Overscan Color Data
|
|
#define TVP3026_RESERVED_0(scale) ExtDev+RamDac+(0x06<<scale) //Reserved
|
|
#define TVP3026_CUR_COLOR_ADDR_RD(scale) ExtDev+RamDac+(0x07<<scale) //Cursor Color Address Read
|
|
#define TVP3026_OVS_COLOR_ADDR_RD(scale) ExtDev+RamDac+(0x07<<scale) //Overscan Color Address Read
|
|
#define TVP3026_RESERVED_1(scale) ExtDev+RamDac+(0x08<<scale) //Reserved
|
|
#define TVP3026_RESERVED_2(scale) ExtDev+RamDac+(0x09<<scale) //Reserved
|
|
#define TVP3026_INDEXED_DATA(scale) ExtDev+RamDac+(0x0a<<scale) //Indexed Data
|
|
#define TVP3026_CUR_DATA(scale) ExtDev+RamDac+(0x0b<<scale) //Cursor RAM Data
|
|
#define TVP3026_CUR_X_LSB(scale) ExtDev+RamDac+(0x0c<<scale) //Cursor Position X LSB
|
|
#define TVP3026_CUR_X_MSB(scale) ExtDev+RamDac+(0x0d<<scale) //Cursor Position X MSB
|
|
#define TVP3026_CUR_Y_LSB(scale) ExtDev+RamDac+(0x0e<<scale) //Cursor Position Y LSB
|
|
#define TVP3026_CUR_Y_MSB(scale) ExtDev+RamDac+(0x0f<<scale) //Cursor Position Y MSB
|
|
|
|
// Indirect Register Map
|
|
|
|
#define TVP3026_I_PAL_STATUS 0x000
|
|
#define TVP3026_I_REV 0x001
|
|
#define TVP3026_I_RES_02 0x002
|
|
#define TVP3026_I_RES_03 0x003
|
|
#define TVP3026_I_RES_04 0x004
|
|
#define TVP3026_I_RES_05 0x005
|
|
#define TVP3026_I_CUR_CTL 0x006
|
|
#define TVP3026_I_RES_07 0x007
|
|
#define TVP3026_I_RES_08 0x008
|
|
#define TVP3026_I_RES_09 0x009
|
|
#define TVP3026_I_RES_0A 0x00a
|
|
#define TVP3026_I_RES_0B 0x00b
|
|
#define TVP3026_I_RES_0C 0x00c
|
|
#define TVP3026_I_RES_0D 0x00d
|
|
#define TVP3026_I_RES_0E 0x00e
|
|
#define TVP3026_I_LATCH_CTL 0x00f
|
|
#define TVP3026_I_RES_10 0x010
|
|
#define TVP3026_I_RES_11 0x011
|
|
#define TVP3026_I_RES_12 0x012
|
|
#define TVP3026_I_RES_13 0x013
|
|
#define TVP3026_I_RES_14 0x014
|
|
#define TVP3026_I_RES_15 0x015
|
|
#define TVP3026_I_RES_16 0x016
|
|
#define TVP3026_I_RES_17 0x017
|
|
#define TVP3026_I_TRUE_COL_CTL 0x018
|
|
#define TVP3026_I_MPX_CTL 0x019
|
|
#define TVP3026_I_CLK_SEL 0x01a
|
|
#define TVP3026_I_RES_1B 0x01b
|
|
#define TVP3026_I_PAL_PAGE 0x01c
|
|
#define TVP3026_I_GENERAL_CTL 0x01d
|
|
#define TVP3026_I_MISC_CTL 0x01e
|
|
#define TVP3026_I_RES_1F 0x01f
|
|
#define TVP3026_I_RES_20 0x020
|
|
#define TVP3026_I_RES_21 0x021
|
|
#define TVP3026_I_RES_22 0x022
|
|
#define TVP3026_I_RES_23 0x023
|
|
#define TVP3026_I_RES_24 0x024
|
|
#define TVP3026_I_RES_25 0x025
|
|
#define TVP3026_I_RES_26 0x026
|
|
#define TVP3026_I_RES_27 0x027
|
|
#define TVP3026_I_RES_28 0x028
|
|
#define TVP3026_I_RES_29 0x029
|
|
#define TVP3026_I_GEN_IO_CTL 0x02a
|
|
#define TVP3026_I_GEN_IO_DATA 0x02b
|
|
#define TVP3026_I_PLL_ADDR 0x02c
|
|
#define TVP3026_I_PEL_CLK_PLL_DATA 0x02d
|
|
#define TVP3026_I_MEM_CLK_PLL_DATA 0x02e
|
|
#define TVP3026_I_LOAD_CLK_PLL_DATA 0x02f
|
|
#define TVP3026_I_COL_KEY_OVL_LO 0x030
|
|
#define TVP3026_I_COL_KEY_OVL_HI 0x031
|
|
#define TVP3026_I_COL_KEY_R_LO 0x032
|
|
#define TVP3026_I_COL_KEY_R_HI 0x033
|
|
#define TVP3026_I_COL_KEY_G_LO 0x034
|
|
#define TVP3026_I_COL_KEY_G_HI 0x035
|
|
#define TVP3026_I_COL_KEY_B_LO 0x036
|
|
#define TVP3026_I_COL_KEY_B_HI 0x037
|
|
#define TVP3026_I_COL_KEY_CTL 0x038
|
|
#define TVP3026_I_MCLK_CTL 0x039
|
|
#define TVP3026_I_SENSE_TEST 0x03a
|
|
#define TVP3026_I_TEST_DATA 0x03b
|
|
#define TVP3026_I_CRC_REM_LSB 0x03c
|
|
#define TVP3026_I_CRC_REM_MSB 0x03d
|
|
#define TVP3026_I_CRC_BIT_SEL 0x03e
|
|
#define TVP3026_I_ID 0x03f
|
|
#define TVP3026_I_SOFT_RESET 0x0ff
|
|
|
|
#define TVP3026_D_CURSOR_ON 0x02 //00000010b enable XGA cursor
|
|
#define TVP3026_D_CURSOR_OFF 0x00 //00000000b disable cursor
|
|
#define TVP3026_D_CURSOR_MASK 0x03
|
|
|
|
//access cursor bitmap:
|
|
#define TVP3026_D_CURSOR_RAM_00 0x00 //00000000b access bytes 000-0FF
|
|
#define TVP3026_D_CURSOR_RAM_01 0x04 //00000100b access bytes 100-1FF
|
|
#define TVP3026_D_CURSOR_RAM_10 0x08 //00001000b access bytes 200-2FF
|
|
#define TVP3026_D_CURSOR_RAM_11 0x0c //00001100b access bytes 300-3FF
|
|
#define TVP3026_D_CURSOR_RAM_MASK 0x0c
|
|
|
|
#define TVP3026_D_OVS_COLOR 0x00 //00000000b Overscan color
|
|
#define TVP3026_D_CUR_COLOR_0 0x01 //00000001b Cursor color 0
|
|
#define TVP3026_D_CUR_COLOR_1 0x02 //00000010b Cursor color 1
|
|
#define TVP3026_D_CUR_COLOR_2 0x03 //00000011b Cursor color 2
|
|
|
|
// --------------------------------------------------------------------------
|
|
|
|
// MGA PRODUCT ID (from DEFBIND.H in miniport driver)
|
|
|
|
#define MGA_ULT_1M 1
|
|
#define MGA_ULT_2M 2
|
|
#define MGA_IMP_3M 3
|
|
#define MGA_IMP_3M_Z 4
|
|
#define MGA_PRO_4M5 5
|
|
#define MGA_PRO_4M5_Z 6
|
|
#define MGA_PCI_2M 7
|
|
#define MGA_PCI_4M 8
|
|
|
|
#define MGA_STORM 10
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
|
|
// Private IOCTL call definitions
|
|
|
|
#define COMMON_FLAG 0x80000000
|
|
#define CUSTOM_FLAG 0x00002000
|
|
|
|
#define IOCTL_VIDEO_MTX_QUERY_NUM_OFFSCREEN_BLOCKS \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x800, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_QUERY_OFFSCREEN_BLOCKS \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x801, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_INITIALIZE_MGA \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x802, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_QUERY_RAMDAC_INFO \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x803, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_GET_UPDATED_INF \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x804, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_QUERY_BOARD_ID \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x805, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_QUERY_HW_DATA \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x806, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_QUERY_BOARD_ARRAY \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x807, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_MAKE_BOARD_CURRENT \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x808, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
#define IOCTL_VIDEO_MTX_INIT_MODE_LIST \
|
|
CTL_CODE(FILE_DEVICE_VIDEO, 0x809, METHOD_BUFFERED, FILE_ANY_ACCESS)
|
|
|
|
// This structure is used with VIDEO_IOCTL_MTX_QUERY_NUM_OFFSCREEN_BLOCKS.
|
|
|
|
typedef struct _VIDEO_NUM_OFFSCREEN_BLOCKS
|
|
{
|
|
ULONG NumBlocks; // number of offscreen blocks
|
|
ULONG OffscreenBlockLength; // size of OFFSCREEN_BLOCK structure
|
|
} VIDEO_NUM_OFFSCREEN_BLOCKS;
|
|
|
|
// This structure is used with VIDEO_IOCTL_MTX_QUERY_OFFSCREEN_BLOCKS.
|
|
|
|
typedef struct _OFFSCREEN_BLOCK
|
|
{
|
|
ULONG Type; // N_VRAM, N_DRAM, Z_VRAM, or Z_DRAM
|
|
ULONG XStart; // X origin of offscreen memory area
|
|
ULONG YStart; // Y origin of offscreen memory area
|
|
ULONG Width; // offscreen width, in pixels
|
|
ULONG Height; // offscreen height, in pixels
|
|
ULONG SafePlanes; // offscreen available planes
|
|
ULONG ZOffset; // Z start offset, if any Z
|
|
} OFFSCREEN_BLOCK;
|
|
|
|
// This structure is used with IOCTL_VIDEO_MTX_QUERY_RAMDAC_INFO.
|
|
|
|
typedef struct _RAMDAC_INFO
|
|
{
|
|
ULONG Flags; // Ramdac type
|
|
ULONG Width; // Maximum cursor width
|
|
ULONG Height; // Maximum cursor height
|
|
ULONG OverScanX; // X overscan
|
|
ULONG OverScanY; // Y overscan
|
|
} RAMDAC_INFO, *PRAMDAC_INFO;
|
|
|
|
// Definitions for 'Type' field.
|
|
|
|
#define N_VRAM 0 // Normal offscreen in VRAM, supports block mode
|
|
#define N_DRAM 6 // Normal offscreen in DRAM, no support for block mode
|
|
#define Z_VRAM 1 // Z-buffer memory in VRAM, supports block mode
|
|
#define Z_DRAM 7 // Z-buffer memory in DRAM, no support for block mode
|
|
|
|
// These structures are used with IOCTL_VIDEO_MTX_QUERY_HW_DATA. They should
|
|
// be kept in sync with the CursorInfo and HwData structures defined in the
|
|
// miniport driver.
|
|
|
|
typedef struct _CURSOR_INFO
|
|
{
|
|
ULONG MaxWidth;
|
|
ULONG MaxHeight;
|
|
ULONG MaxDepth;
|
|
ULONG MaxColors;
|
|
ULONG CurWidth;
|
|
ULONG CurHeight;
|
|
LONG cHotSX;
|
|
LONG cHotSY;
|
|
LONG HotSX;
|
|
LONG HotSY;
|
|
} CURSOR_INFO, *PCURSOR_INFO;
|
|
|
|
// Defines for HwData.Features flags
|
|
|
|
#define DDC_MONITOR_SUPPORT 0x0001
|
|
#define STORM_ON_MOTHERBOARD 0x0002
|
|
#define MEDIA_EXCEL 0x0004
|
|
#define INTERLEAVE_MODE 0x0008
|
|
|
|
typedef struct _HW_DATA
|
|
{
|
|
ULONG StructLength; /* Structure length in bytes */
|
|
ULONG MapAddress; /* Memory map address */
|
|
ULONG MapAddress2; /* Physical base address, frame buffer */
|
|
ULONG RomAddress; /* Physical base address, flash EPROM */
|
|
ULONG ProductType; /* MGA Ultima ID, MGA Impression ID, ... */
|
|
ULONG ProductRev; /* 4 bit revision codes as follows */
|
|
/* 0 - 3 : pcb revision */
|
|
/* 4 - 7 : Titan revision */
|
|
/* 8 - 11 : Dubic revision */
|
|
/* 12 - 31 : all 1's indicating no other device
|
|
present */
|
|
ULONG ShellRev; /* Shell revision */
|
|
ULONG BindingRev; /* Binding revision */
|
|
|
|
ULONG MemAvail; /* Frame buffer memory in bytes */
|
|
BYTE VGAEnable; /* 0 = vga disabled, 1 = vga enabled */
|
|
BYTE Sync; /* relects the hardware straps */
|
|
BYTE Device8_16; /* relects the hardware straps */
|
|
|
|
BYTE PortCfg; /* 0-Disabled, 1-Mouse Port, 2-Laser Port */
|
|
BYTE PortIRQ; /* IRQ level number, -1 = interrupts disabled */
|
|
ULONG MouseMap; /* Mouse I/O map base if PortCfg = Mouse Port else don't care */
|
|
BYTE MouseIRate; /* Mouse interrupt rate in Hz */
|
|
BYTE DacType; /* 0 = BT482, 3 = BT485 */
|
|
CURSOR_INFO cursorInfo;
|
|
ULONG VramAvail; /* VRAM memory available on board in bytes */
|
|
ULONG DramAvail; /* DRAM memory available on board in bytes */
|
|
ULONG CurrentOverScanX; /* Left overscan in pixels */
|
|
ULONG CurrentOverScanY; /* Top overscan in pixels */
|
|
ULONG YDstOrg; /* Physical offset of display start */
|
|
ULONG YDstOrg_DB; /* Starting offset for double buffer */
|
|
ULONG CurrentZoomFactor;
|
|
ULONG CurrentXStart;
|
|
ULONG CurrentYStart;
|
|
ULONG CurrentPanXGran; /* X Panning granularity */
|
|
ULONG CurrentPanYGran; /* Y Panning granularity */
|
|
ULONG Features; /* Bit 0: 0 = DDC monitor not available */
|
|
/* 1 = DDC monitor available */
|
|
BYTE Reserved[64];
|
|
|
|
ULONG MgaBase1; /* MGA control aperture */
|
|
ULONG MgaBase2; /* Direct frame buffer */
|
|
ULONG RomBase; /* BIOS flash EPROM */
|
|
ULONG PresentMCLK;
|
|
} HW_DATA, *PHW_DATA;
|
|
|
|
// Definitions for RamDacType field.
|
|
|
|
#define RAMDAC_FIELDS 0xf000
|
|
#define RAMDAC_NONE 0x0000
|
|
#define RAMDAC_BT482 0x1000
|
|
#define RAMDAC_BT485 0x2000
|
|
#define RAMDAC_VIEWPOINT 0x3000
|
|
#define RAMDAC_TVP3026 0x4000
|
|
#define RAMDAC_PX2085 0x5000
|
|
#define RAMDAC_TVP3030 0x6000
|
|
|
|
//////////////////////////////////////////////////////////////////////
|
|
// PowerPC considerations
|
|
//
|
|
// The PowerPC does not guarantee that I/O to separate addresses will
|
|
// be executed in order. However, the PowerPC guarantees that
|
|
// output to the same address will be executed in order.
|
|
//
|
|
// Consequently, we use the following synchronization macros. They
|
|
// are relatively expensive in terms of performance, so we try to avoid
|
|
// them whereever possible.
|
|
//
|
|
// CP_EIEIO() 'Ensure In-order Execution of I/O'
|
|
// - Used to flush any pending I/O in situations where we wish to
|
|
// avoid out-of-order execution of I/O to separate addresses.
|
|
//
|
|
// CP_MEMORY_BARRIER()
|
|
// - Used to flush any pending I/O in situations where we wish to
|
|
// avoid out-of-order execution or 'collapsing' of I/O to
|
|
// the same address. We used to have to do this separately for
|
|
// the Alpha because unlike the PowerPC it did not guarantee that
|
|
// output to the same address will be exectued in order. However,
|
|
// with the move to kernel-mode, on Alpha we are now calling HAL
|
|
// routines for every port I/O which ensure that this is not a
|
|
// problem.
|
|
|
|
#if defined(_PPC_)
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|
|
|
// On PowerPC, CP_MEMORY_BARRIER doesn't do anything.
|
|
|
|
#define CP_EIEIO() MEMORY_BARRIER()
|
|
#define CP_MEMORY_BARRIER()
|
|
|
|
#elif defined(_ALPHA_)
|
|
|
|
// On Alpha, since we must do all non-frame-buffer I/O through HAL
|
|
// routines, which automatically do memory-barriers, we don't have
|
|
// to do memory barriers ourselves (and should not, because it's a
|
|
// performance hit).
|
|
|
|
#define CP_EIEIO()
|
|
#define CP_MEMORY_BARRIER()
|
|
|
|
#else
|
|
|
|
// On other systems, both CP_EIEIO and CP_MEMORY_BARRIER don't do anything.
|
|
|
|
#define CP_EIEIO() MEMORY_BARRIER()
|
|
#define CP_MEMORY_BARRIER() MEMORY_BARRIER()
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|
|
|
#endif
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
// Unsafe direct access macros
|
|
//
|
|
// These are macros for directly accessing the MGA's accelerator
|
|
// registers. They should be used with care, because they always
|
|
// ignore memory barriers:
|
|
|
|
#define CP_WRITE_DIRECT(pjBase, addr, dw) \
|
|
WRITE_REGISTER_ULONG((BYTE*) (pjBase) + (addr), (ULONG) (dw))
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|
|
|
#define CP_WRITE_DIRECT_BYTE(pjBase, addr, j) \
|
|
WRITE_REGISTER_UCHAR((BYTE*) (pjBase) + (addr), (UCHAR) (j))
|
|
|
|
#define CP_READ_REGISTER(p) \
|
|
READ_REGISTER_ULONG((BYTE*) (p))
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|
|
|
#define CP_READ_REGISTER_BYTE(p) \
|
|
READ_REGISTER_UCHAR((BYTE*) (p))
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
// 'Safe' direct access macros
|
|
//
|
|
// These are the 'safe' slow versions for directly writing to a port,
|
|
// because they automatically always handle memory barriers:
|
|
|
|
#define CP_WRITE_REGISTER(p, dw) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
WRITE_REGISTER_ULONG(p, (ULONG) (dw)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
#define CP_WRITE_REGISTER_WORD(p, w) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
WRITE_REGISTER_USHORT(p, (USHORT) (w)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
#define CP_WRITE_REGISTER_BYTE(p, j) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
WRITE_REGISTER_UCHAR(p, (UCHAR) (j)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
////////////////////////////////////////////////////////////////////////
|
|
// MGA direct access macros
|
|
//
|
|
// These macros abstract some MGA register accesses.
|
|
|
|
#define CP_WRITE_SRC(pjBase, dw) \
|
|
{ \
|
|
CP_WRITE_DIRECT((pjBase), DWG_SRC0, (dw)); \
|
|
CP_MEMORY_BARRIER(); \
|
|
}
|
|
|
|
#define CP_READ_STATUS(pjBase) \
|
|
CP_READ_REGISTER_BYTE((BYTE*) (pjBase) + HST_STATUS + 2)
|
|
|
|
#define CP_READ(pjBase, addr) \
|
|
CP_READ_REGISTER((BYTE*) (pjBase) + (addr))
|
|
|
|
#if DBG
|
|
|
|
#define CP_START(pjBase, addr, dw) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
vWriteDword((BYTE*) (pjBase) + (addr) + (StartDwgReg), (ULONG) (dw)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
#define CP_WRITE(pjBase, addr, dw) \
|
|
vWriteDword((BYTE*) (pjBase) + (addr), (ULONG) (dw))
|
|
|
|
#define CP_WRITE_BYTE(pjBase, addr, j) \
|
|
vWriteByte((BYTE*) (pjBase) + (addr), (UCHAR) (j))
|
|
|
|
#define CHECK_FIFO_SPACE(pjBase, level) \
|
|
vCheckFifoSpace((pjBase), (level))
|
|
|
|
#define GET_FIFO_SPACE(pjBase) \
|
|
cGetFifoSpace((pjBase))
|
|
|
|
#else
|
|
|
|
#define CP_START(pjBase, addr, dw) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
WRITE_REGISTER_ULONG((BYTE*) (pjBase) + (addr) + (StartDwgReg), (ULONG) (dw)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
#define CP_WRITE(pjBase, addr, dw) \
|
|
WRITE_REGISTER_ULONG((BYTE*) (pjBase) + (addr), (ULONG) (dw))
|
|
|
|
#define CP_WRITE_BYTE(pjBase, addr, j) \
|
|
WRITE_REGISTER_UCHAR((BYTE*) (pjBase) + (addr), (UCHAR) (j))
|
|
|
|
#define CHECK_FIFO_SPACE(pjBase, level) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
do {} while (CP_READ_REGISTER_BYTE((pjBase) + HST_FIFOSTATUS) < (level)); \
|
|
}
|
|
|
|
__inline CHAR GET_FIFO_SPACE(BYTE* pjBase) \
|
|
{ \
|
|
CP_EIEIO(); \
|
|
return(CP_READ_REGISTER_BYTE((pjBase) + HST_FIFOSTATUS)); \
|
|
}
|
|
|
|
#endif
|
|
|
|
// It used to be that we had to worry about the Alpha collapsing writes
|
|
// to the same address. Not any more! With NT 4.0, all I/O on the
|
|
// Alpha goes through HAL calls that automatically ensure that
|
|
// collapsed writes will not be a problem.
|
|
|
|
#define CP_WRITE_DMA(ppdev, pjDma, dw) \
|
|
CP_WRITE((pjDma), 0, (dw))
|
|
|
|
#define CP_READ_DMA(ppdev, pjDma) \
|
|
CP_READ((pjDma), 0)
|
|
|
|
#define CHECK_FIFO_FREE(pjBase, cFifo, needed) \
|
|
{ \
|
|
(cFifo) -= (needed); \
|
|
while ((CHAR) (cFifo) < 0) \
|
|
{ \
|
|
(cFifo) = GET_FIFO_SPACE(pjBase) - (needed); \
|
|
} \
|
|
}
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
|
|
__inline ULONG COLOR_REPLICATE(PDEV* ppdev, ULONG x)
|
|
{
|
|
ULONG ulResult = x;
|
|
if (ppdev->cjPelSize == 1)
|
|
{
|
|
ulResult |= (ulResult << 8);
|
|
ulResult |= (ulResult << 16);
|
|
}
|
|
else if (ppdev->cjPelSize == 2)
|
|
{
|
|
ulResult |= (ulResult << 16);
|
|
}
|
|
return(ulResult);
|
|
}
|
|
|
|
// The PACKXY macro is used for line drawing, and is safe for
|
|
// negative 'x' values:
|
|
|
|
#define PACKXY(x, y) (((y) << 16) | (x) & 0xffff)
|
|
|
|
// This one isn't safe for negative 'x' values:
|
|
|
|
#define PACKXY_QUICK(x, y) (((y) << 16) | (x))
|
|
|
|
/////////////////////////////////////////////////////////////////
|
|
// DirectDraw stuff
|
|
|
|
__inline BOOL VBLANK_IS_ACTIVE(BYTE* pjBase)
|
|
{
|
|
CP_EIEIO();
|
|
return(CP_READ_REGISTER_BYTE((BYTE*) (pjBase) + VGA_INSTS1) & 0x08);
|
|
}
|
|
|
|
__inline BOOL DISPLAY_IS_ACTIVE(BYTE* pjBase)
|
|
{
|
|
CP_EIEIO();
|
|
return(!(CP_READ_REGISTER_BYTE((BYTE*) (pjBase) + VGA_INSTS1) & 0x01));
|
|
}
|
|
|
|
__inline ULONG GET_SCANLINE(BYTE* pjBase)
|
|
{
|
|
CP_EIEIO();
|
|
return(CP_READ_REGISTER((pjBase) + HST_VCOUNT));
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// START_ and END_DIRECT_ACCESS should bracket direct frame buffer
|
|
// access so that memory barriers are performed correctly on the
|
|
// PowerPC and Alpha.
|
|
|
|
#define START_DIRECT_ACCESS_MGA_NO_WAIT(ppdev, pjBase)\
|
|
CP_EIEIO()
|
|
|
|
#define START_DIRECT_ACCESS_MGA(ppdev, pjBase)\
|
|
CP_EIEIO();WAIT_NOT_BUSY(pjBase)
|
|
|
|
#define END_DIRECT_ACCESS_MGA(ppdev, pjBase)\
|
|
CP_EIEIO()
|
|
|
|
#define START_DIRECT_ACCESS_STORM(ppdev, pjBase)\
|
|
{\
|
|
CP_EIEIO();\
|
|
WAIT_NOT_BUSY(pjBase);\
|
|
}
|
|
|
|
//////////////////////////////////////////////////////////////////////////
|
|
// The STORM has an ugly framebuffer read coherency bug -- it does not
|
|
// invalidate its frame buffer cache when an accelerator operation is
|
|
// done. To work around this, we do some extra reads to make sure the
|
|
// data in the cache is currently valid.
|
|
//
|
|
// This problem was most evident with USWC turned on with a Pentium Pro,
|
|
// when using a software cursor and selecting text using 'QuickEdit' mode
|
|
// in a console window -- cursor turds would be left around the screen.
|
|
|
|
#define START_DIRECT_ACCESS_STORM_FOR_READ(ppdev, pjBase) \
|
|
{ \
|
|
volatile ULONG ulTmp; \
|
|
CP_EIEIO(); \
|
|
WAIT_NOT_BUSY(pjBase); \
|
|
ulTmp = *(volatile ULONG *)(ppdev->pjScreen); \
|
|
ulTmp = *(volatile ULONG *)(ppdev->pjScreen + 32); \
|
|
CHECK_FIFO_SPACE(pjBase, 1);/* Done to flush USWC cache */ \
|
|
}
|
|
|
|
// The STORM has an ugly framebuffer cache coherency bug. We need to
|
|
// do some extra reads to make sure that data written to the
|
|
// framebuffer are actually flushed from the cache into video memory.
|
|
//
|
|
// This problem was evident when running OpenGL conformance tests.
|
|
|
|
#define END_DIRECT_ACCESS_STORM(ppdev, pjBase) \
|
|
{ \
|
|
volatile ULONG ulTmp; \
|
|
CP_EIEIO(); \
|
|
ulTmp = *(volatile ULONG *)(ppdev->pjScreen); \
|
|
ulTmp = *(volatile ULONG *)(ppdev->pjScreen + 128); \
|
|
}
|
|
|
|
#define BLT_WRITE_ON(ppdev, pjBase) \
|
|
{ \
|
|
ULONG ul; \
|
|
\
|
|
ul = CP_READ_REGISTER(pjBase + HST_OPMODE) & OPMODE_OTHER_INFO; \
|
|
CP_WRITE_DIRECT_BYTE(pjBase, HST_OPMODE, ul | (dmamod_BLIT_WRITE)); \
|
|
CP_MEMORY_BARRIER(); \
|
|
CP_WRITE_DIRECT_BYTE(pjBase, HST_OPMODE, ul | (dmamod_BLIT_WRITE | pseudodma_ON)); \
|
|
CP_EIEIO(); \
|
|
CP_READ_REGISTER(pjBase + HST_OPMODE); \
|
|
}
|
|
|
|
#define BLT_WRITE_OFF(ppdev, pjBase) \
|
|
{ \
|
|
ULONG ul; \
|
|
\
|
|
ul = CP_READ_REGISTER(pjBase + HST_OPMODE) & OPMODE_OTHER_INFO; \
|
|
CP_WRITE_DIRECT_BYTE(pjBase, HST_OPMODE, ul | (pseudodma_OFF)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
#define BLT_READ_ON(ppdev, pjBase) \
|
|
{ \
|
|
ULONG ul; \
|
|
\
|
|
ul = CP_READ_REGISTER(pjBase + HST_OPMODE) & OPMODE_OTHER_INFO; \
|
|
CP_WRITE_DIRECT_BYTE(pjBase, HST_OPMODE, ul | (dmamod_BLIT_READ)); \
|
|
CP_MEMORY_BARRIER(); \
|
|
CP_WRITE_DIRECT_BYTE(pjBase, HST_OPMODE, ul | (dmamod_BLIT_READ | pseudodma_ON)); \
|
|
CP_EIEIO(); \
|
|
}
|
|
|
|
#define BLT_READ_OFF(ppdev, pjBase) \
|
|
BLT_WRITE_OFF((ppdev), (pjBase))
|
|
|
|
#define IS_BUSY(pjBase) \
|
|
((CP_READ_STATUS(pjBase) & (dwgengsts_MASK >> 16)) != 0)
|
|
|
|
#define WAIT_NOT_BUSY(pjBase) \
|
|
{ \
|
|
do {} while (IS_BUSY(pjBase)); \
|
|
}
|
|
|
|
#define DATA_TRANSFER(pjBase, pjSrc, cdSrc) \
|
|
{ \
|
|
LONG i = (LONG) (cdSrc); \
|
|
ULONG* pulSrcTmp = (ULONG*) (pjSrc); \
|
|
do { \
|
|
CP_WRITE_DIRECT(pjBase, DWG_SRC0, *pulSrcTmp); \
|
|
pulSrcTmp++; \
|
|
} while (--i != 0); \
|
|
}
|