1055 lines
36 KiB
C
1055 lines
36 KiB
C
/*++
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Copyright (c) 1992-1997 Microsoft Corporation
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Copyright (c) 1996-1997 Cirrus Logic, Inc.,
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Module Name:
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C I R R U S . H
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Abstract:
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This module contains the definitions for the code that implements the
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Cirrus Logic VGA 6410/6420/542x device driver.
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Environment:
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Kernel mode
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Revision History:
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* chu01 08-26-96 : Distinguish CL-5480 and CL-5436/46 because the former
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* has new fratures such as XY-clipping, XY-position and
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* BLT command list that the others do not have.
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* sge01 10-14-96 : Add PC97 Compliant support.
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*
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* sge02 10-24-96 : Add second aperture flag.
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*
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* sge03 10-29-96 : Merge port access and register access for VGA relocatable and MMIO registers.
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* chu02 12-16-96 : Enable color correct.
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*
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* myf0 : 08-19-96 added 85hz supported
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* myf1 : 08-20-96 supported panning scrolling
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* myf2 : 08-20-96 : fixed hardware save/restore state bug for matterhorn
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* myf3 : 09-01-96 : Added IOCTL_CIRRUS_PRIVATE_BIOS_CALL for TV supported
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* myf4 : 09-01-96 : patch Viking BIOS bug, PDR #4287, begin
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* myf5 : 09-01-96 : Fixed PDR #4365 keep all default refresh rate
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* myf6 : 09-17-96 : Merged Desktop SRC100á1 & MINI10á2
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* myf7 : 09-19-96 : Fixed exclude 60Hz refresh rate selected
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* myf8 :*09-21-96*: May be need change CheckandUpdateDDC2BMonitor --keystring[]
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* myf9 : 09-21-96 : 8x6 panel in 6x4x256 mode, cursor can't move to bottom scrn
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* ms0809:09-25-96 : fixed dstn panel icon corrupted
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* ms923 :09-25-96 : merge MS-923 Disp.zip code
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* myf10 :09-26-96 : Fixed DSTN reserved half-frame buffer bug.
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* myf11 :09-26-96 : Fixed 755x CE chip HW bug, access ramdac before disable HW
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* icons and cursor
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* myf12 :10-01-96 : Supported Hot Key switch display
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* myf13 :10-02-96 : Fixed Panning scrolling (1280x1024x256) bug y < ppdev->miny
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* myf14 :10-15-96 : Fixed PDR#6917, 6x4 panel can't panning scrolling for 754x
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* myf15 :10-16-96 : Fixed disable memory mapped IO for 754x, 755x
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* myf16 :10-22-96 : Fixed PDR #6933,panel type set different demo board setting
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* tao1 : 10-21-96 : added CAPS_IS_7555 flag for direct draw support.
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* smith :10-22-96 : Disable Timer event, because sometimes creat PAGE_FAULT or
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* IRQ level can't handle
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* myf17 :11-04-96 : Added special escape code must be use 11/5/96 later NTCTRL,
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* and added Matterhorn LF Device ID==0x4C
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* myf18 :11-04-96 : Fixed PDR #7075,
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* myf19 :11-06-96 : Fixed Vinking can't work problem, because DEVICEID = 0x30
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* is different from data book (CR27=0x2C)
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* myf20 :11-12-96 : Fixed DSTN panel initial reserved 128K memoru
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* myf21 :11-15-96 : fixed #7495 during change resolution, screen appear garbage
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* image, because not clear video memory.
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* myf22 :11-19-96 : Added 640x480x256/640x480x64K -85Hz refresh rate for 7548
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* myf23 :11-21-96 : Added fixed NT 3.51 S/W cursor panning problem
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* myf24 :11-22-96 : Added fixed NT 4.0 Japanese dos full screen problem
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* myf25 :12-03-96 : Fixed 8x6x16M 2560byte/line patch H/W bug PDR#7843, and
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* fixed pre-install microsoft requested
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* myf26 :12-11-96 : Fixed Japanese NT 4.0 Dos-full screen bug for LCD enable
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* myf27 :01-09-96 : Fixed NT3.51 PDR#7986, horizontal lines appears at logon
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* windows, set 8x6x64K mode boot up CRT, jumper set 8x6 DSTN
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* Fixed NT3.51 PDR#7987, set 64K color modes, garbage on
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* screen when boot up XGA panel.
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* sge04 01-23-96 : Add CL5446_ID and CL5480_ID.
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* myf33 :03-21-97 : Support TV ON/OFF
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* chu03 03-26-97 : Get rid of 1024x768x16bpp ( Mode 0x74 ) 85H for IBM only.
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*
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--*/
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#define INT10_MODE_SET
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//
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// Do full save and restore.
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//
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#define EXTENDED_REGISTER_SAVE_RESTORE 1
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//
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// Banking ifdefs to enable banking
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// the banking type MUST match the type in clhard.asm
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//
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#define ONE_64K_BANK 0
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#define TWO_32K_BANKS 1
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#define MULTIPLE_REFRESH_TABLES 0
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//crus
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//myf17 #define PANNING_SCROLL //myf1
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//
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// Treat CL-GD5434_6 (rev 0xHH) as CL-GD5434 if requested.
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//
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#define CL5434_6_SPECIAL_REQUEST 0
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//---------------------------------------------------------------------------
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//
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// only one banking variable must be defined
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//
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#if TWO_32K_BANKS
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#if ONE_64K_BANK
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#error !!ERROR: two types of banking defined!
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#endif
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#elif ONE_64K_BANK
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#else
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#error !!ERROR: banking type must be defined!
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#endif
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//
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// Enable P6 Cache support
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//
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#define P6CACHE 1
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//
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// Base address of VGA memory range. Also used as base address of VGA
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// memory when loading a font, which is done with the VGA mapped at A0000.
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//
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#define MEM_VGA 0xA0000
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#define MEM_VGA_SIZE 0x20000
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#define MEM_LINEAR 0x0
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#define MEM_LINEAR_SIZE 0x0
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// #ifdef _ALPHA_
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//
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// #define PHY_AD_20_23 0x060 // Value for SR7 to map video memory
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// #define PHY_VGA 0x0600000 // put it at 6 megabytes for Alpha (for now)
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// #define PHY_VGA_SIZE 0x0100000 // allocate a megabyte of space there
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//
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// #endif
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//
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//
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// For memory mapped IO
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//
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#define MEMORY_MAPPED_IO_OFFSET (0xB8000 - 0xA0000)
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#define RELOCATABLE_MEMORY_MAPPED_IO_OFFSET 0x100
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//
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// Port definitions for filling the ACCESS_RANGES structure in the miniport
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// information, defines the range of I/O ports the VGA spans.
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// There is a break in the IO ports - a few ports are used for the parallel
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// port. Those cannot be defined in the ACCESS_RANGE, but are still mapped
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// so all VGA ports are in one address range.
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//
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#define VGA_BASE_IO_PORT 0x000003B0
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#define VGA_START_BREAK_PORT 0x000003BB
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#define VGA_END_BREAK_PORT 0x000003C0
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#define VGA_MAX_IO_PORT 0x000003DF
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//
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// VGA register definitions
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//
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#define CRTC_ADDRESS_PORT_MONO 0x03B4 // CRT Controller Address and
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#define CRTC_DATA_PORT_MONO 0x03B5 // Data registers in mono mode
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#define FEAT_CTRL_WRITE_PORT_MONO 0x03BA // Feature Control write port
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// in mono mode
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#define INPUT_STATUS_1_MONO 0x03BA // Input Status 1 register read
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// port in mono mode
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#define ATT_INITIALIZE_PORT_MONO INPUT_STATUS_1_MONO
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// Register to read to reset
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// Attribute Controller index/data
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#define ATT_ADDRESS_PORT 0x03C0 // Attribute Controller Address and
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#define ATT_DATA_WRITE_PORT 0x03C0 // Data registers share one port
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// for writes, but only Address is
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// readable at 0x010
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#define ATT_DATA_READ_PORT 0x03C1 // Attribute Controller Data reg is
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// readable here
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#define MISC_OUTPUT_REG_WRITE_PORT 0x03C2 // Miscellaneous Output reg write
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// port
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#define INPUT_STATUS_0_PORT 0x03C2 // Input Status 0 register read
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// port
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#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x03C3 // Bit 0 enables/disables the
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// entire VGA subsystem
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#define SEQ_ADDRESS_PORT 0x03C4 // Sequence Controller Address and
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#define SEQ_DATA_PORT 0x03C5 // Data registers
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#define DAC_PIXEL_MASK_PORT 0x03C6 // DAC pixel mask reg
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#define DAC_ADDRESS_READ_PORT 0x03C7 // DAC register read index reg,
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// write-only
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#define DAC_STATE_PORT 0x03C7 // DAC state (read/write),
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// read-only
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#define DAC_ADDRESS_WRITE_PORT 0x03C8 // DAC register write index reg
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#define DAC_DATA_REG_PORT 0x03C9 // DAC data transfer reg
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#define FEAT_CTRL_READ_PORT 0x03CA // Feature Control read port
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#define MISC_OUTPUT_REG_READ_PORT 0x03CC // Miscellaneous Output reg read
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// port
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#define GRAPH_ADDRESS_PORT 0x03CE // Graphics Controller Address
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#define GRAPH_DATA_PORT 0x03CF // and Data registers
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// ports in color mode
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#define CRTC_ADDRESS_PORT_COLOR 0x03D4 // CRT Controller Address and
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#define CRTC_DATA_PORT_COLOR 0x03D5 // Data registers in color mode
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#define FEAT_CTRL_WRITE_PORT_COLOR 0x03DA // Feature Control write port
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#define INPUT_STATUS_1_COLOR 0x03DA // Input Status 1 register read
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// port in color mode
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#define ATT_INITIALIZE_PORT_COLOR INPUT_STATUS_1_COLOR
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// Register to read to reset
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// Attribute Controller index/data
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// toggle in color mode
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//
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// Offsets in HardwareStateHeader->PortValue[] of save areas for non-indexed
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// VGA registers.
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//
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#define CRTC_ADDRESS_MONO_OFFSET 0x04
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#define FEAT_CTRL_WRITE_MONO_OFFSET 0x0A
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#define ATT_ADDRESS_OFFSET 0x10
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#define MISC_OUTPUT_REG_WRITE_OFFSET 0x12
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#define VIDEO_SUBSYSTEM_ENABLE_OFFSET 0x13
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#define SEQ_ADDRESS_OFFSET 0x14
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#define DAC_PIXEL_MASK_OFFSET 0x16
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#define DAC_STATE_OFFSET 0x17
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#define DAC_ADDRESS_WRITE_OFFSET 0x18
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#define GRAPH_ADDRESS_OFFSET 0x1E
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#define CRTC_ADDRESS_COLOR_OFFSET 0x24
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#define FEAT_CTRL_WRITE_COLOR_OFFSET 0x2A
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// toggle in color mode
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//
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// VGA indexed register indexes.
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//
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// CL-GD542x specific registers:
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//
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#define IND_CL_EXTS_ENB 0x06 // index in Sequencer to enable exts
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#define IND_NORD_SCRATCH_PAD 0x09 // index in Seq of Nordic scratch pad
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#define IND_CL_SCRATCH_PAD 0x0A // index in Seq of 542x scratch pad
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#define IND_ALP_SCRATCH_PAD 0x15 // index in Seq of Alpine scratch pad
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#define IND_CL_REV_REG 0x25 // index in CRTC of ID Register
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#define IND_CL_ID_REG 0x27 // index in CRTC of ID Register
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//
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#define IND_CURSOR_START 0x0A // index in CRTC of the Cursor Start
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#define IND_CURSOR_END 0x0B // and End registers
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#define IND_CURSOR_HIGH_LOC 0x0E // index in CRTC of the Cursor Location
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#define IND_CURSOR_LOW_LOC 0x0F // High and Low Registers
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#define IND_VSYNC_END 0x11 // index in CRTC of the Vertical Sync
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// End register, which has the bit
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// that protects/unprotects CRTC
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// index registers 0-7
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#define IND_CR2C 0x2C // Nordic LCD Interface Register
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#define IND_CR2D 0x2D // Nordic LCD Display Control
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#define IND_SET_RESET_ENABLE 0x01 // index of Set/Reset Enable reg in GC
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#define IND_DATA_ROTATE 0x03 // index of Data Rotate reg in GC
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#define IND_READ_MAP 0x04 // index of Read Map reg in Graph Ctlr
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#define IND_GRAPH_MODE 0x05 // index of Mode reg in Graph Ctlr
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#define IND_GRAPH_MISC 0x06 // index of Misc reg in Graph Ctlr
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#define IND_BIT_MASK 0x08 // index of Bit Mask reg in Graph Ctlr
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#define IND_SYNC_RESET 0x00 // index of Sync Reset reg in Seq
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#define IND_MAP_MASK 0x02 // index of Map Mask in Sequencer
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#define IND_MEMORY_MODE 0x04 // index of Memory Mode reg in Seq
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#define IND_CRTC_PROTECT 0x11 // index of reg containing regs 0-7 in
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// CRTC
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#define IND_CRTC_COMPAT 0x34 // index of CRTC Compatibility reg
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// in CRTC
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#define IND_PERF_TUNING 0x16 // index of performance tuning in Seq
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#define START_SYNC_RESET_VALUE 0x01 // value for Sync Reset reg to start
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// synchronous reset
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#define END_SYNC_RESET_VALUE 0x03 // value for Sync Reset reg to end
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// synchronous reset
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//
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// Value to write to Extensions Control register values extensions.
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//
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#define CL64xx_EXTENSION_ENABLE_INDEX 0x0A // GR0A to be exact!
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#define CL64xx_EXTENSION_ENABLE_VALUE 0xEC
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#define CL64xx_EXTENSION_DISABLE_VALUE 0xCE
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#define CL64xx_TRISTATE_CONTROL_REG 0xA1
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#define CL6340_ENABLE_READBACK_REGISTER 0xE0
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#define CL6340_ENABLE_READBACK_ALLSEL_VALUE 0xF0
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#define CL6340_ENABLE_READBACK_OFF_VALUE 0x00
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#define CL6340_IDENTIFICATION_REGISTER 0xE9
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//
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// Values for Attribute Controller Index register to turn video off
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// and on, by setting bit 5 to 0 (off) or 1 (on).
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//
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#define VIDEO_DISABLE 0
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#define VIDEO_ENABLE 0x20
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#define INDEX_ENABLE_AUTO_START 0x31
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// Masks to keep only the significant bits of the Graphics Controller and
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// Sequencer Address registers. Masking is necessary because some VGAs, such
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// as S3-based ones, don't return unused bits set to 0, and some SVGAs use
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// these bits if extensions are enabled.
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//
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#define GRAPH_ADDR_MASK 0x0F
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#define SEQ_ADDR_MASK 0x07
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//
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// Mask used to toggle Chain4 bit in the Sequencer's Memory Mode register.
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//
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#define CHAIN4_MASK 0x08
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//
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// Value written to the Read Map register when identifying the existence of
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// a VGA in VgaInitialize. This value must be different from the final test
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// value written to the Bit Mask in that routine.
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//
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#define READ_MAP_TEST_SETTING 0x03
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//
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// Default text mode setting for various registers, used to restore their
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// states if VGA detection fails after they've been modified.
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//
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#define MEMORY_MODE_TEXT_DEFAULT 0x02
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#define BIT_MASK_DEFAULT 0xFF
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#define READ_MAP_DEFAULT 0x00
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//
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// Palette-related info.
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//
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//
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// Highest valid DAC color register index.
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//
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#define VIDEO_MAX_COLOR_REGISTER 0xFF
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//
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// Highest valid palette register index
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//
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#define VIDEO_MAX_PALETTE_REGISTER 0x0F
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//
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// Indices for type of memory mapping; used in ModesVGA[], must match
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// MemoryMap[].
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//
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typedef enum _VIDEO_MEMORY_MAP {
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MemMap_Mono,
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MemMap_CGA,
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MemMap_VGA
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} VIDEO_MEMORY_MAP, *PVIDEO_MEMORY_MAP;
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//
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// Memory map table definition
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//
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typedef struct {
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ULONG MaxSize; // Maximum addressable size of memory
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ULONG Offset; // Start address of display memory
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} MEMORYMAPS;
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//
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// For a mode, the type of banking supported. Controls the information
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// returned in VIDEO_BANK_SELECT. PlanarHCBanking includes NormalBanking.
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//
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typedef enum _BANK_TYPE {
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NoBanking = 0,
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NormalBanking,
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PlanarHCBanking
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} BANK_TYPE, *PBANK_TYPE;
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//
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// Define type of cirrus boards
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//
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typedef enum _BOARD_TYPE {
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SPEEDSTARPRO = 1,
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SIEMENS_ONBOARD_CIRRUS,
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NEC_ONBOARD_CIRRUS,
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OTHER
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} BOARD_TYPE;
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||
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||
|
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//
|
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// The chip ID is returned to the display driver in the
|
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// DriverSpecificAttributeFlags field during processing of
|
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// the IOCTL_VIDEO_QUERY_CURRENT_MODE.
|
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//
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||
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#define CL6410 0x0001
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#define CL6420 0x0002
|
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#define CL542x 0x0004
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#define CL543x 0x0008
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#define CL5434 0x0010
|
||
#define CL5434_6 0x0020
|
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#define CL5446BE 0x0040
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#define CL5436 0x0100
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#define CL5446 0x0200
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#define CL54UM36 0x0400
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//crus
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#define CL5480 0x0800
|
||
|
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//myf32 begin
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||
//#define CL754x 0x1000
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//#define CL755x 0x2000
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#define CL7541 0x1000
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#define CL7542 0x2000
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#define CL7543 0x4000
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#define CL7548 0x8000
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#define CL754x (CL7541 | CL7542 | CL7543 | CL7548)
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#define CL7555 0x10000
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||
#define CL7556 0x20000
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#define CL755x (CL7555 | CL7556)
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#define CL756x 0x40000
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// crus
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#define CL6245 0x80000
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||
//myf32 end
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//
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// Actual Revision IDs for certain cirrus chips
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||
//
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#define CL5429_ID 0x27
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#define CL5428_ID 0x26
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#define CL5430_ID 0x28
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||
#define CL5434_ID 0x2A
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||
#define CL5436_ID 0x2B
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//sge04
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||
#define CL5446_ID 0x2E
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#define CL5480_ID 0x2F
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||
//myf32 begin
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||
#define CL7542_ID 0x2C
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#define CL7541_ID 0x34
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#define CL7543_ID 0x30
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#define CL7548_ID 0x38
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||
#define CL7555_ID 0x40
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#define CL7556_ID 0x4C
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||
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||
//#define CHIP754X (CL7541_ID | CL7542_ID | CL7543_ID | CL7548_ID)
|
||
//#define CHIP755X (CL7555_ID | CL7556_ID)
|
||
//myf32 end
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||
|
||
//
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||
// Driver Specific Attribute Flags
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||
//
|
||
|
||
#define CAPS_NO_HOST_XFER 0x00000002 // Do not use host xfers to
|
||
// the blt engine.
|
||
#define CAPS_SW_POINTER 0x00000004 // Use software pointer.
|
||
#define CAPS_TRUE_COLOR 0x00000008 // Set upper color registers.
|
||
#define CAPS_MM_IO 0x00000010 // Use memory mapped IO.
|
||
#define CAPS_BLT_SUPPORT 0x00000020 // BLTs are supported
|
||
#define CAPS_IS_542x 0x00000040 // This is a 542x
|
||
#define CAPS_AUTOSTART 0x00000080 // Autostart feature support.
|
||
#define CAPS_CURSOR_VERT_EXP 0x00000100 // Flag set if 8x6 panel,
|
||
#define CAPS_DSTN_PANEL 0x00000200 // DSTN panel in use, ms0809.
|
||
#define CAPS_VIDEO 0x00000400 // Video support.
|
||
#define CAPS_SECOND_APERTURE 0x00000800 // Second aperture support.
|
||
#define CAPS_COMMAND_LIST 0x00001000 // Command List support.
|
||
#define CAPS_GAMMA_CORRECT 0x00002000 // Color correction
|
||
#define CAPS_VGA_PANEL 0x00004000 // use 6x4 VGA PANEL.
|
||
#define CAPS_SVGA_PANEL 0x00008000 // use 8x6 SVGA PANEL.
|
||
#define CAPS_XGA_PANEL 0x00010000 // use 10x7 XGA PANEL.
|
||
#define CAPS_PANNING 0x00020000 // Panning scrolling supported.
|
||
#define CAPS_TV_ON 0x00040000 // TV turn on supported., myf33
|
||
#define CAPS_TRANSPARENCY 0x00080000 // Transparency is supported
|
||
#define CAPS_ENGINEMANAGED 0x00100000 // Engine managed surface
|
||
//myf16, end
|
||
//crus end
|
||
|
||
|
||
// bitfields for the DisplayType
|
||
#define crt 0x0001
|
||
#define panel 0x0002
|
||
|
||
#define panel8x6 0x0004
|
||
#define panel10x7 0x0008
|
||
|
||
#define TFT_LCD 0x0100
|
||
#define STN_LCD 0x0200
|
||
#define Mono_LCD 0x0400
|
||
#define Color_LCD 0x0800
|
||
#define Single_LCD 0x1000
|
||
#define Dual_LCD 0x2000
|
||
#define Jump_type 0x8000 //myf27
|
||
|
||
//crus
|
||
#define DefaultMode 0x9 //myf19: 11-07-96 if panel can't support mode,
|
||
// use 640x480x256c(0x5F) replace.
|
||
//
|
||
// Indexes into array of mode table pointers
|
||
//
|
||
|
||
#define pCL6410_crt 0
|
||
#define pCL6410_panel 1
|
||
#define pCL6420_crt 2
|
||
#define pCL6420_panel 3
|
||
#define pCL542x 4
|
||
#define pCL543x 5
|
||
#define pStretchScan 6
|
||
#define pNEC_CL543x 7
|
||
#define NUM_CHIPTYPES 8
|
||
|
||
typedef struct {
|
||
USHORT BiosModeCL6410; // bios modes are different across the
|
||
USHORT BiosModeCL6420; // products. that's why we need multiple
|
||
USHORT BiosModeCL542x; // values.
|
||
} CLMODE, *PCLMODE;
|
||
|
||
//
|
||
// Structure used to describe each video mode in ModesVGA[].
|
||
//
|
||
|
||
typedef struct {
|
||
USHORT fbType; // color or monochrome, text or graphics, via
|
||
// VIDEO_MODE_COLOR and VIDEO_MODE_GRAPHICS
|
||
USHORT numPlanes; // # of video memory planes
|
||
USHORT bitsPerPlane; // # of bits of color in each plane
|
||
SHORT col; // # of text columns across screen with default font
|
||
SHORT row; // # of text rows down screen with default font
|
||
USHORT hres; // # of pixels across screen
|
||
USHORT vres; // # of scan lines down screen
|
||
USHORT wbytes; // # of bytes from start of one scan line to start of next
|
||
ULONG sbytes; // total size of addressable display memory in bytes
|
||
ULONG Frequency; // Vertical Frequency
|
||
ULONG Interlaced; // Determines if the mode is interlaced or not
|
||
ULONG MonitorType; // Sets the desired vertical freq in an int10
|
||
ULONG MonTypeAX; // Sets the desired horizontal freq in an int10
|
||
ULONG MonTypeBX;
|
||
ULONG MonTypeCX;
|
||
BOOLEAN HWCursorEnable; // Flag to disable cursor if necessary
|
||
BANK_TYPE banktype; // NoBanking, NormalBanking, PlanarHCBanking
|
||
VIDEO_MEMORY_MAP MemMap; // index from VIDEO_MEMORY_MAP of memory
|
||
// mapping used by this mode
|
||
ULONG ChipType; // flags that say which chipset runs this mode
|
||
//myf32 change USHORT to ULONG
|
||
USHORT DisplayType; // display type this mode runs on(crt or panel)
|
||
BOOLEAN ValidMode; // TRUE if mode valid, FALSE if not
|
||
BOOLEAN LinearSupport; // TRUE if this mode can have its memory
|
||
// mapped in linearly.
|
||
|
||
CLMODE BiosModes;
|
||
|
||
//
|
||
// the mode will be TRUE if there is enough video memory to support the
|
||
// mode, and the display type(it could be a panel), will support the mode.
|
||
// PANELS only support 640x480 for now.
|
||
//
|
||
PUSHORT CmdStrings[NUM_CHIPTYPES]; // pointer to array of register-setting commands to
|
||
// set up mode
|
||
} VIDEOMODE, *PVIDEOMODE;
|
||
|
||
//
|
||
// Mode into which to put the VGA before starting a VDM, so it's a plain
|
||
// vanilla VGA. (This is the mode's index in ModesVGA[], currently standard
|
||
// 80x25 text mode.)
|
||
//
|
||
|
||
#define DEFAULT_MODE 0
|
||
|
||
//crus, begin
|
||
//myf1, begin
|
||
#ifdef PANNING_SCROLL
|
||
typedef struct {
|
||
USHORT Hres;
|
||
USHORT Vres;
|
||
USHORT BitsPerPlane;
|
||
USHORT ModesVgaStart;
|
||
USHORT Mode;
|
||
} RESTABLE, *PRESTABLE;
|
||
|
||
typedef struct {
|
||
USHORT hres;
|
||
USHORT vres;
|
||
USHORT wbytes;
|
||
USHORT bpp;
|
||
SHORT flag;
|
||
} PANNMODE;
|
||
|
||
USHORT ViewPoint_Mode = 0x5F;
|
||
#endif
|
||
|
||
|
||
UCHAR HWcur, HWicon0, HWicon1, HWicon2, HWicon3; //myf11
|
||
//myf1, end
|
||
//crus, end
|
||
|
||
|
||
//
|
||
// Info used by the Validator functions and save/restore code.
|
||
// Structure used to trap register accesses that must be done atomically.
|
||
//
|
||
|
||
#define VGA_MAX_VALIDATOR_DATA 100
|
||
|
||
#define VGA_VALIDATOR_UCHAR_ACCESS 1
|
||
#define VGA_VALIDATOR_USHORT_ACCESS 2
|
||
#define VGA_VALIDATOR_ULONG_ACCESS 3
|
||
|
||
typedef struct _VGA_VALIDATOR_DATA {
|
||
ULONG Port;
|
||
UCHAR AccessType;
|
||
ULONG Data;
|
||
} VGA_VALIDATOR_DATA, *PVGA_VALIDATOR_DATA;
|
||
|
||
//
|
||
// Number of bytes to save in each plane.
|
||
//
|
||
|
||
#define VGA_PLANE_SIZE 0x10000
|
||
|
||
//
|
||
// Number of each type of indexed register in a standard VGA, used by
|
||
// validator and state save/restore functions.
|
||
//
|
||
// Note: VDMs currently only support basic VGAs only.
|
||
//
|
||
|
||
#define VGA_NUM_SEQUENCER_PORTS 5
|
||
#define VGA_NUM_CRTC_PORTS 25
|
||
#define VGA_NUM_GRAPH_CONT_PORTS 9
|
||
#define VGA_NUM_ATTRIB_CONT_PORTS 21
|
||
#define VGA_NUM_DAC_ENTRIES 256
|
||
|
||
#ifdef EXTENDED_REGISTER_SAVE_RESTORE
|
||
|
||
//
|
||
// Indices to start save/restore in extension registers:
|
||
// For both chip types
|
||
|
||
#define CL64xx_GRAPH_EXT_START 0x0b // does not include ext. enable
|
||
#define CL64xx_GRAPH_EXT_END 0xFF
|
||
|
||
#define CL542x_GRAPH_EXT_START 0x09
|
||
#define CL542x_GRAPH_EXT_END 0x39
|
||
#define CL542x_SEQUENCER_EXT_START 0x07 // does not include ext. enable
|
||
#define CL542x_SEQUENCER_EXT_END 0x1F
|
||
#define CL542x_CRTC_EXT_START 0x19
|
||
#define CL542x_CRTC_EXT_END 0x1B
|
||
|
||
//
|
||
// Number of extended regs for both chip types
|
||
//
|
||
|
||
#define CL64xx_NUM_GRAPH_EXT_PORTS (CL64xx_GRAPH_EXT_END - CL64xx_GRAPH_EXT_START + 1)
|
||
|
||
#define CL542x_NUM_GRAPH_EXT_PORTS (CL542x_GRAPH_EXT_END - CL542x_GRAPH_EXT_START + 1)
|
||
#define CL542x_NUM_SEQUENCER_EXT_PORTS (CL542x_SEQUENCER_EXT_END - CL542x_SEQUENCER_EXT_START + 1)
|
||
#define CL542x_NUM_CRTC_EXT_PORTS (CL542x_CRTC_EXT_END - CL542x_CRTC_EXT_START + 1)
|
||
|
||
//
|
||
// set values for save/restore area based on largest value for a chipset.
|
||
//
|
||
|
||
#define EXT_NUM_GRAPH_CONT_PORTS ((CL64xx_NUM_GRAPH_EXT_PORTS > \
|
||
CL542x_NUM_GRAPH_EXT_PORTS) ? \
|
||
CL64xx_NUM_GRAPH_EXT_PORTS : \
|
||
CL542x_NUM_GRAPH_EXT_PORTS)
|
||
#define EXT_NUM_SEQUENCER_PORTS CL542x_NUM_SEQUENCER_EXT_PORTS
|
||
#define EXT_NUM_CRTC_PORTS CL542x_NUM_CRTC_EXT_PORTS
|
||
#define EXT_NUM_ATTRIB_CONT_PORTS 0
|
||
#define EXT_NUM_DAC_ENTRIES 0
|
||
|
||
#else
|
||
|
||
#define EXT_NUM_GRAPH_CONT_PORTS 0
|
||
#define EXT_NUM_SEQUENCER_PORTS 0
|
||
#define EXT_NUM_CRTC_PORTS 0
|
||
#define EXT_NUM_ATTRIB_CONT_PORTS 0
|
||
#define EXT_NUM_DAC_ENTRIES 0
|
||
|
||
#endif
|
||
|
||
//
|
||
// These constants determine the offsets within the
|
||
// VIDEO_HARDWARE_STATE_HEADER structure that are used to save and
|
||
// restore the VGA's state.
|
||
//
|
||
|
||
#define VGA_HARDWARE_STATE_SIZE sizeof(VIDEO_HARDWARE_STATE_HEADER)
|
||
|
||
#define VGA_BASIC_SEQUENCER_OFFSET (VGA_HARDWARE_STATE_SIZE + 0)
|
||
#define VGA_BASIC_CRTC_OFFSET (VGA_BASIC_SEQUENCER_OFFSET + \
|
||
VGA_NUM_SEQUENCER_PORTS)
|
||
#define VGA_BASIC_GRAPH_CONT_OFFSET (VGA_BASIC_CRTC_OFFSET + \
|
||
VGA_NUM_CRTC_PORTS)
|
||
#define VGA_BASIC_ATTRIB_CONT_OFFSET (VGA_BASIC_GRAPH_CONT_OFFSET + \
|
||
VGA_NUM_GRAPH_CONT_PORTS)
|
||
#define VGA_BASIC_DAC_OFFSET (VGA_BASIC_ATTRIB_CONT_OFFSET + \
|
||
VGA_NUM_ATTRIB_CONT_PORTS)
|
||
#define VGA_BASIC_LATCHES_OFFSET (VGA_BASIC_DAC_OFFSET + \
|
||
(3 * VGA_NUM_DAC_ENTRIES))
|
||
|
||
#define VGA_EXT_SEQUENCER_OFFSET (VGA_BASIC_LATCHES_OFFSET + 4)
|
||
#define VGA_EXT_CRTC_OFFSET (VGA_EXT_SEQUENCER_OFFSET + \
|
||
EXT_NUM_SEQUENCER_PORTS)
|
||
#define VGA_EXT_GRAPH_CONT_OFFSET (VGA_EXT_CRTC_OFFSET + \
|
||
EXT_NUM_CRTC_PORTS)
|
||
#define VGA_EXT_ATTRIB_CONT_OFFSET (VGA_EXT_GRAPH_CONT_OFFSET +\
|
||
EXT_NUM_GRAPH_CONT_PORTS)
|
||
#define VGA_EXT_DAC_OFFSET (VGA_EXT_ATTRIB_CONT_OFFSET + \
|
||
EXT_NUM_ATTRIB_CONT_PORTS)
|
||
|
||
#define VGA_VALIDATOR_OFFSET (VGA_EXT_DAC_OFFSET + 4 * EXT_NUM_DAC_ENTRIES)
|
||
|
||
#define VGA_VALIDATOR_AREA_SIZE sizeof (ULONG) + (VGA_MAX_VALIDATOR_DATA * \
|
||
sizeof (VGA_VALIDATOR_DATA)) + \
|
||
sizeof (ULONG) + \
|
||
sizeof (ULONG) + \
|
||
sizeof (PVIDEO_ACCESS_RANGE)
|
||
|
||
#define VGA_MISC_DATA_AREA_OFFSET VGA_VALIDATOR_OFFSET + VGA_VALIDATOR_AREA_SIZE
|
||
|
||
#define VGA_MISC_DATA_AREA_SIZE 0
|
||
|
||
#define VGA_PLANE_0_OFFSET VGA_MISC_DATA_AREA_OFFSET + VGA_MISC_DATA_AREA_SIZE
|
||
|
||
#define VGA_PLANE_1_OFFSET VGA_PLANE_0_OFFSET + VGA_PLANE_SIZE
|
||
#define VGA_PLANE_2_OFFSET VGA_PLANE_1_OFFSET + VGA_PLANE_SIZE
|
||
#define VGA_PLANE_3_OFFSET VGA_PLANE_2_OFFSET + VGA_PLANE_SIZE
|
||
|
||
//
|
||
// Space needed to store all state data.
|
||
//
|
||
|
||
#define VGA_TOTAL_STATE_SIZE VGA_PLANE_3_OFFSET + VGA_PLANE_SIZE
|
||
|
||
//
|
||
// Merge port and register access for VGA relocatable and MMIO registers
|
||
//
|
||
// sge03
|
||
typedef VIDEOPORT_API UCHAR (*FnVideoPortReadPortUchar)(PUCHAR Port);
|
||
typedef VIDEOPORT_API USHORT (*FnVideoPortReadPortUshort)(PUSHORT Port);
|
||
typedef VIDEOPORT_API ULONG (*FnVideoPortReadPortUlong)(PULONG Port);
|
||
typedef VIDEOPORT_API VOID (*FnVideoPortWritePortUchar)(PUCHAR Port, UCHAR Value);
|
||
typedef VIDEOPORT_API VOID (*FnVideoPortWritePortUshort)(PUSHORT Port, USHORT Value);
|
||
typedef VIDEOPORT_API VOID (*FnVideoPortWritePortUlong)(PULONG Port, ULONG Value);
|
||
|
||
typedef struct _PORT_READ_WRITE_FUNTION_TABLE
|
||
{
|
||
FnVideoPortReadPortUchar pfnVideoPortReadPortUchar;
|
||
FnVideoPortReadPortUshort pfnVideoPortReadPortUshort;
|
||
FnVideoPortReadPortUlong pfnVideoPortReadPortUlong;
|
||
FnVideoPortWritePortUchar pfnVideoPortWritePortUchar;
|
||
FnVideoPortWritePortUshort pfnVideoPortWritePortUshort;
|
||
FnVideoPortWritePortUlong pfnVideoPortWritePortUlong;
|
||
} PORT_READ_WRITE_FUNTION_TABLE;
|
||
|
||
|
||
|
||
//
|
||
// Device extension for the driver object. This data is only used
|
||
// locally, so this structure can be added to as needed.
|
||
//
|
||
|
||
typedef struct _HW_DEVICE_EXTENSION {
|
||
|
||
PHYSICAL_ADDRESS PhysicalVideoMemoryBase; // physical memory address and
|
||
PHYSICAL_ADDRESS PhysicalFrameOffset; // physical memory address and
|
||
ULONG PhysicalVideoMemoryLength; // length of display memory
|
||
ULONG PhysicalFrameLength; // length of display memory for
|
||
// the current mode.
|
||
|
||
PUCHAR IOAddress; // base I/O address of VGA ports
|
||
PUCHAR VideoMemoryAddress; // base virtual memory address of VGA memory
|
||
ULONG NumAvailableModes; // number of available modes this session
|
||
ULONG ModeIndex; // index of current mode in ModesVGA[]
|
||
PVIDEOMODE CurrentMode; // pointer to VIDEOMODE structure for
|
||
// current mode
|
||
|
||
USHORT FontPelColumns; // Width of the font in pels
|
||
USHORT FontPelRows; // height of the font in pels
|
||
|
||
USHORT cursor_vert_exp_flag;
|
||
|
||
VIDEO_CURSOR_POSITION CursorPosition; // current cursor position
|
||
|
||
|
||
UCHAR CursorEnable; // whether cursor is enabled or not
|
||
UCHAR CursorTopScanLine; // Cursor Start register setting (top scan)
|
||
UCHAR CursorBottomScanLine; // Cursor End register setting (bottom scan)
|
||
|
||
// add HW cursor data here
|
||
BOOLEAN VideoPointerEnabled; // Whether HW Cursor is supported
|
||
|
||
ULONG ChipType; // CL6410, CL6420, CL542x, or CL543x
|
||
//myf32 change USHORT to ULONG
|
||
USHORT ChipRevision; // chip revision value
|
||
INTERFACE_TYPE BusType; // isa, pci, etc.
|
||
USHORT DisplayType; // crt, panel or panel8x6
|
||
USHORT BoardType; // Diamond, etc ...
|
||
WCHAR LegacyPnPId[8]; // legacy PnP ID
|
||
ULONG AdapterMemorySize; // amount of installed video ram
|
||
BOOLEAN LinearMode; // TRUE if memory is mapped linear
|
||
BOOLEAN BiosGT130; // Do we have a 1.30 or higher bios
|
||
BOOLEAN BIOSPresent; // Indicates whether a bios is present
|
||
BOOLEAN AutoFeature; // Autostart on 54x6
|
||
|
||
// crus
|
||
BOOLEAN BitBLTEnhance; // BitBLT enhancement includes
|
||
// XY-position, XY-clipping and
|
||
// command list in off-screen memory
|
||
// For CL-GD5480, it is TRUE,
|
||
// otherwise, it is FALSE.
|
||
|
||
//
|
||
// The following two values are used to pass information to the
|
||
// IO Callback called by IOWaitDisplEnableThenWrite.
|
||
//
|
||
|
||
ULONG DEPort; // stores the port address to write to
|
||
UCHAR DEValue; // stores the value to write
|
||
|
||
//
|
||
// These 4 fields must be at the end of the device extension and must be
|
||
// kept in this order since this data will be copied to and from the save
|
||
// state buffer that is passed to and from the VDM.
|
||
//
|
||
|
||
ULONG TrappedValidatorCount; // number of entries in the Trapped
|
||
// validator data Array.
|
||
VGA_VALIDATOR_DATA TrappedValidatorData[VGA_MAX_VALIDATOR_DATA];
|
||
// Data trapped by the validator routines
|
||
// but not yet played back into the VGA
|
||
// register.
|
||
|
||
ULONG SequencerAddressValue; // Determines if the Sequencer Address Port
|
||
// is currently selecting the SyncReset data
|
||
// register.
|
||
|
||
ULONG CurrentNumVdmAccessRanges; // Number of access ranges in
|
||
// the access range array pointed
|
||
// to by the next field
|
||
PVIDEO_ACCESS_RANGE CurrentVdmAccessRange; // Access range currently
|
||
// associated to the VDM
|
||
// sge01 PC97 Compliant
|
||
ULONG ulBIOSVersionNumber; // BIOS version number.
|
||
|
||
BOOLEAN bMMAddress; // VGA register MMIO
|
||
|
||
BOOLEAN bSecondAperture; // TRUE if chips have second apterture
|
||
// else FALSE, sge02
|
||
//crus, begin
|
||
//myf12, for hoy-key support
|
||
SHORT bBlockSwitch; //display switch block flag //myf12
|
||
SHORT bDisplaytype; //display type, 0:LCD, 1:CRT, 2:SIM //myf12
|
||
ULONG bCurrentMode; //Current Mode
|
||
//crus end
|
||
|
||
PORT_READ_WRITE_FUNTION_TABLE gPortRWfn;
|
||
|
||
ULONG PMCapability;
|
||
|
||
} HW_DEVICE_EXTENSION, *PHW_DEVICE_EXTENSION;
|
||
|
||
|
||
//
|
||
// Function prototypes.
|
||
//
|
||
|
||
//
|
||
// Entry points for the VGA validator. Used in VgaEmulatorAccessEntries[].
|
||
//
|
||
|
||
VP_STATUS
|
||
VgaValidatorUcharEntry (
|
||
ULONG_PTR Context,
|
||
ULONG Port,
|
||
UCHAR AccessMode,
|
||
PUCHAR Data
|
||
);
|
||
|
||
VP_STATUS
|
||
VgaValidatorUshortEntry (
|
||
ULONG_PTR Context,
|
||
ULONG Port,
|
||
UCHAR AccessMode,
|
||
PUSHORT Data
|
||
);
|
||
|
||
VP_STATUS
|
||
VgaValidatorUlongEntry (
|
||
ULONG_PTR Context,
|
||
ULONG Port,
|
||
UCHAR AccessMode,
|
||
PULONG Data
|
||
);
|
||
|
||
BOOLEAN
|
||
VgaPlaybackValidatorData (
|
||
PVOID Context
|
||
);
|
||
|
||
#ifdef _X86_
|
||
|
||
//
|
||
// Bank switch code start and end labels, defined in CLHARD.ASM
|
||
//
|
||
// three versions for Cirrus Logic products
|
||
//
|
||
|
||
extern UCHAR CL64xxBankSwitchStart;
|
||
extern UCHAR CL64xxBankSwitchEnd;
|
||
extern UCHAR CL64xxPlanarHCBankSwitchStart;
|
||
extern UCHAR CL64xxPlanarHCBankSwitchEnd;
|
||
extern UCHAR CL64xxEnablePlanarHCStart;
|
||
extern UCHAR CL64xxEnablePlanarHCEnd;
|
||
extern UCHAR CL64xxDisablePlanarHCStart;
|
||
extern UCHAR CL64xxDisablePlanarHCEnd;
|
||
|
||
extern UCHAR CL542xBankSwitchStart;
|
||
extern UCHAR CL542xBankSwitchEnd;
|
||
extern UCHAR CL542xPlanarHCBankSwitchStart;
|
||
extern UCHAR CL542xPlanarHCBankSwitchEnd;
|
||
extern UCHAR CL542xEnablePlanarHCStart;
|
||
extern UCHAR CL542xEnablePlanarHCEnd;
|
||
extern UCHAR CL542xDisablePlanarHCStart;
|
||
extern UCHAR CL542xDisablePlanarHCEnd;
|
||
|
||
extern UCHAR CL543xBankSwitchStart;
|
||
extern UCHAR CL543xBankSwitchEnd;
|
||
extern UCHAR CL543xPlanarHCBankSwitchStart;
|
||
extern UCHAR CL543xPlanarHCBankSwitchEnd;
|
||
|
||
#endif
|
||
|
||
//
|
||
// Vga init scripts for font loading
|
||
//
|
||
|
||
extern USHORT EnableA000Data[];
|
||
extern USHORT DisableA000Color[];
|
||
|
||
//
|
||
// Mode Information
|
||
//
|
||
|
||
extern MEMORYMAPS MemoryMaps[];
|
||
extern ULONG NumVideoModes;
|
||
extern VIDEOMODE ModesVGA[];
|
||
|
||
//crus, begin
|
||
//myf1, begin
|
||
#ifdef PANNING_SCROLL
|
||
extern RESTABLE ResolutionTable[];
|
||
extern PANNMODE PanningMode;
|
||
extern USHORT ViewPoint_Mode;
|
||
|
||
#endif
|
||
|
||
extern SHORT Panning_flag;
|
||
//myf1, end
|
||
//crus, end
|
||
|
||
#define NUM_VGA_ACCESS_RANGES 5
|
||
extern VIDEO_ACCESS_RANGE VgaAccessRange[];
|
||
|
||
#define VGA_NUM_EMULATOR_ACCESS_ENTRIES 6
|
||
extern EMULATOR_ACCESS_ENTRY VgaEmulatorAccessEntries[];
|
||
|
||
#define NUM_MINIMAL_VGA_VALIDATOR_ACCESS_RANGE 4
|
||
extern VIDEO_ACCESS_RANGE MinimalVgaValidatorAccessRange[];
|
||
|
||
#define NUM_FULL_VGA_VALIDATOR_ACCESS_RANGE 2
|
||
extern VIDEO_ACCESS_RANGE FullVgaValidatorAccessRange[];
|
||
|
||
//
|
||
// sr754x (NORDIC) prototypes
|
||
//
|
||
|
||
VP_STATUS
|
||
NordicSaveRegs(
|
||
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
||
PUSHORT NordicSaveArea
|
||
);
|
||
|
||
VP_STATUS
|
||
NordicRestoreRegs(
|
||
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
||
PUSHORT NordicSaveArea
|
||
);
|
||
|
||
#define VideoPortReadPortUchar(Port) HwDeviceExtension->gPortRWfn.pfnVideoPortReadPortUchar(Port)
|
||
#define VideoPortReadPortUshort(Port) HwDeviceExtension->gPortRWfn.pfnVideoPortReadPortUshort(Port)
|
||
#define VideoPortReadPortUlong(Port) HwDeviceExtension->gPortRWfn.pfnVideoPortReadPortUlong(Port)
|
||
#define VideoPortWritePortUchar(Port, Value) HwDeviceExtension->gPortRWfn.pfnVideoPortWritePortUchar(Port, Value)
|
||
#define VideoPortWritePortUshort(Port, Value) HwDeviceExtension->gPortRWfn.pfnVideoPortWritePortUshort(Port, Value)
|
||
#define VideoPortWritePortUlong(Port, Value) HwDeviceExtension->gPortRWfn.pfnVideoPortWritePortUlong(Port, Value)
|
||
|
||
typedef struct _PGAMMA_VALUE // chu02
|
||
{
|
||
UCHAR value[4] ;
|
||
|
||
} GAMMA_VALUE, *PGAMMA_VALUE, *PCONTRAST_VALUE ;
|
||
|
||
ULONG
|
||
GetAttributeFlags(
|
||
PHW_DEVICE_EXTENSION HwDeviceExtension
|
||
);
|
||
|
||
typedef struct _POEMMODE_EXCLUDE // chu03
|
||
{
|
||
UCHAR mode ;
|
||
UCHAR refresh ;
|
||
BOOLEAN NeverAccessed ;
|
||
|
||
} OEMMODE_EXCLUDE, *PMODE_EXCLUDE ;
|
||
|
||
|
||
//
|
||
// New NT 5.0 Functions
|
||
//
|
||
|
||
ULONG
|
||
CirrusGetChildDescriptor(
|
||
PVOID pHwDeviceExtension,
|
||
PVIDEO_CHILD_ENUM_INFO ChildEnumInfo,
|
||
PVIDEO_CHILD_TYPE pChildType,
|
||
PVOID pvChildDescriptor,
|
||
PULONG pHwId,
|
||
PULONG pUnused
|
||
);
|
||
|
||
VP_STATUS
|
||
CirrusGetPowerState(
|
||
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
||
ULONG HwDeviceId,
|
||
PVIDEO_POWER_MANAGEMENT VideoPowerManagement
|
||
);
|
||
|
||
VP_STATUS
|
||
CirrusSetPowerState(
|
||
PHW_DEVICE_EXTENSION HwDeviceExtension,
|
||
ULONG HwDeviceId,
|
||
PVIDEO_POWER_MANAGEMENT VideoPowerManagement
|
||
);
|
||
|
||
#define VESA_POWER_FUNCTION 0x4f10
|
||
#define VESA_POWER_ON 0x0000
|
||
#define VESA_POWER_STANDBY 0x0100
|
||
#define VESA_POWER_SUSPEND 0x0200
|
||
#define VESA_POWER_OFF 0x0400
|
||
#define VESA_GET_POWER_FUNC 0x0000
|
||
#define VESA_SET_POWER_FUNC 0x0001
|
||
#define VESA_STATUS_SUCCESS 0x004f
|