283 lines
9.2 KiB
C
283 lines
9.2 KiB
C
//---------------------------------------------------------------------------
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/*++
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Copyright (c) 1994 Cirrus Logic, Inc.
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Module Name:
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sr754x.c
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Abstract:
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This module performs the save/restore operations specific to the
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CL-GD754x chipset (aka Nordic).
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Environment:
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kernel mode only
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Notes:
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Revision History:
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13Oct94 mrh Initial version
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--*/
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//---------------------------------------------------------------------------
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#include "dderror.h"
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#include "devioctl.h"
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#include "miniport.h"
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#include "ntddvdeo.h"
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#include "video.h"
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#include "cirrus.h"
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#include "sr754x.h"
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#if defined(ALLOC_PRAGMA)
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#pragma alloc_text(PAGE,NordicSaveRegs)
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#pragma alloc_text(PAGE,NordicRestoreRegs)
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#endif
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VP_STATUS NordicSaveRegs(
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PHW_DEVICE_EXTENSION HwDeviceExtension,
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PUSHORT pNordicSaveArea
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)
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{
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UCHAR i;
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UCHAR PortVal, Save2C, Save2D;
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PUCHAR CRTCAddressPort, CRTCDataPort;
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PUSHORT pSaveBuf;
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UCHAR vShadowIndex[CL754x_NUM_VSHADOW] = {0x06,0x07,0x10,0x11,0x15,0x16};
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UCHAR zShadowIndex[CL754x_NUM_ZSHADOW] = {0,2,3,4,5};
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UCHAR yShadowIndex[CL754x_NUM_YSHADOW] = {0,2,3,4,5};
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UCHAR xShadowIndex[CL754x_NUM_XSHADOW] = {2,3,4,5,6,7,8,9,0x0B,0x0C,0x0D,0x0E};
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//
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// Determine where the CRTC registers are addressed (color or mono).
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//
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CRTCAddressPort = HwDeviceExtension->IOAddress;
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CRTCDataPort = HwDeviceExtension->IOAddress;
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if (VideoPortReadPortUchar(HwDeviceExtension->IOAddress +
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MISC_OUTPUT_REG_READ_PORT) & 0x01)
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{
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CRTCAddressPort += CRTC_ADDRESS_PORT_COLOR;
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CRTCDataPort += CRTC_DATA_PORT_COLOR;
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}
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else
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{
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CRTCAddressPort += CRTC_ADDRESS_PORT_MONO;
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CRTCDataPort += CRTC_DATA_PORT_MONO;
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}
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VideoPortWritePortUchar(CRTCAddressPort, IND_CR2D);
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Save2D = (VideoPortReadPortUchar(CRTCDataPort));
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VideoPortWritePortUchar(CRTCAddressPort, IND_CR2C);
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Save2C = (VideoPortReadPortUchar(CRTCDataPort));
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pSaveBuf = pNordicSaveArea;
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//Initialize the control registers to access shadowed vertical regs:
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// CR2C[3] = {0} Allows access to Vert regs (CR6,CR7,CR10,CR11,CR15,CR16)
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// CR2D[7] = {0} Blocks access to LCD timing regs (R2X-REX)
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((Save2C & ~0x08) << 8) | IND_CR2C));
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((Save2D & ~0x80) << 8) | IND_CR2D));
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for (i = 0; i < CL754x_NUM_VSHADOW; i++)
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{
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VideoPortWritePortUchar (CRTCAddressPort, vShadowIndex[i]);
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*pSaveBuf++ = (USHORT)((VideoPortReadPortUchar (CRTCDataPort)) << 8) |
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vShadowIndex[i];
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}
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for (i = CL754x_CRTC_EXT_START; i <= CL754x_CRTC_EXT_END; i++)
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{
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VideoPortWritePortUchar (CRTCAddressPort, i);
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*pSaveBuf++ = (USHORT)((VideoPortReadPortUchar (CRTCDataPort)) << 8) | i;
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}
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for (i = CL754x_HRZ_TIME_START; i <= CL754x_HRZ_TIME_END; i++)
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{
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VideoPortWritePortUchar (CRTCAddressPort, i);
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*pSaveBuf++ = (USHORT)((VideoPortReadPortUchar (CRTCDataPort)) << 8) | i;
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}
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// Set CR2D [7] to {0} and CR2C[5,4] to {1,0}
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// These values provide access to Y shadow registers
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((Save2D & ~0x80) << 8) | IND_CR2D));
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PortVal = Save2C & ~0x30; // We'll use PortVal again below
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((PortVal | 0x20) << 8) | IND_CR2C));
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for (i = 0; i < CL754x_NUM_YSHADOW; i++)
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{
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VideoPortWritePortUchar (CRTCAddressPort, yShadowIndex[i]);
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*pSaveBuf++ = (USHORT)((VideoPortReadPortUchar (CRTCDataPort)) << 8) |
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yShadowIndex[i];
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}
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// Set CR2C[5,4] to {1,1}
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// This will provide access to Z shadow registers
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((PortVal | 0x30) << 8 )| IND_CR2C));
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for (i = 0; i < CL754x_NUM_ZSHADOW; i++)
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{
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VideoPortWritePortUchar (CRTCAddressPort, zShadowIndex[i]);
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*pSaveBuf++ = (USHORT)((VideoPortReadPortUchar (CRTCDataPort)) << 8) |
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zShadowIndex[i];
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}
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// Set CR2C[5,4] to {0,0} and CR2D[7] to {1}
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// This will provide access to X shadow registers
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort, // PortVal=Save2C & ~0x30
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(USHORT)((PortVal << 8) | IND_CR2C));
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((Save2D | 0x80) << 8) | IND_CR2D));
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for (i = 0; i < CL754x_NUM_XSHADOW; i++)
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{
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VideoPortWritePortUchar (CRTCAddressPort, xShadowIndex[i]);
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*pSaveBuf++ = ((VideoPortReadPortUchar (CRTCDataPort)) << 8) |
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xShadowIndex[i];
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}
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//Restore the original values for CR2C and CR2D
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)((Save2D << 8) | IND_CR2D));
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)((Save2C << 8) | IND_CR2C));
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return NO_ERROR;
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}
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VP_STATUS NordicRestoreRegs(
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PHW_DEVICE_EXTENSION HwDeviceExtension,
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PUSHORT pNordicSaveArea
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)
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{
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ULONG i;
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UCHAR PortVal, Save2C, Save2D;
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PUSHORT pSaveBuf;
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PUCHAR CRTCAddressPort, CRTCDataPort;
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//
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// Determine where the CRTC registers are addressed (color or mono).
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//
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CRTCAddressPort = HwDeviceExtension->IOAddress;
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CRTCDataPort = HwDeviceExtension->IOAddress;
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if (VideoPortReadPortUchar(HwDeviceExtension->IOAddress +
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MISC_OUTPUT_REG_READ_PORT) & 0x01)
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{
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CRTCAddressPort += CRTC_ADDRESS_PORT_COLOR;
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CRTCDataPort += CRTC_DATA_PORT_COLOR;
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}
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else
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{
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CRTCAddressPort += CRTC_ADDRESS_PORT_MONO;
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CRTCDataPort += CRTC_DATA_PORT_MONO;
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}
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//Initialize the control registers to access shadowed vertical regs
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// CR11[7] = {0} Allows access to CR0-7
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// CR2C[3] = {0} Allows access to Vertical regs (CR6,CR7,CR10,CR11,CR15,CR16
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// CR2D[7] = {0} Blocks access to LCD timing regs (R2X-REX)
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//
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VideoPortWritePortUchar(CRTCAddressPort, IND_CRTC_PROTECT);
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VideoPortWritePortUchar(CRTCDataPort,
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(UCHAR) (VideoPortReadPortUchar(CRTCDataPort) & ~0x80));
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VideoPortWritePortUchar(CRTCAddressPort, IND_CR2C);
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VideoPortWritePortUchar(CRTCDataPort,
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(UCHAR) (VideoPortReadPortUchar(CRTCDataPort) & ~0x08));
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VideoPortWritePortUchar(CRTCAddressPort, IND_CR2D);
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VideoPortWritePortUchar(CRTCDataPort,
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(UCHAR) (VideoPortReadPortUchar(CRTCDataPort) & ~0x80));
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pSaveBuf = pNordicSaveArea;
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for (i = 0; i < CL754x_NUM_VSHADOW; i++)
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{
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort, (*pSaveBuf++));
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}
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// Make sure we didn't lock CR0-CR7
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//
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VideoPortWritePortUchar(CRTCAddressPort, IND_CRTC_PROTECT);
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VideoPortWritePortUchar(CRTCDataPort,
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(UCHAR) (VideoPortReadPortUchar(CRTCDataPort) & ~0x80));
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for (i=0; i < (CL754x_NUM_CRTC_EXT_PORTS + CL754x_NUM_HRZ_TIME_PORTS); i++)
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{
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort, (*pSaveBuf++));
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}
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// Set CR2D [7] to {0} and CR2C[5,4] to {1,0}; save current contents
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// These values provide access to Y shadow registers
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//
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VideoPortWritePortUchar(CRTCAddressPort, IND_CR2D);
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Save2D = (VideoPortReadPortUchar(CRTCDataPort));
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VideoPortWritePortUchar(CRTCDataPort, (UCHAR)(Save2D & ~0x80));
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VideoPortWritePortUchar(CRTCAddressPort, IND_CR2C);
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PortVal = Save2C = (VideoPortReadPortUchar(CRTCDataPort));
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PortVal &= ~0x30;
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PortVal |= 0x20;
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VideoPortWritePortUchar(CRTCDataPort, PortVal);
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for (i = 0; i < CL754x_NUM_YSHADOW; i++)
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{
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort, (*pSaveBuf++));
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}
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// Set CR2C[5,4] to {1,1}
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// This will provide access to Z shadow registers
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((PortVal | 0x30) << 8) | IND_CR2C) );
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for (i = 0; i < CL754x_NUM_ZSHADOW; i++)
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{
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort, (*pSaveBuf++));
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}
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// Set CR2C[5,4] to {0,0} and CR2D[7] to {1}
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// This will provide access to X shadow registers
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//
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((PortVal & ~0x30) << 8) | IND_CR2C) );
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort,
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(USHORT)(((Save2D | 0x80) << 8) | IND_CR2D) );
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for (i = 0; i < CL754x_NUM_XSHADOW; i++)
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{
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VideoPortWritePortUshort((PUSHORT)CRTCAddressPort, (*pSaveBuf++));
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}
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// Reset the Blitter, in case it's busy
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//
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VideoPortWritePortUshort((PUSHORT) (HwDeviceExtension->IOAddress +
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GRAPH_ADDRESS_PORT), 0x0430);
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VideoPortWritePortUshort((PUSHORT) (HwDeviceExtension->IOAddress +
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GRAPH_ADDRESS_PORT), 0x0030);
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VideoPortWritePortUshort((PUSHORT) CRTCAddressPort,
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(USHORT)((Save2C << 8) | IND_CR2C));
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VideoPortWritePortUshort((PUSHORT) CRTCAddressPort,
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(USHORT)((Save2D << 8) | IND_CR2D));
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return NO_ERROR;
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}
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