113 lines
5.2 KiB
C
113 lines
5.2 KiB
C
/******************************Module*Header*******************************\
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* Module Name: hw.h
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*
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* All the hardware specific driver file stuff.
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*
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* Copyright (c) 1992-1995 Microsoft Corporation
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\**************************************************************************/
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// Miscellaneous Registers used only at EGA/VGA initialization time
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#define MISC_OUTPUT 0x0C2 // Miscellaneous Output Register
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#define CRTC_ADDR 0x0D4 // CRTC Address Register for color mode
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#define CRTC_DATA 0x0D5 // CRTC Data Register for color mode
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#define GRAF_1_POS 0x0CC // Graphics 1 Address Register
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#define GRAF_2_POS 0x0CA // Graphics 2 Address Register
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#define ATTR_READ 0x0DA // Attribute Controler Read Address
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#define ATTR_WRITE 0x0C0 // Attribute Controler Write Address
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#define IN_STAT_0 0x0C2 // Input Status Register 0
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#define IN_STAT_1 0x0DA // Input Status Register 1
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// EGA/VGA Register Definitions.
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//
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// The following definitions are the EGA/VGA registers and values
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// used by this driver. All other registers are set up at
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// when the EGA/VGA is placed into graphics mode and never altered
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// afterwards.
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//
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// All unspecified bits in the following registers must be 0.
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#define EGA_BASE 0x300 // Base address of the EGA (3xx)
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#define VGA_BASE 0x300 // Base address of the VGA (3xx)
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// SEQUencer Registers Used
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#define SEQ_ADDR 0xC4 // SEQUencer Address Register
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#define SEQ_DATA 0xC5 // SEQUencer Data Register
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#define SEQ_MAP_MASK 0x02 // Write Plane Enable Mask
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#define MM_C0 0x01 // C0 plane enable
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#define MM_C1 0x02 // C1 plane enable
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#define MM_C2 0x04 // C2 plane enable
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#define MM_C3 0x08 // C3 plane enable
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#define MM_ALL 0x0f // All planes
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#define SEQ_MODE 0x04 // Memory Mode
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#define SM_ALPHA 0x01 // Char map select enable
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#define SM_EXTENDED 0x02 // Extended memory present
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#define SM_ODD_PLANE 0x04 // Odd/even bytes to same plane
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// Graphics Controller Registers Used
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#define GRAF_ADDR 0xCE // Graphics Controller Address Register
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#define GRAF_DATA 0xCF // Graphics Controller Data Register
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#define GRAF_SET_RESET 0x00 // Set/Reset Plane Color
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#define GRAF_ENAB_SR 0x01 // Set/Reset Enable
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#define GRAF_COL_COMP 0x02 // Color Compare Register
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#define GRAF_DATA_ROT 0x03 // Data Rotate Register
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#define DR_ROT_CNT 0x07 // Data Rotate Count
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#define DR_SET 0x00 // Data Unmodified
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#define DR_AND 0x08 // Data ANDed with latches
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#define DR_OR 0x10 // Data ORed with latches
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#define DR_XOR 0x18 // Data XORed with latches
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#define GRAF_READ_MAP 0x04 // Read Map Select Register
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#define RM_C0 0x00 // Read C0 plane
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#define RM_C1 0x01 // Read C1 plane
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#define RM_C2 0x02 // Read C2 plane
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#define RM_C3 0x03 // Read C3 plane
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#define GRAF_MODE 0x05 // Mode Register
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#define M_PROC_WRITE 0x00 // Write processor data rotated
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#define M_LATCH_WRITE 0x01 // Write latched data
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#define M_COLOR_WRITE 0x02 // Write processor data as color
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#define M_AND_WRITE 0x03 // Write (procdata AND bitmask)
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#define M_DATA_READ 0x00 // Read selected plane
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#define M_COLOR_READ 0x08 // Read color compare
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#define GRAF_MISC 0x06 // Miscellaneous Register
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#define MS_NON_ALPHA 0x01 // Char generator disabled
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#define MS_ODD_EVEN 0x02 // Map odd addresses to even
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#define MS_A0000_128K 0x00 // Memory present at A0000, 128kb
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#define MS_A0000_64K 0x04 // Memory present at A0000, 64kb
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#define MS_B0000_32K 0x08 // Memory present at B0000, 32kb
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#define MS_B8000_32K 0x0C // Memory present at B8000, 32kb
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#define MS_ADDR_MASK 0x0C
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#define GRAF_CDC 0x07 // Color Don't Care Register
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#define GRAF_BIT_MASK 0x08 // Bit Mask Register
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////////////////////////////////////////////////////////////////////////
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// Direct access macros
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//
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#define OUT_WORD(pjBase, addr, w) \
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{ \
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MEMORY_BARRIER(); \
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WRITE_PORT_USHORT((BYTE*) (pjBase) + (addr), (USHORT) (w)); \
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}
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#define OUT_BYTE(pjBase, addr, j) \
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{ \
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MEMORY_BARRIER(); \
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WRITE_PORT_UCHAR((BYTE*) (pjBase) + (addr), (UCHAR) (j)); \
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}
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#define WRITE_WORD(pwAddr, w) \
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WRITE_REGISTER_USHORT((USHORT*) (pwAddr), (USHORT) (w))
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#define WRITE_BYTE(pbAddr, b) \
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WRITE_REGISTER_UCHAR((UCHAR *) (pbAddr), (UCHAR) (b))
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