461 lines
12 KiB
C
461 lines
12 KiB
C
/******************************Module*Header*******************************\
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*
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* *******************
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* * GDI SAMPLE CODE *
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* *******************
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*
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* Module Name: debug.c
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*
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* Debug helper routines.
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*
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* Copyright (c) 1992-1998 Microsoft Corporation
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*
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\**************************************************************************/
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#include "precomp.h"
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#if DBG
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////////////////////////////////////////////////////////////////////////////
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// DEBUGGING INITIALIZATION CODE
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//
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// When you're bringing up your display for the first time, you can
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// recompile with 'DebugLevel' set to 100. That will cause absolutely
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// all DISPDBG messages to be displayed on the kernel debugger (this
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// is known as the "PrintF Approach to Debugging" and is about the only
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// viable method for debugging driver initialization code).
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LONG DebugLevel = 0; // Set to '100' to debug initialization code
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// (the default is '0')
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////////////////////////////////////////////////////////////////////////////
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LONG gcFifo = 0; // Number of currently free FIFO entries
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BOOL gbCrtcCriticalSection = FALSE;
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// Have we acquired the CRTC register
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// critical section?
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#define LARGE_LOOP_COUNT 10000000
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////////////////////////////////////////////////////////////////////////////
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// Miscellaneous Driver Debug Routines
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////////////////////////////////////////////////////////////////////////////
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/*****************************************************************************
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*
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* Routine Description:
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*
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* This function is variable-argument, level-sensitive debug print
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* routine.
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* If the specified debug level for the print statement is lower or equal
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* to the current debug level, the message will be printed.
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*
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* Arguments:
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*
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* DebugPrintLevel - Specifies at which debugging level the string should
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* be printed
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*
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* DebugMessage - Variable argument ascii c string
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*
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* Return Value:
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*
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* None.
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*
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***************************************************************************/
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VOID
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DebugPrint(
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LONG DebugPrintLevel,
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PCHAR DebugMessage,
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...
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)
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{
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va_list ap;
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va_start(ap, DebugMessage);
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if (DebugPrintLevel <= DebugLevel)
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{
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EngDebugPrint(STANDARD_DEBUG_PREFIX, DebugMessage, ap);
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EngDebugPrint("", "\n", ap);
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}
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va_end(ap);
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} // DebugPrint()
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/******************************Public*Routine******************************\
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* VOID vCheckDataComplete
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\**************************************************************************/
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VOID vCheckDataReady(
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PDEV* ppdev)
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{
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ASSERTDD((IO_GP_STAT(ppdev) & HARDWARE_BUSY),
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"Not ready for data transfer.");
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}
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/******************************Public*Routine******************************\
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* VOID vCheckDataComplete
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\**************************************************************************/
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VOID vCheckDataComplete(
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PDEV* ppdev)
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{
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LONG i;
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// We loop because it may take a while for the hardware to finish
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// digesting all the data we transferred:
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for (i = LARGE_LOOP_COUNT; i > 0; i--)
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{
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if (!(IO_GP_STAT(ppdev) & HARDWARE_BUSY))
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return;
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}
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RIP("Data transfer not complete.");
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}
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/******************************Public*Routine******************************\
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* VOID vOutFifoW
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\**************************************************************************/
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VOID vOutFifoW(
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VOID* p,
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ULONG v)
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{
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gcFifo--;
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if (gcFifo < 0)
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{
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gcFifo = 0;
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RIP("Incorrect FIFO wait count");
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}
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WRITE_PORT_USHORT(p, (USHORT)v);
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}
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/******************************Public*Routine******************************\
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* VOID vOutFifoPseudoD
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\**************************************************************************/
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VOID vOutFifoPseudoD(
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PDEV* ppdev,
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VOID* p,
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ULONG v)
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{
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ULONG ulMiscState;
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ASSERTDD(!(ppdev->flCaps & CAPS_MM_IO),
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"No pseudo 32-bit writes when using memory-mapped I/O");
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ASSERTDD(ppdev->iBitmapFormat == BMF_32BPP,
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"We're trying to do 32bpp output while not in 32bpp mode");
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IO_GP_WAIT(ppdev); // Wait so we don't interfere with any
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// pending commands waiting on the
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// FIFO
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IO_READ_SEL(ppdev, 6); // We'll be reading index 0xE
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IO_GP_WAIT(ppdev); // Wait until that's processed
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IO_RD_REG_DT(ppdev, ulMiscState); // Read ulMiscState
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ASSERTDD((ulMiscState & 0x10) == 0,
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"Register select flag is out of sync");
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gcFifo -= 2;
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if (gcFifo < 0)
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{
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gcFifo = 0;
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RIP("Incorrect FIFO wait count");
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}
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OUT_PSEUDO_DWORD(p, v);
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}
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/******************************Public*Routine******************************\
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* VOID vWriteFifoW
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\**************************************************************************/
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VOID vWriteFifoW(
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VOID* p,
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ULONG v)
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{
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gcFifo--;
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if (gcFifo < 0)
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{
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gcFifo = 0;
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RIP("Incorrect FIFO wait count");
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}
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WRITE_REGISTER_USHORT(p, (USHORT) v);
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}
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/******************************Public*Routine******************************\
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* VOID vWriteFifoD
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\**************************************************************************/
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VOID vWriteFifoD(
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VOID* p,
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ULONG v)
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{
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gcFifo--;
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if (gcFifo < 0)
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{
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gcFifo = 0;
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RIP("Incorrect FIFO wait count");
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}
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WRITE_REGISTER_ULONG(p, v);
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}
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/******************************Public*Routine******************************\
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* VOID vIoFifoWait
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\**************************************************************************/
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VOID vIoFifoWait(
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PDEV* ppdev,
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LONG level)
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{
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LONG i;
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ASSERTDD((level > 0) && (level <= 8), "Illegal wait level");
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gcFifo = level;
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for (i = LARGE_LOOP_COUNT; i != 0; i--)
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{
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if (!(IO_FIFO_BUSY(ppdev, level)))
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return;
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}
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RIP("vIoFifoWait timeout -- The hardware is in a funky state.");
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}
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/******************************Public*Routine******************************\
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* VOID vMmFifoWait
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\**************************************************************************/
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VOID vMmFifoWait(
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PDEV* ppdev,
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BYTE* pjMmBase,
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LONG level)
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{
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LONG i;
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// We only enabled MM I/O on the 864/964 and newer, so we can wait
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// for up to 13 FIFO slots:
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ASSERTDD((level > 0) && (level <= 13), "Illegal wait level");
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gcFifo = level;
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for (i = LARGE_LOOP_COUNT; i != 0; i--)
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{
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if (!(MM_FIFO_BUSY(ppdev, pjMmBase, level)))
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return;
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}
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RIP("vMmFifoWait timeout -- The hardware is in a funky state.");
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}
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/******************************Public*Routine******************************\
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* VOID vNwFifoWait
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\**************************************************************************/
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VOID vNwFifoWait(
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PDEV* ppdev,
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BYTE* pjMmBase,
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LONG level)
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{
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LONG i;
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ASSERTDD((level > 0) && (level <= 13), "Illegal wait level");
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gcFifo = level;
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for (i = LARGE_LOOP_COUNT; i != 0; i--)
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{
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if (!(NW_FIFO_BUSY(ppdev, pjMmBase, level)))
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return;
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}
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RIP("vNwFifoWait timeout -- The hardware is in a funky state.");
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}
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/******************************Public*Routine******************************\
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* VOID vDbgFakeWait
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\**************************************************************************/
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VOID vDbgFakeWait(
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PDEV* ppdev,
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BYTE* pjMmBase,
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LONG level)
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{
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gcFifo = level;
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}
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/******************************Public*Routine******************************\
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* VOID vIoGpWait
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\**************************************************************************/
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VOID vIoGpWait(
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PDEV* ppdev)
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{
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LONG i;
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gcFifo = (ppdev->flCaps & CAPS_16_ENTRY_FIFO) ? 16 : 8;
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for (i = LARGE_LOOP_COUNT; i != 0; i--)
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{
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if (!(IO_GP_STAT(ppdev) & HARDWARE_BUSY))
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return; // It isn't busy
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}
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RIP("vIoGpWait timeout -- The hardware is in a funky state.");
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}
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/******************************Public*Routine******************************\
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* VOID vNwGpWait
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\**************************************************************************/
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VOID vNwGpWait(
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PDEV* ppdev,
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BYTE* pjMmBase)
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{
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LONG i;
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gcFifo = 16;
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for (i = LARGE_LOOP_COUNT; i != 0; i--)
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{
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if (!NW_GP_BUSY(ppdev, pjMmBase))
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return; // It isn't busy
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}
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RIP("vNwGpWait timeout -- The hardware is in a funky state.");
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}
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/******************************Public*Routine******************************\
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* VOID vIoAllEmpty
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\**************************************************************************/
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VOID vIoAllEmpty(
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PDEV* ppdev)
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{
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LONG i;
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ASSERTDD(ppdev->flCaps & CAPS_16_ENTRY_FIFO,
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"Can't call ALL_EMPTY on chips with 8-deep FIFOs");
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gcFifo = 16;
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for (i = LARGE_LOOP_COUNT; i != 0; i--)
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{
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if (IO_GP_STAT(ppdev) & GP_ALL_EMPTY) // Not implemented on 911/924s
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return;
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}
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RIP("ALL_EMPTY timeout -- The hardware is in a funky state.");
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}
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/******************************Public*Routines*****************************\
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* UCHAR jInp() - INP()
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* USHORT wInpW() - INPW()
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* VOID vOutp() - OUTP()
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* VOID vOutpW() - OUTPW()
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*
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* Debug thunks for general I/O routines. This is used primarily to verify
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* that any code accessing the CRTC register has grabbed the CRTC critical
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* section (necessary because with GCAPS_ASYNCMOVE, DrvMovePointer calls
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* may happen at any time, and they need to access the CRTC register).
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*
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\**************************************************************************/
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UCHAR jInp(BYTE* pjIoBase, ULONG p)
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{
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if (((p == CRTC_INDEX) || (p == CRTC_DATA)) &&
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(!gbCrtcCriticalSection))
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{
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RIP("Must have acquired CRTC critical section to access CRTC register");
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}
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CP_EIEIO();
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return((UCHAR) READ_PORT_UCHAR(pjIoBase + (p)));
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}
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USHORT wInpW(BYTE* pjIoBase, ULONG p)
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{
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if (((p == CRTC_INDEX) || (p == CRTC_DATA)) &&
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(!gbCrtcCriticalSection))
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{
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RIP("Must have acquired CRTC critical section to access CRTC register");
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}
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CP_EIEIO();
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return(READ_PORT_USHORT(pjIoBase + (p)));
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}
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VOID vOutp(BYTE* pjIoBase, ULONG p, ULONG v)
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{
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if (((p == CRTC_INDEX) || (p == CRTC_DATA)) &&
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(!gbCrtcCriticalSection))
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{
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RIP("Must have acquired CRTC critical section to access CRTC register");
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}
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CP_EIEIO();
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WRITE_PORT_UCHAR((PUCHAR)((ULONG_PTR)(pjIoBase + p)), (UCHAR)(v));
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CP_EIEIO();
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}
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VOID vOutpW(BYTE* pjIoBase, ULONG p, ULONG v)
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{
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if (((p == CRTC_INDEX) || (p == CRTC_DATA)) &&
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(!gbCrtcCriticalSection))
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{
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RIP("Must have acquired CRTC critical section to access CRTC register");
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}
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CP_EIEIO();
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WRITE_PORT_USHORT(pjIoBase + (p), (USHORT)(v));
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CP_EIEIO();
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}
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/******************************Public*Routine******************************\
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* VOID vAcquireCrtc()
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* VOID vReleaseCrtc()
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*
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* Debug thunks for grabbing the CRTC register critical section.
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*
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\**************************************************************************/
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VOID vAcquireCrtc(PDEV* ppdev)
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{
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EngAcquireSemaphore(ppdev->csCrtc);
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if (gbCrtcCriticalSection)
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RIP("Had already acquired Critical Section");
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gbCrtcCriticalSection = TRUE;
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}
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VOID vReleaseCrtc(PDEV* ppdev)
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{
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// 80x/805i/928 and 928PCI chips have a bug where if I/O registers
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// are left unlocked after accessing them, writes to memory with
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// similar addresses can cause writes to I/O registers. The problem
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// registers are 0x40, 0x58, 0x59 and 0x5c. We will simply always
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// leave the index set to an innocuous register (namely, the text
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// mode cursor start scan line):
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OUTP(ppdev->pjIoBase, CRTC_INDEX, 0xa);
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if (!gbCrtcCriticalSection)
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RIP("Hadn't yet acquired Critical Section");
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gbCrtcCriticalSection = FALSE;
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EngReleaseSemaphore(ppdev->csCrtc);
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}
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////////////////////////////////////////////////////////////////////////////
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#endif // DBG
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